drm/amdgpu/gfx10: implement mqd functions of gfx/compute eng v2

Refine the existing gfx/compute mqd functions, and add them
to engine mqd layer.

v2: rebase fix.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index f2dd53f2af6148ec386594a7052fd36a4199285a..cc70594d7e4cc9143e7793e4a8aaae6d68d99ae5 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3485,6 +3485,7 @@ static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
+static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev);
 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
                                 struct amdgpu_cu_info *cu_info);
 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
@@ -6564,10 +6565,10 @@ static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
        }
 }
 
-static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
+static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
+                                 struct amdgpu_mqd_prop *prop)
 {
-       struct amdgpu_device *adev = ring->adev;
-       struct v10_gfx_mqd *mqd = ring->mqd_ptr;
+       struct v10_gfx_mqd *mqd = m;
        uint64_t hqd_gpu_addr, wb_gpu_addr;
        uint32_t tmp;
        uint32_t rb_bufsz;
@@ -6577,8 +6578,8 @@ static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
        mqd->cp_gfx_hqd_wptr_hi = 0;
 
        /* set the pointer to the MQD */
-       mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
-       mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
+       mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
+       mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
 
        /* set up mqd control */
        tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
@@ -6604,23 +6605,23 @@ static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
        mqd->cp_gfx_hqd_quantum = tmp;
 
        /* set up gfx hqd base. this is similar as CP_RB_BASE */
-       hqd_gpu_addr = ring->gpu_addr >> 8;
+       hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
        mqd->cp_gfx_hqd_base = hqd_gpu_addr;
        mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
 
        /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
-       wb_gpu_addr = ring->rptr_gpu_addr;
+       wb_gpu_addr = prop->rptr_gpu_addr;
        mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
        mqd->cp_gfx_hqd_rptr_addr_hi =
                upper_32_bits(wb_gpu_addr) & 0xffff;
 
        /* set up rb_wptr_poll addr */
-       wb_gpu_addr = ring->wptr_gpu_addr;
+       wb_gpu_addr = prop->wptr_gpu_addr;
        mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
        mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
 
        /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
-       rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
+       rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
        tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
        tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
        tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
@@ -6631,9 +6632,9 @@ static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
 
        /* set up cp_doorbell_control */
        tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
-       if (ring->use_doorbell) {
+       if (prop->use_doorbell) {
                tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
-                                   DOORBELL_OFFSET, ring->doorbell_index);
+                                   DOORBELL_OFFSET, prop->doorbell_index);
                tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
                                    DOORBELL_EN, 1);
        } else
@@ -6641,13 +6642,7 @@ static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
                                    DOORBELL_EN, 0);
        mqd->cp_rb_doorbell_control = tmp;
 
-       /*if there are 2 gfx rings, set the lower doorbell range of the first ring,
-        *otherwise the range of the second ring will override the first ring */
-       if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
-               gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
-
        /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
-       ring->wptr = 0;
        mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
 
        /* active the queue */
@@ -6715,7 +6710,16 @@ static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
                memset((void *)mqd, 0, sizeof(*mqd));
                mutex_lock(&adev->srbm_mutex);
                nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
-               gfx_v10_0_gfx_mqd_init(ring);
+               amdgpu_ring_init_mqd(ring);
+
+               /*
+                * if there are 2 gfx rings, set the lower doorbell
+                * range of the first ring, otherwise the range of
+                * the second ring will override the first ring
+                */
+               if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
+                       gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
+
 #ifdef BRING_UP_DEBUG
                gfx_v10_0_gfx_queue_init_register(ring);
 #endif
@@ -6808,23 +6812,10 @@ done:
        return r;
 }
 
-static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
+static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
+                                     struct amdgpu_mqd_prop *prop)
 {
-       struct amdgpu_device *adev = ring->adev;
-
-       if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
-               if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
-                       mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
-                       mqd->cp_hqd_queue_priority =
-                               AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
-               }
-       }
-}
-
-static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
-{
-       struct amdgpu_device *adev = ring->adev;
-       struct v10_compute_mqd *mqd = ring->mqd_ptr;
+       struct v10_compute_mqd *mqd = m;
        uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
        uint32_t tmp;
 
@@ -6836,7 +6827,7 @@ static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
        mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
        mqd->compute_misc_reserved = 0x00000003;
 
-       eop_base_addr = ring->eop_gpu_addr >> 8;
+       eop_base_addr = prop->eop_gpu_addr >> 8;
        mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
        mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
 
@@ -6850,9 +6841,9 @@ static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
        /* enable doorbell? */
        tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
 
-       if (ring->use_doorbell) {
+       if (prop->use_doorbell) {
                tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
-                                   DOORBELL_OFFSET, ring->doorbell_index);
+                                   DOORBELL_OFFSET, prop->doorbell_index);
                tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
                                    DOORBELL_EN, 1);
                tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
@@ -6867,15 +6858,14 @@ static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
        mqd->cp_hqd_pq_doorbell_control = tmp;
 
        /* disable the queue if it's active */
-       ring->wptr = 0;
        mqd->cp_hqd_dequeue_request = 0;
        mqd->cp_hqd_pq_rptr = 0;
        mqd->cp_hqd_pq_wptr_lo = 0;
        mqd->cp_hqd_pq_wptr_hi = 0;
 
        /* set the pointer to the MQD */
-       mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
-       mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
+       mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
+       mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
 
        /* set MQD vmid to 0 */
        tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
@@ -6883,14 +6873,14 @@ static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
        mqd->cp_mqd_control = tmp;
 
        /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
-       hqd_gpu_addr = ring->gpu_addr >> 8;
+       hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
        mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
        mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
 
        /* set up the HQD, this is similar to CP_RB0_CNTL */
        tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
        tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
-                           (order_base_2(ring->ring_size / 4) - 1));
+                           (order_base_2(prop->queue_size / 4) - 1));
        tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
                            ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
 #ifdef __BIG_ENDIAN
@@ -6903,22 +6893,22 @@ static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
        mqd->cp_hqd_pq_control = tmp;
 
        /* set the wb address whether it's enabled or not */
-       wb_gpu_addr = ring->rptr_gpu_addr;
+       wb_gpu_addr = prop->rptr_gpu_addr;
        mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
        mqd->cp_hqd_pq_rptr_report_addr_hi =
                upper_32_bits(wb_gpu_addr) & 0xffff;
 
        /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
-       wb_gpu_addr = ring->wptr_gpu_addr;
+       wb_gpu_addr = prop->wptr_gpu_addr;
        mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
        mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
 
        tmp = 0;
        /* enable the doorbell if requested */
-       if (ring->use_doorbell) {
+       if (prop->use_doorbell) {
                tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
                tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
-                               DOORBELL_OFFSET, ring->doorbell_index);
+                               DOORBELL_OFFSET, prop->doorbell_index);
 
                tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
                                    DOORBELL_EN, 1);
@@ -6931,7 +6921,6 @@ static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
        mqd->cp_hqd_pq_doorbell_control = tmp;
 
        /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
-       ring->wptr = 0;
        mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
 
        /* set the vmid for the queue */
@@ -6947,13 +6936,10 @@ static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
        mqd->cp_hqd_ib_control = tmp;
 
        /* set static priority for a compute queue/ring */
-       gfx_v10_0_compute_mqd_set_priority(ring, mqd);
+       mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
+       mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
 
-       /* map_queues packet doesn't need activate the queue,
-        * so only kiq need set this field.
-        */
-       if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
-               mqd->cp_hqd_active = 1;
+       mqd->cp_hqd_active = prop->hqd_active;
 
        return 0;
 }
@@ -7094,7 +7080,7 @@ static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
                memset((void *)mqd, 0, sizeof(*mqd));
                mutex_lock(&adev->srbm_mutex);
                nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
-               gfx_v10_0_compute_mqd_init(ring);
+               amdgpu_ring_init_mqd(ring);
                gfx_v10_0_kiq_init_register(ring);
                nv_grbm_select(adev, 0, 0, 0, 0);
                mutex_unlock(&adev->srbm_mutex);
@@ -7116,7 +7102,7 @@ static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
                memset((void *)mqd, 0, sizeof(*mqd));
                mutex_lock(&adev->srbm_mutex);
                nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
-               gfx_v10_0_compute_mqd_init(ring);
+               amdgpu_ring_init_mqd(ring);
                nv_grbm_select(adev, 0, 0, 0, 0);
                mutex_unlock(&adev->srbm_mutex);
 
@@ -7799,6 +7785,7 @@ static int gfx_v10_0_early_init(void *handle)
        gfx_v10_0_set_irq_funcs(adev);
        gfx_v10_0_set_gds_init(adev);
        gfx_v10_0_set_rlc_funcs(adev);
+       gfx_v10_0_set_mqd_funcs(adev);
 
        /* init rlcg reg access ctrl */
        gfx_v10_0_init_rlcg_reg_access_ctrl(adev);
@@ -9581,6 +9568,20 @@ static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
        adev->gds.oa_size = 16;
 }
 
+static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev)
+{
+       /* set gfx eng mqd */
+       adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =
+               sizeof(struct v10_gfx_mqd);
+       adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
+               gfx_v10_0_gfx_mqd_init;
+       /* set compute eng mqd */
+       adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
+               sizeof(struct v10_compute_mqd);
+       adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
+               gfx_v10_0_compute_mqd_init;
+}
+
 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
                                                          u32 bitmap)
 {