cooling-maps {
map0 {
/* Corresponds to 500MHz */
- cooling-device = <&cpu0 5 5>;
+ cooling-device = <&cpu0 5 5>,
+ <&cpu1 5 5>;
};
map1 {
/* Corresponds to 200MHz */
- cooling-device = <&cpu0 8 8>;
+ cooling-device = <&cpu0 8 8>,
+ <&cpu1 8 8>;
};
};
};
cooling-maps {
map0 {
/* Correspond to 500MHz at freq_table */
- cooling-device = <&cpu0 5 5>;
+ cooling-device = <&cpu0 5 5>,
+ <&cpu1 5 5>;
};
map1 {
/* Correspond to 200MHz at freq_table */
- cooling-device = <&cpu0 8 8>;
+ cooling-device = <&cpu0 8 8>,
+ <&cpu1 8 8>;
};
};
};
cooling-maps {
map0 {
/* Corresponds to 500MHz */
- cooling-device = <&cpu0 5 5>;
+ cooling-device = <&cpu0 5 5>,
+ <&cpu1 5 5>;
};
map1 {
/* Corresponds to 200MHz */
- cooling-device = <&cpu0 8 8>;
+ cooling-device = <&cpu0 8 8>,
+ <&cpu1 8 8>;
};
};
};
};
hsotg: hsotg@12480000 {
- compatible = "snps,dwc2";
+ compatible = "samsung,s3c6400-hsotg", "snps,dwc2";
reg = <0x12480000 0x20000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_USBOTG>;
cooling-maps {
map0 {
/* Corresponds to 800MHz at freq_table */
- cooling-device = <&cpu0 2 2>;
+ cooling-device = <&cpu0 2 2>, <&cpu1 2 2>;
};
map1 {
/* Corresponds to 200MHz at freq_table */
- cooling-device = <&cpu0 4 4>;
+ cooling-device = <&cpu0 4 4>, <&cpu1 4 4>;
};
};
};
#cooling-cells = <2>; /* min followed by max */
};
- cpu@901 {
+ cpu1: cpu@901 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0x901>;
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1150000>;
+ opp-suspend;
};
};
};
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
+ opp-suspend;
};
};
};
cooling-maps {
map0 {
/* Corresponds to 800MHz at freq_table */
- cooling-device = <&cpu0 7 7>;
+ cooling-device = <&cpu0 7 7>, <&cpu1 7 7>,
+ <&cpu2 7 7>, <&cpu3 7 7>;
};
map1 {
/* Corresponds to 200MHz at freq_table */
- cooling-device = <&cpu0 13 13>;
+ cooling-device = <&cpu0 13 13>,
+ <&cpu1 13 13>,
+ <&cpu2 13 13>,
+ <&cpu3 13 13>;
};
};
};
};
s5m8767_osc: clocks {
+ compatible = "samsung,s5m8767-clk";
#clock-cells = <1>;
clock-output-names = "s5m8767_ap",
"s5m8767_cp", "s5m8767_bt";
cooling-maps {
map0 {
/* Corresponds to 800MHz at freq_table */
- cooling-device = <&cpu0 7 7>;
+ cooling-device = <&cpu0 7 7>, <&cpu1 7 7>,
+ <&cpu2 7 7>, <&cpu3 7 7>;
};
map1 {
/* Corresponds to 200MHz at freq_table */
- cooling-device = <&cpu0 13 13>;
+ cooling-device = <&cpu0 13 13>,
+ <&cpu1 13 13>,
+ <&cpu2 13 13>,
+ <&cpu3 13 13>;
};
};
};
cooling-maps {
cooling_map0: map0 {
/* Corresponds to 800MHz at freq_table */
- cooling-device = <&cpu0 7 7>;
+ cooling-device = <&cpu0 7 7>, <&cpu1 7 7>,
+ <&cpu2 7 7>, <&cpu3 7 7>;
};
cooling_map1: map1 {
/* Corresponds to 200MHz at freq_table */
- cooling-device = <&cpu0 13 13>;
+ cooling-device = <&cpu0 13 13>,
+ <&cpu1 13 13>,
+ <&cpu2 13 13>,
+ <&cpu3 13 13>;
};
};
};
cooling-maps {
map0 {
trip = <&cpu_alert1>;
- cooling-device = <&cpu0 9 9>;
+ cooling-device = <&cpu0 9 9>, <&cpu1 9 9>,
+ <&cpu2 9 9>, <&cpu3 9 9>,
+ <&fan0 1 2>;
};
map1 {
trip = <&cpu_alert2>;
- cooling-device = <&cpu0 15 15>;
+ cooling-device = <&cpu0 15 15>,
+ <&cpu1 15 15>,
+ <&cpu2 15 15>,
+ <&cpu3 15 15>,
+ <&fan0 2 3>;
};
map2 {
trip = <&cpu_alert0>;
cooling-device = <&fan0 0 1>;
};
- map3 {
- trip = <&cpu_alert1>;
- cooling-device = <&fan0 1 2>;
- };
- map4 {
- trip = <&cpu_alert2>;
- cooling-device = <&fan0 2 3>;
- };
};
};
};
};
&cooling_map0 {
- cooling-device = <&cpu0 9 9>;
+ cooling-device = <&cpu0 9 9>, <&cpu1 9 9>,
+ <&cpu2 9 9>, <&cpu3 9 9>;
};
&cooling_map1 {
- cooling-device = <&cpu0 15 15>;
+ cooling-device = <&cpu0 15 15>, <&cpu1 15 15>,
+ <&cpu2 15 15>, <&cpu3 15 15>;
};
#cooling-cells = <2>; /* min followed by max */
};
- cpu@a01 {
+ cpu1: cpu@a01 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0xA01>;
#cooling-cells = <2>; /* min followed by max */
};
- cpu@a02 {
+ cpu2: cpu@a02 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0xA02>;
#cooling-cells = <2>; /* min followed by max */
};
- cpu@a03 {
+ cpu3: cpu@a03 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0xA03>;
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1050000>;
+ opp-suspend;
};
};
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <1000000>;
+ opp-suspend;
};
};
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/input.h>
+#include <dt-bindings/clock/samsung,s2mps11.h>
#include "exynos5250.dtsi"
/ {
};
};
-&dp {
- status = "okay";
- samsung,color-space = <0>;
- samsung,color-depth = <1>;
- samsung,link-rate = <0x0a>;
- samsung,lane-count = <4>;
-
- display-timings {
- native-mode = <&timing0>;
-
- timing0: timing {
- /* 2560x1600 DP panel */
- clock-frequency = <50000>;
- hactive = <2560>;
- vactive = <1600>;
- hfront-porch = <48>;
- hback-porch = <80>;
- hsync-len = <32>;
- vback-porch = <16>;
- vfront-porch = <8>;
- vsync-len = <6>;
- };
- };
-};
-
&fimd {
status = "okay";
};
<&gpx2 4 GPIO_ACTIVE_HIGH>,
<&gpx2 5 GPIO_ACTIVE_HIGH>;
+ s5m8767_osc: clocks {
+ compatible = "samsung,s5m8767-clk";
+ #clock-cells = <1>;
+ clock-output-names = "s5m8767_ap", "unused1", "unused2";
+ };
+
regulators {
ldo1_reg: LDO1 {
regulator-name = "VDD_ALIVE_1.0V";
};
&rtc {
+ clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>;
+ clock-names = "rtc", "rtc_src";
status = "okay";
};
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>; /* min followed by max */
};
- cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <1>;
cooling-maps {
map0 {
/* Corresponds to 800MHz at freq_table */
- cooling-device = <&cpu0 9 9>;
+ cooling-device = <&cpu0 9 9>, <&cpu1 9 9>;
};
map1 {
/* Corresponds to 200MHz at freq_table */
- cooling-device = <&cpu0 15 15>;
+ cooling-device = <&cpu0 15 15>,
+ <&cpu1 15 15>;
};
};
};
pinctrl-0 = <&s2mps11_irq>;
s2mps11_osc: clocks {
+ compatible = "samsung,s2mps11-clk";
#clock-cells = <1>;
clock-output-names = "s2mps11_ap",
"s2mps11_cp", "s2mps11_bt";
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
};
+
+ sd2_wp: sd2-wp {
+ samsung,pins = "gpc4-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
+ };
};
&pinctrl_2 {
reg = <0x66>;
s2mps11_osc: clocks {
+ compatible = "samsung,s2mps11-clk";
#clock-cells = <1>;
clock-output-names = "s2mps11_ap",
"s2mps11_cp", "s2mps11_bt";
// SPDX-License-Identifier: GPL-2.0
/*
- * Hardkernel Odroid XU3/XU4/HC1 boards core device tree source
+ * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source
*
* Copyright (c) 2017 Marek Szyprowski
* Copyright (c) 2013-2017 Samsung Electronics Co., Ltd.
pinctrl-0 = <&s2mps11_irq>;
s2mps11_osc: clocks {
+ compatible = "samsung,s2mps11-clk";
#clock-cells = <1>;
clock-output-names = "s2mps11_ap",
"s2mps11_cp", "s2mps11_bt";
ldo13_reg: LDO13 {
regulator-name = "vddq_mmc2";
- regulator-min-microvolt = <2800000>;
+ regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2800000>;
};
samsung,dw-mshc-sdr-timing = <0 4>;
samsung,dw-mshc-ddr-timing = <0 2>;
pinctrl-names = "default";
- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
+ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>;
bus-width = <4>;
cap-sd-highspeed;
+ max-frequency = <200000000>;
vmmc-supply = <&ldo19_reg>;
vqmmc-supply = <&ldo13_reg>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ sd-uhs-ddr50;
};
&nocp_mem0_0 {
*/
map0 {
trip = <&cpu0_alert0>;
- cooling-device = <&cpu0 0 2>;
- };
- map1 {
- trip = <&cpu0_alert0>;
- cooling-device = <&cpu4 0 2>;
+ cooling-device = <&cpu0 0 2>,
+ <&cpu1 0 2>,
+ <&cpu2 0 2>,
+ <&cpu3 0 2>,
+ <&cpu4 0 2>,
+ <&cpu5 0 2>,
+ <&cpu6 0 2>,
+ <&cpu7 0 2>;
};
/*
* When reaching cpu0_alert1, reduce CPU
* further, down to 600 MHz (12 steps for big,
* 7 steps for LITTLE).
*/
- map2 {
- trip = <&cpu0_alert1>;
- cooling-device = <&cpu0 3 7>;
- };
- map3 {
+ map1 {
trip = <&cpu0_alert1>;
- cooling-device = <&cpu4 3 12>;
+ cooling-device = <&cpu0 3 7>,
+ <&cpu1 3 7>,
+ <&cpu2 3 7>,
+ <&cpu3 3 7>,
+ <&cpu4 3 12>,
+ <&cpu5 3 12>,
+ <&cpu6 3 12>,
+ <&cpu7 3 12>;
};
};
};
cooling-maps {
map0 {
trip = <&cpu1_alert0>;
- cooling-device = <&cpu0 0 2>;
+ cooling-device = <&cpu0 0 2>,
+ <&cpu1 0 2>,
+ <&cpu2 0 2>,
+ <&cpu3 0 2>,
+ <&cpu4 0 2>,
+ <&cpu5 0 2>,
+ <&cpu6 0 2>,
+ <&cpu7 0 2>;
};
map1 {
- trip = <&cpu1_alert0>;
- cooling-device = <&cpu4 0 2>;
- };
- map2 {
- trip = <&cpu1_alert1>;
- cooling-device = <&cpu0 3 7>;
- };
- map3 {
trip = <&cpu1_alert1>;
- cooling-device = <&cpu4 3 12>;
+ cooling-device = <&cpu0 3 7>,
+ <&cpu1 3 7>,
+ <&cpu2 3 7>,
+ <&cpu3 3 7>,
+ <&cpu4 3 12>,
+ <&cpu5 3 12>,
+ <&cpu6 3 12>,
+ <&cpu7 3 12>;
};
};
};
cooling-maps {
map0 {
trip = <&cpu2_alert0>;
- cooling-device = <&cpu0 0 2>;
+ cooling-device = <&cpu0 0 2>,
+ <&cpu1 0 2>,
+ <&cpu2 0 2>,
+ <&cpu3 0 2>,
+ <&cpu4 0 2>,
+ <&cpu5 0 2>,
+ <&cpu6 0 2>,
+ <&cpu7 0 2>;
};
map1 {
- trip = <&cpu2_alert0>;
- cooling-device = <&cpu4 0 2>;
- };
- map2 {
- trip = <&cpu2_alert1>;
- cooling-device = <&cpu0 3 7>;
- };
- map3 {
trip = <&cpu2_alert1>;
- cooling-device = <&cpu4 3 12>;
+ cooling-device = <&cpu0 3 7>,
+ <&cpu1 3 7>,
+ <&cpu2 3 7>,
+ <&cpu3 3 7>,
+ <&cpu4 3 12>,
+ <&cpu5 3 12>,
+ <&cpu6 3 12>,
+ <&cpu7 3 12>;
};
};
};
cooling-maps {
map0 {
trip = <&cpu3_alert0>;
- cooling-device = <&cpu0 0 2>;
+ cooling-device = <&cpu0 0 2>,
+ <&cpu1 0 2>,
+ <&cpu2 0 2>,
+ <&cpu3 0 2>,
+ <&cpu4 0 2>,
+ <&cpu5 0 2>,
+ <&cpu6 0 2>,
+ <&cpu7 0 2>;
};
map1 {
- trip = <&cpu3_alert0>;
- cooling-device = <&cpu4 0 2>;
- };
- map2 {
- trip = <&cpu3_alert1>;
- cooling-device = <&cpu0 3 7>;
- };
- map3 {
trip = <&cpu3_alert1>;
- cooling-device = <&cpu4 3 12>;
+ cooling-device = <&cpu0 3 7>,
+ <&cpu1 3 7>,
+ <&cpu2 3 7>,
+ <&cpu3 3 7>,
+ <&cpu4 3 12>,
+ <&cpu5 3 12>,
+ <&cpu6 3 12>,
+ <&cpu7 3 12>;
};
};
};
"Speakers", "SPKL",
"Speakers", "SPKR";
- assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>,
- <&clock CLK_MOUT_EPLL>,
+ assigned-clocks = <&clock CLK_MOUT_EPLL>,
<&clock CLK_MOUT_MAU_EPLL>,
<&clock CLK_MOUT_USER_MAU_EPLL>,
<&clock_audss EXYNOS_MOUT_AUDSS>,
<&clock_audss EXYNOS_DOUT_AUD_BUS>,
<&clock_audss EXYNOS_DOUT_I2S>;
- assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>,
- <&clock CLK_FOUT_EPLL>,
+ assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
<&clock CLK_MOUT_EPLL>,
<&clock CLK_MOUT_MAU_EPLL>,
<&clock CLK_MAU_EPLL>,
<0>,
<0>,
<0>,
- <0>,
<196608001>,
<(196608002 / 2)>,
<196608000>;
&i2s0 {
status = "okay";
+ assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>;
+ assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>;
};
// SPDX-License-Identifier: GPL-2.0
/*
- * Hardkernel Odroid XU3 board device tree source
+ * Hardkernel Odroid XU3/XU3-Lite/XU4 boards common device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*/
map3 {
trip = <&cpu0_alert3>;
- cooling-device = <&cpu0 0 2>;
- };
- map4 {
- trip = <&cpu0_alert3>;
- cooling-device = <&cpu4 0 2>;
+ cooling-device = <&cpu0 0 2>,
+ <&cpu1 0 2>,
+ <&cpu2 0 2>,
+ <&cpu3 0 2>,
+ <&cpu4 0 2>,
+ <&cpu5 0 2>,
+ <&cpu6 0 2>,
+ <&cpu7 0 2>;
};
/*
* When reaching cpu0_alert4, reduce CPU
* further, down to 600 MHz (12 steps for big,
* 7 steps for LITTLE).
*/
- map5 {
- trip = <&cpu0_alert4>;
- cooling-device = <&cpu0 3 7>;
- };
- map6 {
+ map4 {
trip = <&cpu0_alert4>;
- cooling-device = <&cpu4 3 12>;
+ cooling-device = <&cpu0 3 7>,
+ <&cpu1 3 7>,
+ <&cpu2 3 7>,
+ <&cpu3 3 7>,
+ <&cpu4 3 12>,
+ <&cpu5 3 12>,
+ <&cpu6 3 12>,
+ <&cpu7 3 12>;
};
};
};
};
map3 {
trip = <&cpu1_alert3>;
- cooling-device = <&cpu0 0 2>;
+ cooling-device = <&cpu0 0 2>,
+ <&cpu1 0 2>,
+ <&cpu2 0 2>,
+ <&cpu3 0 2>,
+ <&cpu4 0 2>,
+ <&cpu5 0 2>,
+ <&cpu6 0 2>,
+ <&cpu7 0 2>;
};
map4 {
- trip = <&cpu1_alert3>;
- cooling-device = <&cpu4 0 2>;
- };
- map5 {
- trip = <&cpu1_alert4>;
- cooling-device = <&cpu0 3 7>;
- };
- map6 {
trip = <&cpu1_alert4>;
- cooling-device = <&cpu4 3 12>;
+ cooling-device = <&cpu0 3 7>,
+ <&cpu1 3 7>,
+ <&cpu2 3 7>,
+ <&cpu3 3 7>,
+ <&cpu4 3 12>,
+ <&cpu5 3 12>,
+ <&cpu6 3 12>,
+ <&cpu7 3 12>;
};
};
};
};
map3 {
trip = <&cpu2_alert3>;
- cooling-device = <&cpu0 0 2>;
+ cooling-device = <&cpu0 0 2>,
+ <&cpu1 0 2>,
+ <&cpu2 0 2>,
+ <&cpu3 0 2>,
+ <&cpu4 0 2>,
+ <&cpu5 0 2>,
+ <&cpu6 0 2>,
+ <&cpu7 0 2>;
};
map4 {
- trip = <&cpu2_alert3>;
- cooling-device = <&cpu4 0 2>;
- };
- map5 {
- trip = <&cpu2_alert4>;
- cooling-device = <&cpu0 3 7>;
- };
- map6 {
trip = <&cpu2_alert4>;
- cooling-device = <&cpu4 3 12>;
+ cooling-device = <&cpu0 3 7>,
+ <&cpu1 3 7>,
+ <&cpu2 3 7>,
+ <&cpu3 3 7>,
+ <&cpu4 3 12>,
+ <&cpu5 3 12>,
+ <&cpu6 3 12>,
+ <&cpu7 3 12>;
};
};
};
};
map3 {
trip = <&cpu3_alert3>;
- cooling-device = <&cpu0 0 2>;
+ cooling-device = <&cpu0 0 2>,
+ <&cpu1 0 2>,
+ <&cpu2 0 2>,
+ <&cpu3 0 2>,
+ <&cpu4 0 2>,
+ <&cpu5 0 2>,
+ <&cpu6 0 2>,
+ <&cpu7 0 2>;
};
map4 {
- trip = <&cpu3_alert3>;
- cooling-device = <&cpu4 0 2>;
- };
- map5 {
- trip = <&cpu3_alert4>;
- cooling-device = <&cpu0 3 7>;
- };
- map6 {
trip = <&cpu3_alert4>;
- cooling-device = <&cpu4 3 12>;
+ cooling-device = <&cpu0 3 7>,
+ <&cpu1 3 7>,
+ <&cpu2 3 7>,
+ <&cpu3 3 7>,
+ <&cpu4 3 12>,
+ <&cpu5 3 12>,
+ <&cpu6 3 12>,
+ <&cpu7 3 12>;
};
};
};
cap-mmc-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
+ max-frequency = <200000000>;
vmmc-supply = <&ldo18_reg>;
vqmmc-supply = <&ldo3_reg>;
};
compatible = "samsung,odroid-xu3-audio";
model = "Odroid-XU4";
- assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>,
- <&clock CLK_MOUT_EPLL>,
+ assigned-clocks = <&clock CLK_MOUT_EPLL>,
<&clock CLK_MOUT_MAU_EPLL>,
<&clock CLK_MOUT_USER_MAU_EPLL>,
<&clock_audss EXYNOS_MOUT_AUDSS>,
<&clock_audss EXYNOS_DOUT_AUD_BUS>,
<&clock_audss EXYNOS_DOUT_I2S>;
- assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>,
- <&clock CLK_FOUT_EPLL>,
+ assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
<&clock CLK_MOUT_EPLL>,
<&clock CLK_MOUT_MAU_EPLL>,
<&clock CLK_MAU_EPLL>,
<0>,
<0>,
<0>,
- <0>,
<196608001>,
<(196608002 / 2)>,
<196608000>;
&i2s0 {
status = "okay";
+ assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>;
+ assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>;
};
&pwm {
samsung,lcd-wb;
};
};
+
+ jpeg_codec: jpeg-codec@fb600000 {
+ compatible = "samsung,s5pv210-jpeg";
+ reg = <0xfb600000 0x1000>;
+ interrupt-parent = <&vic2>;
+ interrupts = <8>;
+ clocks = <&clocks CLK_JPEG>;
+ clock-names = "jpeg";
+ };
};
};