arm64: dts: mba8xx: Add PCIe support

Add PCIe support for TQMa8Xx on MBa8Xx board.

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/mba8xx.dtsi b/arch/arm64/boot/dts/freescale/mba8xx.dtsi
index 276d1683b03bb0fa431aac63b337b46d8fc0e4be..117f65728319161cb1e8a05f24203d909c405f5b 100644 (file)
--- a/arch/arm64/boot/dts/freescale/mba8xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/mba8xx.dtsi
@@ -36,6 +36,13 @@
                stdout-path = &lpuart1;
        };
 
+       /* Non-controllable PCIe reference clock generator */
+       pcie_refclk: clock-pcie-ref {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <100000000>;
+       };
+
        gpio-keys {
                compatible = "gpio-keys";
                pinctrl-names = "default";
@@ -208,6 +215,12 @@
        status = "okay";
 };
 
+&hsio_phy {
+       fsl,hsio-cfg = "pciea-x2-pcieb";
+       fsl,refclk-pad-mode = "input";
+       status = "okay";
+};
+
 &i2c1 {
        tlv320aic3x04: audio-codec@18 {
                compatible = "ti,tlv320aic32x4";
@@ -309,7 +322,16 @@
                          "", "", "", "";
 };
 
-/* TODO: Mini-PCIe */
+&pcieb {
+       phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>;
+       phy-names = "pcie-phy";
+       pinctrl-0 = <&pinctrl_pcieb>;
+       pinctrl-names = "default";
+       reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
+       disable-gpio = <&expander 7 GPIO_ACTIVE_LOW>;
+       vpcie-supply = <&reg_pcie_1v5>;
+       status = "okay";
+};
 
 &sai1 {
        assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
@@ -467,10 +489,10 @@
                fsl,pins = <IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19      0x00000020>;
        };
 
-       pinctrl_pcieb: pcieagrp {
-               fsl,pins = <IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00  0x06000041>,
-                          <IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000041>,
-                          <IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02   0x04000041>;
+       pinctrl_pcieb: pciebgrp {
+               fsl,pins = <IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00          0x06000041>,
+                          <IMX8QXP_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B     0x06000041>,
+                          <IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02           0x04000041>;
        };
 
        pinctrl_reg_pcie_1v5: regpcie1v5grp {