drm/amd/display: revert removing otg toggle w/a back when no active display

w/a use case:
- dual display, compliance, toggling between the displays
- switching between 120Hz 420 -> 144Hz 444 and vice versa
- switching between 144Hz -> 60Hz TMDS or vice versa

It'd typically involve TMDS in some capacity since that's the only link
signal we leave the OTG running but DIO/PHY off you can hit this in
cases where you have multiple displays as well it syncs with the first
active OTG, so if you had OTG[0] mapped and FIFO off you'd hit it even
if OTG[1] was mapped and had FIFO

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
index 9e0fa01ecb795619c3d920306e1634e2c13bb674..439414ef464a03adbb2b92fd8ba6827051530a9c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
@@ -312,13 +312,11 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
        }
 
        if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
+               dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);
+
                clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
-               if (all_active_disps != 0) {
-                       dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);
-                       dcn35_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
-                       dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);
-               } else
-                       dcn35_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
+               dcn35_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
+               dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);
 
                update_dispclk = true;
        }

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
index 786b62ab8d0fca3d55daf91f8cd24d315c733f05..d6db9d7fced2e04758c175b14f5abbacbcd5c981 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
@@ -475,14 +475,14 @@ int dcn35_smu_get_ips_supported(struct clk_mgr_internal *clk_mgr)
                        VBIOSSMC_MSG_QueryIPS2Support,
                        0);
 
-       smu_print("%s: VBIOSSMC_MSG_QueryIPS2Support return = %x\n", __func__, retv);
+       //smu_print("%s: VBIOSSMC_MSG_QueryIPS2Support return = %x\n", __func__, retv);
        return retv;
 }
 
 void dcn35_smu_write_ips_scratch(struct clk_mgr_internal *clk_mgr, uint32_t param)
 {
        REG_WRITE(MP1_SMN_C2PMSG_71, param);
-       smu_print("%s: write_ips_scratch = %x\n", __func__, param);
+       //smu_print("%s: write_ips_scratch = %x\n", __func__, param);
 }
 
 uint32_t dcn35_smu_read_ips_scratch(struct clk_mgr_internal *clk_mgr)
@@ -490,6 +490,6 @@ uint32_t dcn35_smu_read_ips_scratch(struct clk_mgr_internal *clk_mgr)
        uint32_t retv;
 
        retv = REG_READ(MP1_SMN_C2PMSG_71);
-       smu_print("%s: dcn35_smu_read_ips_scratch = %x\n",  __func__, retv);
+       //smu_print("%s: dcn35_smu_read_ips_scratch = %x\n",  __func__, retv);
        return retv;
 }