pinctrl: intel: Add a generic Intel pin control platform driver

New generations of Intel platforms will provide better description
of the pin control devices in the ACPI tables. Hence, we may provide
a generic pin control platform driver to cover all of them. Currently
the following Intel SoCs / platforms require this to be functional:
- Lunar Lake

Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig
index 44b022d8aee1ef4ae93474b11631f490eb7ba7fe..d9bdd0e0e8a2bf4a670a2115bfe3808eeafbac13 100644 (file)
--- a/drivers/pinctrl/intel/Kconfig
+++ b/drivers/pinctrl/intel/Kconfig
@@ -37,6 +37,16 @@ config PINCTRL_INTEL
        select GPIOLIB
        select GPIOLIB_IRQCHIP
 
+config PINCTRL_INTEL_PLATFORM
+       tristate "Intel pinctrl and GPIO platform driver"
+       depends on ACPI
+       select PINCTRL_INTEL
+       help
+         This pinctrl driver provides an interface that allows configuring
+         of Intel PCH pins and using them as GPIOs. Currently the following
+         Intel SoCs / platforms require this to be functional:
+         - Lunar Lake
+
 config PINCTRL_ALDERLAKE
        tristate "Intel Alder Lake pinctrl and GPIO driver"
        select PINCTRL_INTEL

diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile
index f6d30f2d973a01028890fa1bc3963f854a2f07ab..96c93ed4bd58042edd1fab6305e862ff833b8b7e 100644 (file)
--- a/drivers/pinctrl/intel/Makefile
+++ b/drivers/pinctrl/intel/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_TANGIER)           += pinctrl-tangier.o
 obj-$(CONFIG_PINCTRL_MERRIFIELD)       += pinctrl-merrifield.o
 obj-$(CONFIG_PINCTRL_MOOREFIELD)       += pinctrl-moorefield.o
 obj-$(CONFIG_PINCTRL_INTEL)            += pinctrl-intel.o
+obj-$(CONFIG_PINCTRL_INTEL_PLATFORM)   += pinctrl-intel-platform.o
 obj-$(CONFIG_PINCTRL_ALDERLAKE)                += pinctrl-alderlake.o
 obj-$(CONFIG_PINCTRL_BROXTON)          += pinctrl-broxton.o
 obj-$(CONFIG_PINCTRL_CANNONLAKE)       += pinctrl-cannonlake.o

diff --git a/drivers/pinctrl/intel/pinctrl-intel-platform.c b/drivers/pinctrl/intel/pinctrl-intel-platform.c
new file mode 100644 (file)
index 0000000..4a19ab3
--- /dev/null
+++ b/drivers/pinctrl/intel/pinctrl-intel-platform.c
@@ -0,0 +1,225 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Intel PCH pinctrl/GPIO driver
+ *
+ * Copyright (C) 2021-2023, Intel Corporation
+ * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+ */
+
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/property.h>
+#include <linux/string_helpers.h>
+
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-intel.h"
+
+struct intel_platform_pins {
+       struct pinctrl_pin_desc *pins;
+       size_t npins;
+};
+
+static int intel_platform_pinctrl_prepare_pins(struct device *dev, size_t base,
+                                              const char *name, u32 size,
+                                              struct intel_platform_pins *pins)
+{
+       struct pinctrl_pin_desc *descs;
+       char **pin_names;
+       unsigned int i;
+
+       pin_names = devm_kasprintf_strarray(dev, name, size);
+       if (IS_ERR(pin_names))
+               return PTR_ERR(pin_names);
+
+       descs = devm_krealloc_array(dev, pins->pins, base + size, sizeof(*descs), GFP_KERNEL);
+       if (!descs)
+               return -ENOMEM;
+
+       for (i = 0; i < size; i++) {
+               unsigned int pin_number = base + i;
+               char *pin_name = pin_names[i];
+               struct pinctrl_pin_desc *desc;
+
+               /* Unify delimiter for pin name */
+               strreplace(pin_name, '-', '_');
+
+               desc = &descs[pin_number];
+               desc->number = pin_number;
+               desc->name = pin_name;
+       }
+
+       pins->pins = descs;
+       pins->npins = base + size;
+
+       return 0;
+}
+
+static int intel_platform_pinctrl_prepare_group(struct device *dev,
+                                               struct fwnode_handle *child,
+                                               struct intel_padgroup *gpp,
+                                               struct intel_platform_pins *pins)
+{
+       size_t base = pins->npins;
+       const char *name;
+       u32 size;
+       int ret;
+
+       ret = fwnode_property_read_string(child, "intc-gpio-group-name", &name);
+       if (ret)
+               return ret;
+
+       ret = fwnode_property_read_u32(child, "intc-gpio-pad-count", &size);
+       if (ret)
+               return ret;
+
+       ret = intel_platform_pinctrl_prepare_pins(dev, base, name, size, pins);
+       if (ret)
+               return ret;
+
+       gpp->base = base;
+       gpp->size = size;
+       gpp->gpio_base = INTEL_GPIO_BASE_MATCH;
+
+       return 0;
+}
+
+static int intel_platform_pinctrl_prepare_community(struct device *dev,
+                                                   struct intel_community *community,
+                                                   struct intel_platform_pins *pins)
+{
+       struct fwnode_handle *child;
+       struct intel_padgroup *gpps;
+       unsigned int group;
+       size_t ngpps;
+       u32 offset;
+       int ret;
+
+       ret = device_property_read_u32(dev, "intc-gpio-pad-ownership-offset", &offset);
+       if (ret)
+               return ret;
+       community->padown_offset = offset;
+
+       ret = device_property_read_u32(dev, "intc-gpio-pad-configuration-lock-offset", &offset);
+       if (ret)
+               return ret;
+       community->padcfglock_offset = offset;
+
+       ret = device_property_read_u32(dev, "intc-gpio-host-software-pad-ownership-offset", &offset);
+       if (ret)
+               return ret;
+       community->hostown_offset = offset;
+
+       ret = device_property_read_u32(dev, "intc-gpio-gpi-interrupt-status-offset", &offset);
+       if (ret)
+               return ret;
+       community->is_offset = offset;
+
+       ret = device_property_read_u32(dev, "intc-gpio-gpi-interrupt-enable-offset", &offset);
+       if (ret)
+               return ret;
+       community->ie_offset = offset;
+
+       ngpps = device_get_child_node_count(dev);
+       if (!ngpps)
+               return -ENODEV;
+
+       gpps = devm_kcalloc(dev, ngpps, sizeof(*gpps), GFP_KERNEL);
+       if (!gpps)
+               return -ENOMEM;
+
+       group = 0;
+       device_for_each_child_node(dev, child) {
+               struct intel_padgroup *gpp = &gpps[group];
+
+               gpp->reg_num = group;
+
+               ret = intel_platform_pinctrl_prepare_group(dev, child, gpp, pins);
+               if (ret)
+                       return ret;
+
+               group++;
+       }
+
+       community->ngpps = ngpps;
+       community->gpps = gpps;
+
+       return 0;
+}
+
+static int intel_platform_pinctrl_prepare_soc_data(struct device *dev,
+                                                  struct intel_pinctrl_soc_data *data)
+{
+       struct intel_platform_pins pins = {};
+       struct intel_community *communities;
+       size_t ncommunities;
+       unsigned int i;
+       int ret;
+
+       /* Version 1.0 of the specification assumes only a single community per device node */
+       ncommunities = 1,
+       communities = devm_kcalloc(dev, ncommunities, sizeof(*communities), GFP_KERNEL);
+       if (!communities)
+               return -ENOMEM;
+
+       for (i = 0; i < ncommunities; i++) {
+               struct intel_community *community = &communities[i];
+
+               community->barno = i;
+               community->pin_base = pins.npins;
+
+               ret = intel_platform_pinctrl_prepare_community(dev, community, &pins);
+               if (ret)
+                       return ret;
+
+               community->npins = pins.npins - community->pin_base;
+       }
+
+       data->ncommunities = ncommunities;
+       data->communities = communities;
+
+       data->npins = pins.npins;
+       data->pins = pins.pins;
+
+       return 0;
+}
+
+static int intel_platform_pinctrl_probe(struct platform_device *pdev)
+{
+       struct intel_pinctrl_soc_data *data;
+       struct device *dev = &pdev->dev;
+       int ret;
+
+       data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+       if (!data)
+               return -ENOMEM;
+
+       ret = intel_platform_pinctrl_prepare_soc_data(dev, data);
+       if (ret)
+               return ret;
+
+       return intel_pinctrl_probe(pdev, data);
+}
+
+static const struct acpi_device_id intel_platform_pinctrl_acpi_match[] = {
+       { "INTC105F" },
+       { }
+};
+MODULE_DEVICE_TABLE(acpi, intel_platform_pinctrl_acpi_match);
+
+static struct platform_driver intel_platform_pinctrl_driver = {
+       .probe = intel_platform_pinctrl_probe,
+       .driver = {
+               .name = "intel-pinctrl",
+               .acpi_match_table = intel_platform_pinctrl_acpi_match,
+               .pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
+       },
+};
+module_platform_driver(intel_platform_pinctrl_driver);
+
+MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
+MODULE_DESCRIPTION("Intel PCH pinctrl/GPIO driver");
+MODULE_LICENSE("GPL v2");
+MODULE_IMPORT_NS(PINCTRL_INTEL);