drm/amdgpu: exposing fica registers to df offsets

exposing fica registers to poll df pie data for xgmi error counters for
vega20.

Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com>
Reviewed-by: Alexander Deucher <Alexander.Deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h
index 6efcaa93e17b3a7df4d1df2f35f1c236d873bc62..c2bd25589e845207057b32049ba303ce47506506 100644 (file)
--- a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h
@@ -48,4 +48,8 @@
 #define smnPerfMonCtrLo3                                       0x01d478UL
 #define smnPerfMonCtrHi3                                       0x01d47cUL
 
+#define smnDF_PIE_AON_FabricIndirectConfigAccessAddress3       0x1d05cUL
+#define smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3                0x1d098UL
+#define smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3                0x1d09cUL
+
 #endif