PCI: pci-bridge-emul: Re-arrange register tests

Re-arrange the tests for which sets of registers are being accessed so that
it is easier to add further regions later. No functional change.

[pali: Fix reading old value in pci_bridge_emul_conf_write]
Link: https://lore.kernel.org/r/20220222155030.988-2-pali@kernel.org
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c
index a16f9e30099ef136ea60333b78ec258e23a3dbb2..a956408834d6c983a59bd4617d591c0e7e5f92ec 100644 (file)
--- a/drivers/pci/pci-bridge-emul.c
+++ b/drivers/pci/pci-bridge-emul.c
@@ -422,25 +422,25 @@ int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
        __le32 *cfgspace;
        const struct pci_bridge_reg_behavior *behavior;
 
-       if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) {
-               *value = 0;
-               return PCIBIOS_SUCCESSFUL;
-       }
-
-       if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) {
+       if (reg < PCI_BRIDGE_CONF_END) {
+               /* Emulated PCI space */
+               read_op = bridge->ops->read_base;
+               cfgspace = (__le32 *) &bridge->conf;
+               behavior = bridge->pci_regs_behavior;
+       } else if (!bridge->has_pcie) {
+               /* PCIe space is not implemented, and no PCI capabilities */
                *value = 0;
                return PCIBIOS_SUCCESSFUL;
-       }
-
-       if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
+       } else if (reg < PCI_CAP_PCIE_END) {
+               /* Our emulated PCIe capability */
                reg -= PCI_CAP_PCIE_START;
                read_op = bridge->ops->read_pcie;
                cfgspace = (__le32 *) &bridge->pcie_conf;
                behavior = bridge->pcie_cap_regs_behavior;
        } else {
-               read_op = bridge->ops->read_base;
-               cfgspace = (__le32 *) &bridge->conf;
-               behavior = bridge->pci_regs_behavior;
+               /* Beyond our PCIe space */
+               *value = 0;
+               return PCIBIOS_SUCCESSFUL;
        }
 
        if (read_op)
@@ -484,11 +484,27 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
        __le32 *cfgspace;
        const struct pci_bridge_reg_behavior *behavior;
 
-       if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END)
-               return PCIBIOS_SUCCESSFUL;
+       ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old);
+       if (ret != PCIBIOS_SUCCESSFUL)
+               return ret;
 
-       if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END)
+       if (reg < PCI_BRIDGE_CONF_END) {
+               /* Emulated PCI space */
+               write_op = bridge->ops->write_base;
+               cfgspace = (__le32 *) &bridge->conf;
+               behavior = bridge->pci_regs_behavior;
+       } else if (!bridge->has_pcie) {
+               /* PCIe space is not implemented, and no PCI capabilities */
                return PCIBIOS_SUCCESSFUL;
+       } else if (reg < PCI_CAP_PCIE_END) {
+               /* Our emulated PCIe capability */
+               reg -= PCI_CAP_PCIE_START;
+               write_op = bridge->ops->write_pcie;
+               cfgspace = (__le32 *) &bridge->pcie_conf;
+               behavior = bridge->pcie_cap_regs_behavior;
+       } else {
+               return PCIBIOS_SUCCESSFUL;
+       }
 
        shift = (where & 0x3) * 8;
 
@@ -501,21 +517,6 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
        else
                return PCIBIOS_BAD_REGISTER_NUMBER;
 
-       ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old);
-       if (ret != PCIBIOS_SUCCESSFUL)
-               return ret;
-
-       if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
-               reg -= PCI_CAP_PCIE_START;
-               write_op = bridge->ops->write_pcie;
-               cfgspace = (__le32 *) &bridge->pcie_conf;
-               behavior = bridge->pcie_cap_regs_behavior;
-       } else {
-               write_op = bridge->ops->write_base;
-               cfgspace = (__le32 *) &bridge->conf;
-               behavior = bridge->pci_regs_behavior;
-       }
-
        /* Keep all bits, except the RW bits */
        new = old & (~mask | ~behavior[reg / 4].rw);