8250: microchip: pci1xxxx: Add PCIe Hot reset disable support for Rev C0 and later...

Systems that issue PCIe hot reset requests during a suspend/resume
cycle cause PCI1XXXX device revisions prior to C0 to get its UART
configuration registers reset to hardware default values. This results
in device inaccessibility and data transfer failures. Starting with
Revision C0, support was added in the device hardware (via the Hot
Reset Disable Bit) to allow resetting only the PCIe interface and its
associated logic, but preserving the UART configuration during a hot
reset. This patch enables the hot reset disable feature during suspend/
resume for C0 and later revisions of the device.

Signed-off-by: Rengarajan S <rengarajan.s@microchip.com>
Reviewed-by: Jiri Slaby <jirislaby@kernel.org>
Link: https://lore.kernel.org/r/20250425145500.29036-1-rengarajan.s@microchip.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/tty/serial/8250/8250_pci1xxxx.c b/drivers/tty/serial/8250/8250_pci1xxxx.c
index e9c51d4e447dd29bcb63f10b1244501e59aeeb02..4c149db846925f63b2c84ad93695e4e334076961 100644 (file)
--- a/drivers/tty/serial/8250/8250_pci1xxxx.c
+++ b/drivers/tty/serial/8250/8250_pci1xxxx.c
@@ -115,6 +115,7 @@
 
 #define UART_RESET_REG                         0x94
 #define UART_RESET_D3_RESET_DISABLE            BIT(16)
+#define UART_RESET_HOT_RESET_DISABLE           BIT(17)
 
 #define UART_BURST_STATUS_REG                  0x9C
 #define UART_TX_BURST_FIFO                     0xA0
@@ -620,6 +621,10 @@ static int pci1xxxx_suspend(struct device *dev)
        }
 
        data = readl(p + UART_RESET_REG);
+
+       if (priv->dev_rev >= 0xC0)
+               data |= UART_RESET_HOT_RESET_DISABLE;
+
        writel(data | UART_RESET_D3_RESET_DISABLE, p + UART_RESET_REG);
 
        if (wakeup)
@@ -647,7 +652,12 @@ static int pci1xxxx_resume(struct device *dev)
        }
 
        data = readl(p + UART_RESET_REG);
+
+       if (priv->dev_rev >= 0xC0)
+               data &= ~UART_RESET_HOT_RESET_DISABLE;
+
        writel(data & ~UART_RESET_D3_RESET_DISABLE, p + UART_RESET_REG);
+
        iounmap(p);
 
        for (i = 0; i < priv->nr; i++) {