drm/i915: FIFO space query code refactor
authorDave Gordon <david.s.gordon@intel.com>
Wed, 10 Dec 2014 18:12:12 +0000 (18:12 +0000)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Mon, 23 Feb 2015 15:45:16 +0000 (16:45 +0100)
When querying the GTFIFOCTL register to check the FIFO space, the read value
must be masked. The operation is repeated explicitly in several places. This
change refactors the read-and-mask code into a function call.

v2: rebased on top of Mika's forcewake patch set, specifically:
[PATCH 8/8] drm/i915: Enum forcewake domains and domain identifiers

Change-Id: Id1a9f3785cb20b82d4caa330c37b31e4e384a3ef
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_uncore.c

index 27cc45849715f960eb8337a6d848d392c0f277d8..439cae455f5e4b0643d35d6bdacb0af1a33b13d2 100644 (file)
@@ -210,6 +210,13 @@ static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,
        gen6_gt_check_fifodbg(dev_priv);
 }
 
+static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
+{
+       u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL);
+
+       return count & GT_FIFO_FREE_ENTRIES_MASK;
+}
+
 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 {
        int ret = 0;
@@ -217,16 +224,15 @@ static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
        /* On VLV, FIFO will be shared by both SW and HW.
         * So, we need to read the FREE_ENTRIES everytime */
        if (IS_VALLEYVIEW(dev_priv->dev))
-               dev_priv->uncore.fifo_count =
-                       __raw_i915_read32(dev_priv, GTFIFOCTL) &
-                                               GT_FIFO_FREE_ENTRIES_MASK;
+               dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv);
 
        if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
                int loop = 500;
-               u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
+               u32 fifo = fifo_free_entries(dev_priv);
+
                while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
                        udelay(10);
-                       fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
+                       fifo = fifo_free_entries(dev_priv);
                }
                if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
                        ++ret;
@@ -314,8 +320,7 @@ void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
 
                if (IS_GEN6(dev) || IS_GEN7(dev))
                        dev_priv->uncore.fifo_count =
-                               __raw_i915_read32(dev_priv, GTFIFOCTL) &
-                               GT_FIFO_FREE_ENTRIES_MASK;
+                               fifo_free_entries(dev_priv);
        }
 
        if (!restore)