arm64: dts: ti: k3-j721e-evm: Add overlay for PCIE1 Endpoint Mode

Add overlay to enable the PCIE1 instance of PCIe on J721E-EVM in Endpoint
mode of operation. Additionally, in order to support both PCIE0 and PCIE1
in Endpoint Mode of operation, enable applying device-tree overlays on
"k3-j721e-evm-pcie0-ep.dtb", thereby allowing the overlay for PCIE1 in
Endpoint mode to be applied on the aforementioned DTB.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20241205105041.749576-3-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 379bfa4425d49dd54a54634636f11be374023399..03bacbc589ee2f095176792aee7719d97a257f09 100644 (file)
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -107,6 +107,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board-infotainment.dtbo
 dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-gesi-exp-board.dtbo
 dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-pcie0-ep.dtbo
+dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-pcie1-ep.dtbo
 dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk-csi2-dual-imx219.dtbo
 
@@ -200,6 +201,8 @@ k3-j721e-common-proc-board-infotainment-dtbs := k3-j721e-common-proc-board.dtb \
        k3-j721e-common-proc-board-infotainment.dtbo
 k3-j721e-evm-pcie0-ep-dtbs := k3-j721e-common-proc-board.dtb \
        k3-j721e-evm-pcie0-ep.dtbo
+k3-j721e-evm-pcie1-ep-dtbs := k3-j721e-common-proc-board.dtb \
+       k3-j721e-evm-pcie1-ep.dtbo
 k3-j721e-sk-csi2-dual-imx219-dtbs := k3-j721e-sk.dtb \
        k3-j721e-sk-csi2-dual-imx219.dtbo
 k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \
@@ -233,6 +236,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
        k3-j7200-evm-pcie1-ep.dtb \
        k3-j721e-common-proc-board-infotainment.dtb \
        k3-j721e-evm-pcie0-ep.dtb \
+       k3-j721e-evm-pcie1-ep.dtb \
        k3-j721e-sk-csi2-dual-imx219.dtb \
        k3-j721s2-evm-pcie1-ep.dtb \
        k3-j784s4-evm-pcie0-pcie1-ep.dtb \
@@ -255,6 +259,7 @@ DTC_FLAGS_k3-am68-sk-base-board += -@
 DTC_FLAGS_k3-am69-sk += -@
 DTC_FLAGS_k3-j7200-common-proc-board += -@
 DTC_FLAGS_k3-j721e-common-proc-board += -@
+DTC_FLAGS_k3-j721e-evm-pcie0-ep += -@
 DTC_FLAGS_k3-j721e-sk += -@
 DTC_FLAGS_k3-j721s2-common-proc-board += -@
 DTC_FLAGS_k3-j784s4-evm += -@

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso
new file mode 100644 (file)
index 0000000..a8cccdc
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/**
+ * DT Overlay for enabling PCIE1 instance in Endpoint Configuration with the
+ * J7 common processor board.
+ *
+ * J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+#include "k3-pinctrl.h"
+
+/*
+ * Since Root Complex and Endpoint modes are mutually exclusive
+ * disable Root Complex mode.
+ */
+&pcie1_rc {
+       status = "disabled";
+};
+
+&cbass_main {
+       #address-cells = <2>;
+       #size-cells = <2>;
+       interrupt-parent = <&gic500>;
+
+       pcie1_ep: pcie-ep@2910000 {
+               compatible = "ti,j721e-pcie-ep";
+               reg = <0x00 0x02910000 0x00 0x1000>,
+                     <0x00 0x02917000 0x00 0x400>,
+                     <0x00 0x0d800000 0x00 0x00800000>,
+                     <0x00 0x18000000 0x00 0x08000000>;
+               reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+               interrupt-names = "link_state";
+               interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+               max-link-speed = <3>;
+               num-lanes = <2>;
+               power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 240 1>;
+               clock-names = "fck";
+               max-functions = /bits/ 8 <6>;
+               max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
+               dma-coherent;
+               phys = <&serdes1_pcie_link>;
+               phy-names = "pcie-phy";
+               ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
+       };
+};