powerpc/64s: Make hash MMU support configurable
authorNicholas Piggin <npiggin@gmail.com>
Wed, 1 Dec 2021 14:41:51 +0000 (00:41 +1000)
committerMichael Ellerman <mpe@ellerman.id.au>
Thu, 9 Dec 2021 11:40:24 +0000 (22:40 +1100)
This adds Kconfig selection which allows 64s hash MMU support to be
disabled. It can be disabled if radix support is enabled, the minimum
supported CPU type is POWER9 (or higher), and KVM is not selected.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20211201144153.2456614-17-npiggin@gmail.com
14 files changed:
arch/powerpc/Kconfig
arch/powerpc/include/asm/mmu.h
arch/powerpc/kernel/dt_cpu_ftrs.c
arch/powerpc/kvm/Kconfig
arch/powerpc/mm/init_64.c
arch/powerpc/platforms/Kconfig.cputype
arch/powerpc/platforms/cell/Kconfig
arch/powerpc/platforms/maple/Kconfig
arch/powerpc/platforms/microwatt/Kconfig
arch/powerpc/platforms/pasemi/Kconfig
arch/powerpc/platforms/powermac/Kconfig
arch/powerpc/platforms/powernv/Kconfig
drivers/misc/cxl/Kconfig
drivers/misc/lkdtm/Makefile

index e3e281a35327ada86b4db3ae70a59c6096335226..2555563efff0b7b795d6147f400ce4b7c19b2cd8 100644 (file)
@@ -846,7 +846,7 @@ config FORCE_MAX_ZONEORDER
 config PPC_SUBPAGE_PROT
        bool "Support setting protections for 4k subpages (subpage_prot syscall)"
        default n
-       depends on PPC_BOOK3S_64 && PPC_64K_PAGES
+       depends on PPC_64S_HASH_MMU && PPC_64K_PAGES
        help
          This option adds support for system call to allow user programs
          to set access permissions (read/write, readonly, or no access)
@@ -944,6 +944,7 @@ config PPC_MEM_KEYS
        prompt "PowerPC Memory Protection Keys"
        def_bool y
        depends on PPC_BOOK3S_64
+       depends on PPC_64S_HASH_MMU
        select ARCH_USES_HIGH_VMA_FLAGS
        select ARCH_HAS_PKEYS
        help
index 8abe8e42e045cd5828139d4ea2d011c42e200e79..5f41565a1e5d71a770bd8b5c1970540d2960c9ca 100644 (file)
@@ -157,7 +157,7 @@ DECLARE_PER_CPU(int, next_tlbcam_idx);
 
 enum {
        MMU_FTRS_POSSIBLE =
-#if defined(CONFIG_PPC_BOOK3S_64) || defined(CONFIG_PPC_BOOK3S_604)
+#if defined(CONFIG_PPC_BOOK3S_604)
                MMU_FTR_HPTE_TABLE |
 #endif
 #ifdef CONFIG_PPC_8xx
@@ -184,15 +184,18 @@ enum {
                MMU_FTR_USE_TLBRSRV | MMU_FTR_USE_PAIRED_MAS |
 #endif
 #ifdef CONFIG_PPC_BOOK3S_64
+               MMU_FTR_KERNEL_RO |
+#ifdef CONFIG_PPC_64S_HASH_MMU
                MMU_FTR_NO_SLBIE_B | MMU_FTR_16M_PAGE | MMU_FTR_TLBIEL |
                MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_CI_LARGE_PAGE |
                MMU_FTR_1T_SEGMENT | MMU_FTR_TLBIE_CROP_VA |
-               MMU_FTR_KERNEL_RO | MMU_FTR_68_BIT_VA |
+               MMU_FTR_68_BIT_VA | MMU_FTR_HPTE_TABLE |
 #endif
 #ifdef CONFIG_PPC_RADIX_MMU
                MMU_FTR_TYPE_RADIX |
                MMU_FTR_GTSE |
 #endif /* CONFIG_PPC_RADIX_MMU */
+#endif
 #ifdef CONFIG_PPC_KUAP
        MMU_FTR_BOOK3S_KUAP |
 #endif /* CONFIG_PPC_KUAP */
@@ -224,6 +227,13 @@ enum {
 #define MMU_FTRS_ALWAYS                MMU_FTR_TYPE_FSL_E
 #endif
 
+/* BOOK3S_64 options */
+#if defined(CONFIG_PPC_RADIX_MMU) && !defined(CONFIG_PPC_64S_HASH_MMU)
+#define MMU_FTRS_ALWAYS                MMU_FTR_TYPE_RADIX
+#elif !defined(CONFIG_PPC_RADIX_MMU) && defined(CONFIG_PPC_64S_HASH_MMU)
+#define MMU_FTRS_ALWAYS                MMU_FTR_HPTE_TABLE
+#endif
+
 #ifndef MMU_FTRS_ALWAYS
 #define MMU_FTRS_ALWAYS                0
 #endif
@@ -329,7 +339,7 @@ static __always_inline bool radix_enabled(void)
        return mmu_has_feature(MMU_FTR_TYPE_RADIX);
 }
 
-static inline bool early_radix_enabled(void)
+static __always_inline bool early_radix_enabled(void)
 {
        return early_mmu_has_feature(MMU_FTR_TYPE_RADIX);
 }
index d2b35fb9181df61ba8974b0a984b66eaf6d0662f..1ac8d7357195c54e885667a4f0504d831295dad2 100644 (file)
@@ -273,6 +273,9 @@ static int __init feat_enable_mmu_hash(struct dt_cpu_feature *f)
 {
        u64 lpcr;
 
+       if (!IS_ENABLED(CONFIG_PPC_64S_HASH_MMU))
+               return 0;
+
        lpcr = mfspr(SPRN_LPCR);
        lpcr &= ~LPCR_ISL;
 
@@ -292,6 +295,9 @@ static int __init feat_enable_mmu_hash_v3(struct dt_cpu_feature *f)
 {
        u64 lpcr;
 
+       if (!IS_ENABLED(CONFIG_PPC_64S_HASH_MMU))
+               return 0;
+
        lpcr = mfspr(SPRN_LPCR);
        lpcr &= ~(LPCR_ISL | LPCR_UPRT | LPCR_HR);
        mtspr(SPRN_LPCR, lpcr);
@@ -305,15 +311,15 @@ static int __init feat_enable_mmu_hash_v3(struct dt_cpu_feature *f)
 
 static int __init feat_enable_mmu_radix(struct dt_cpu_feature *f)
 {
-#ifdef CONFIG_PPC_RADIX_MMU
+       if (!IS_ENABLED(CONFIG_PPC_RADIX_MMU))
+               return 0;
+
+       cur_cpu_spec->mmu_features |= MMU_FTR_KERNEL_RO;
        cur_cpu_spec->mmu_features |= MMU_FTR_TYPE_RADIX;
-       cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE;
        cur_cpu_spec->mmu_features |= MMU_FTR_GTSE;
        cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU;
 
        return 1;
-#endif
-       return 0;
 }
 
 static int __init feat_enable_dscr(struct dt_cpu_feature *f)
index 6a58532300c50dc50cb67794574aed3b726388f9..f947b77386a9e790e75b8f2fb86794d90a05330e 100644 (file)
@@ -69,6 +69,7 @@ config KVM_BOOK3S_64
        select KVM_BOOK3S_64_HANDLER
        select KVM
        select KVM_BOOK3S_PR_POSSIBLE if !KVM_BOOK3S_HV_POSSIBLE
+       select PPC_64S_HASH_MMU
        select SPAPR_TCE_IOMMU if IOMMU_SUPPORT && (PPC_PSERIES || PPC_POWERNV)
        help
          Support running unmodified book3s_64 and book3s_32 guest kernels
index 3e5f9ac9dded7b98b0684c54672d6c43d4a84963..35f46bf5428198c369cfb8047806f505a63e4252 100644 (file)
@@ -472,8 +472,12 @@ void __init mmu_early_init_devtree(void)
        bool hvmode = !!(mfmsr() & MSR_HV);
 
        /* Disable radix mode based on kernel command line. */
-       if (disable_radix)
-               cur_cpu_spec->mmu_features &= ~MMU_FTR_TYPE_RADIX;
+       if (disable_radix) {
+               if (IS_ENABLED(CONFIG_PPC_64S_HASH_MMU))
+                       cur_cpu_spec->mmu_features &= ~MMU_FTR_TYPE_RADIX;
+               else
+                       pr_warn("WARNING: Ignoring cmdline option disable_radix\n");
+       }
 
        of_scan_flat_dt(dt_scan_mmu_pid_width, NULL);
        if (hvmode && !mmu_lpid_bits) {
@@ -498,6 +502,7 @@ void __init mmu_early_init_devtree(void)
 
        if (early_radix_enabled()) {
                radix__early_init_devtree();
+
                /*
                 * We have finalized the translation we are going to use by now.
                 * Radix mode is not limited by RMA / VRMA addressing.
@@ -507,5 +512,9 @@ void __init mmu_early_init_devtree(void)
                memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
        } else
                hash__early_init_devtree();
+
+       if (!(cur_cpu_spec->mmu_features & MMU_FTR_HPTE_TABLE) &&
+           !(cur_cpu_spec->mmu_features & MMU_FTR_TYPE_RADIX))
+               panic("kernel does not support any MMU type offered by platform");
 }
 #endif /* CONFIG_PPC_BOOK3S_64 */
index a208997ade88be2f26a237ab94ecf2ce5e5c510a..7ca07df1c374ad60514f360fb7dbd42f2517eb25 100644 (file)
@@ -105,9 +105,9 @@ config PPC_BOOK3S_64
        select HAVE_MOVE_PMD
        select HAVE_MOVE_PUD
        select IRQ_WORK
-       select PPC_MM_SLICES
        select PPC_HAVE_KUEP
        select PPC_HAVE_KUAP
+       select PPC_64S_HASH_MMU if !PPC_RADIX_MMU
 
 config PPC_BOOK3E_64
        bool "Embedded processors"
@@ -130,11 +130,13 @@ choice
 config GENERIC_CPU
        bool "Generic (POWER4 and above)"
        depends on PPC64 && !CPU_LITTLE_ENDIAN
+       select PPC_64S_HASH_MMU if PPC_BOOK3S_64
 
 config GENERIC_CPU
        bool "Generic (POWER8 and above)"
        depends on PPC64 && CPU_LITTLE_ENDIAN
        select ARCH_HAS_FAST_MULTIPLIER
+       select PPC_64S_HASH_MMU
 
 config GENERIC_CPU
        bool "Generic 32 bits powerpc"
@@ -143,24 +145,29 @@ config GENERIC_CPU
 config CELL_CPU
        bool "Cell Broadband Engine"
        depends on PPC_BOOK3S_64 && !CPU_LITTLE_ENDIAN
+       select PPC_64S_HASH_MMU
 
 config POWER5_CPU
        bool "POWER5"
        depends on PPC_BOOK3S_64 && !CPU_LITTLE_ENDIAN
+       select PPC_64S_HASH_MMU
 
 config POWER6_CPU
        bool "POWER6"
        depends on PPC_BOOK3S_64 && !CPU_LITTLE_ENDIAN
+       select PPC_64S_HASH_MMU
 
 config POWER7_CPU
        bool "POWER7"
        depends on PPC_BOOK3S_64
        select ARCH_HAS_FAST_MULTIPLIER
+       select PPC_64S_HASH_MMU
 
 config POWER8_CPU
        bool "POWER8"
        depends on PPC_BOOK3S_64
        select ARCH_HAS_FAST_MULTIPLIER
+       select PPC_64S_HASH_MMU
 
 config POWER9_CPU
        bool "POWER9"
@@ -364,6 +371,22 @@ config SPE
 
          If in doubt, say Y here.
 
+config PPC_64S_HASH_MMU
+       bool "Hash MMU Support"
+       depends on PPC_BOOK3S_64
+       select PPC_MM_SLICES
+       default y
+       help
+         Enable support for the Power ISA Hash style MMU. This is implemented
+         by all IBM Power and other 64-bit Book3S CPUs before ISA v3.0. The
+         OpenPOWER ISA does not mandate the hash MMU and some CPUs do not
+         implement it (e.g., Microwatt).
+
+         Note that POWER9 PowerVM platforms only support the hash
+         MMU. From POWER10 radix is also supported by PowerVM.
+
+         If you're unsure, say Y.
+
 config PPC_RADIX_MMU
        bool "Radix MMU Support"
        depends on PPC_BOOK3S_64
@@ -375,7 +398,8 @@ config PPC_RADIX_MMU
          you can probably disable this.
 
 config PPC_RADIX_MMU_DEFAULT
-       bool "Default to using the Radix MMU when possible"
+       bool "Default to using the Radix MMU when possible" if PPC_64S_HASH_MMU
+       depends on PPC_BOOK3S_64
        depends on PPC_RADIX_MMU
        default y
        help
index db4465c51b56e425db47526c3564f5c563d24716..34669b060f36613b937ddd0b81259a234eec7b4f 100644 (file)
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 config PPC_CELL
+       select PPC_64S_HASH_MMU if PPC64
        bool
 
 config PPC_CELL_COMMON
index 7fd84311ade58c219060cb12325bfa5536637db6..4c058cc57c9011a7811b17e3fe62b1bedcbffacb 100644 (file)
@@ -9,6 +9,7 @@ config PPC_MAPLE
        select GENERIC_TBSYNC
        select PPC_UDBG_16550
        select PPC_970_NAP
+       select PPC_64S_HASH_MMU
        select PPC_HASH_MMU_NATIVE
        select PPC_RTAS
        select MMIO_NVRAM
index 62b51e37fc05a9e81a974c56aa7a899a7d8def70..823192e9d38ad2a738776df4b854e825c2ef7447 100644 (file)
@@ -5,7 +5,7 @@ config PPC_MICROWATT
        select PPC_XICS
        select PPC_ICS_NATIVE
        select PPC_ICP_NATIVE
-       select PPC_HASH_MMU_NATIVE
+       select PPC_HASH_MMU_NATIVE if PPC_64S_HASH_MMU
        select PPC_UDBG_16550
        select ARCH_RANDOM
        help
index bc7137353a7f194e86a16b65e57e162e62a15d2f..85ae18ddd9111765f441228cd9286f5db0a08307 100644 (file)
@@ -5,6 +5,7 @@ config PPC_PASEMI
        select MPIC
        select FORCE_PCI
        select PPC_UDBG_16550
+       select PPC_64S_HASH_MMU
        select PPC_HASH_MMU_NATIVE
        select MPIC_BROKEN_REGREAD
        help
index 2b56df145b824e15a196b28ba6ab28f003fe25b2..130707ec9f992b41885200281cfc491ee136ea8b 100644 (file)
@@ -6,6 +6,7 @@ config PPC_PMAC
        select FORCE_PCI
        select PPC_INDIRECT_PCI if PPC32
        select PPC_MPC106 if PPC32
+       select PPC_64S_HASH_MMU if PPC64
        select PPC_HASH_MMU_NATIVE
        select ZONE_DMA if PPC32
        default y
index cd754e1161848b43be8bc66b4f73639dd7d2eca7..161dfe024085f07d8b3c6d220ba6233c12addc36 100644 (file)
@@ -2,7 +2,7 @@
 config PPC_POWERNV
        depends on PPC64 && PPC_BOOK3S
        bool "IBM PowerNV (Non-Virtualized) platform support"
-       select PPC_HASH_MMU_NATIVE
+       select PPC_HASH_MMU_NATIVE if PPC_64S_HASH_MMU
        select PPC_XICS
        select PPC_ICP_NATIVE
        select PPC_XIVE_NATIVE
index 51aecafdcbdf0d80dda97dbc2560f490e2838245..5efc4151bf585cd53ee6fbc9bb6b55a97329456c 100644 (file)
@@ -6,6 +6,7 @@
 config CXL_BASE
        bool
        select PPC_COPRO_BASE
+       select PPC_64S_HASH_MMU
 
 config CXL
        tristate "Support for IBM Coherent Accelerators (CXL)"
index aa12097668d33ed9dffef72344d573982c15aed5..83a7baf5df822609517eb689d6e4661f9f5b3e61 100644 (file)
@@ -11,7 +11,7 @@ lkdtm-$(CONFIG_LKDTM)         += usercopy.o
 lkdtm-$(CONFIG_LKDTM)          += stackleak.o
 lkdtm-$(CONFIG_LKDTM)          += cfi.o
 lkdtm-$(CONFIG_LKDTM)          += fortify.o
-lkdtm-$(CONFIG_PPC_BOOK3S_64)  += powerpc.o
+lkdtm-$(CONFIG_PPC_64S_HASH_MMU)       += powerpc.o
 
 KASAN_SANITIZE_rodata.o                := n
 KASAN_SANITIZE_stackleak.o     := n