arm64: dts: renesas: r8a779h0: Add display support

Add the device nodes for supporting DU and DSI.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241206-rcar-gh-dsi-v3-9-d74c2166fa15@ideasonboard.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
index facfff4b9cdca155b403463672db7dce849b9be4..d0c01c0fdda2ff7946e4818f942db00b361d6f60 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
@@ -1900,6 +1900,50 @@
                        };
                };
 
+               fcpvd0: fcp@fea10000 {
+                       compatible = "renesas,fcpv";
+                       reg = <0 0xfea10000 0 0x200>;
+                       clocks = <&cpg CPG_MOD 508>;
+                       power-domains = <&sysc R8A779H0_PD_C4>;
+                       resets = <&cpg 508>;
+               };
+
+               vspd0: vsp@fea20000 {
+                       compatible = "renesas,vsp2";
+                       reg = <0 0xfea20000 0 0x8000>;
+                       interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 830>;
+                       power-domains = <&sysc R8A779H0_PD_C4>;
+                       resets = <&cpg 830>;
+                       renesas,fcp = <&fcpvd0>;
+               };
+
+               du: display@feb00000 {
+                       compatible = "renesas,du-r8a779h0";
+                       reg = <0 0xfeb00000 0 0x40000>;
+                       interrupts = <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 411>;
+                       clock-names = "du.0";
+                       power-domains = <&sysc R8A779H0_PD_C4>;
+                       resets = <&cpg 411>;
+                       reset-names = "du.0";
+                       renesas,vsps = <&vspd0 0>;
+
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+                                       du_out_dsi0: endpoint {
+                                               remote-endpoint = <&dsi0_in>;
+                                       };
+                               };
+                       };
+               };
+
                isp0: isp@fed00000 {
                        compatible = "renesas,r8a779h0-isp",
                                     "renesas,rcar-gen4-isp";
@@ -2068,6 +2112,35 @@
                        };
                };
 
+               dsi0: dsi-encoder@fed80000 {
+                       compatible = "renesas,r8a779h0-dsi-csi2-tx";
+                       reg = <0 0xfed80000 0 0x10000>;
+                       clocks = <&cpg CPG_MOD 415>,
+                                <&cpg CPG_CORE R8A779H0_CLK_DSIEXT>,
+                                <&cpg CPG_CORE R8A779H0_CLK_DSIREF>;
+                       clock-names = "fck", "dsi", "pll";
+                       power-domains = <&sysc R8A779H0_PD_C4>;
+                       resets = <&cpg 415>;
+
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+                                       dsi0_in: endpoint {
+                                               remote-endpoint = <&du_out_dsi0>;
+                                       };
+                               };
+
+                               port@1 {
+                                       reg = <1>;
+                               };
+                       };
+               };
+
                prr: chipid@fff00044 {
                        compatible = "renesas,prr";
                        reg = <0 0xfff00044 0 4>;