drm/i915: Move setting of rps thresholds to init
authorTvrtko Ursulin <tvrtko.ursulin@intel.com>
Mon, 17 Jul 2023 16:40:10 +0000 (17:40 +0100)
committerTvrtko Ursulin <tvrtko.ursulin@intel.com>
Wed, 19 Jul 2023 10:28:16 +0000 (11:28 +0100)
Since 36d516be867c ("drm/i915/gt: Switch to manual evaluation of RPS")
thresholds are invariant so lets move their setting to init time.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@kernel.org>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230717164013.826614-1-tvrtko.ursulin@linux.intel.com
drivers/gpu/drm/i915/gt/intel_rps.c

index b2671ac59dc04a7b2851ce1e370ef6f3eae4e55d..5c9a24aab38e78485b00408d9660cf7fde580b5c 100644 (file)
@@ -669,7 +669,6 @@ static void rps_set_power(struct intel_rps *rps, int new_power)
 {
        struct intel_gt *gt = rps_to_gt(rps);
        struct intel_uncore *uncore = gt->uncore;
-       u32 threshold_up = 0, threshold_down = 0; /* in % */
        u32 ei_up = 0, ei_down = 0;
 
        lockdep_assert_held(&rps->power.mutex);
@@ -677,9 +676,6 @@ static void rps_set_power(struct intel_rps *rps, int new_power)
        if (new_power == rps->power.mode)
                return;
 
-       threshold_up = 95;
-       threshold_down = 85;
-
        /* Note the units here are not exactly 1us, but 1280ns. */
        switch (new_power) {
        case LOW_POWER:
@@ -706,17 +702,22 @@ static void rps_set_power(struct intel_rps *rps, int new_power)
 
        GT_TRACE(gt,
                 "changing power mode [%d], up %d%% @ %dus, down %d%% @ %dus\n",
-                new_power, threshold_up, ei_up, threshold_down, ei_down);
+                new_power,
+                rps->power.up_threshold, ei_up,
+                rps->power.down_threshold, ei_down);
 
        set(uncore, GEN6_RP_UP_EI,
            intel_gt_ns_to_pm_interval(gt, ei_up * 1000));
        set(uncore, GEN6_RP_UP_THRESHOLD,
-           intel_gt_ns_to_pm_interval(gt, ei_up * threshold_up * 10));
+           intel_gt_ns_to_pm_interval(gt,
+                                      ei_up * rps->power.up_threshold * 10));
 
        set(uncore, GEN6_RP_DOWN_EI,
            intel_gt_ns_to_pm_interval(gt, ei_down * 1000));
        set(uncore, GEN6_RP_DOWN_THRESHOLD,
-           intel_gt_ns_to_pm_interval(gt, ei_down * threshold_down * 10));
+           intel_gt_ns_to_pm_interval(gt,
+                                      ei_down *
+                                      rps->power.down_threshold * 10));
 
        set(uncore, GEN6_RP_CONTROL,
            (GRAPHICS_VER(gt->i915) > 9 ? 0 : GEN6_RP_MEDIA_TURBO) |
@@ -728,8 +729,6 @@ static void rps_set_power(struct intel_rps *rps, int new_power)
 
 skip_hw_write:
        rps->power.mode = new_power;
-       rps->power.up_threshold = threshold_up;
-       rps->power.down_threshold = threshold_down;
 }
 
 static void gen6_rps_set_thresholds(struct intel_rps *rps, u8 val)
@@ -1555,10 +1554,12 @@ void intel_rps_enable(struct intel_rps *rps)
                return;
 
        GT_TRACE(rps_to_gt(rps),
-                "min:%x, max:%x, freq:[%d, %d]\n",
+                "min:%x, max:%x, freq:[%d, %d], thresholds:[%u, %u]\n",
                 rps->min_freq, rps->max_freq,
                 intel_gpu_freq(rps, rps->min_freq),
-                intel_gpu_freq(rps, rps->max_freq));
+                intel_gpu_freq(rps, rps->max_freq),
+                rps->power.up_threshold,
+                rps->power.down_threshold);
 
        GEM_BUG_ON(rps->max_freq < rps->min_freq);
        GEM_BUG_ON(rps->idle_freq > rps->max_freq);
@@ -2011,6 +2012,10 @@ void intel_rps_init(struct intel_rps *rps)
                }
        }
 
+       /* Set default thresholds in % */
+       rps->power.up_threshold = 95;
+       rps->power.down_threshold = 85;
+
        /* Finally allow us to boost to max by default */
        rps->boost_freq = rps->max_freq;
        rps->idle_freq = rps->min_freq;