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riscv: mm: fix NOCACHE_THEAD does not set bit[61] correctly
author
Yangyu Chen
<cyy@cyyself.name>
Wed, 21 Feb 2024 03:02:31 +0000
(11:02 +0800)
committer
Palmer Dabbelt
<palmer@rivosinc.com>
Thu, 22 Feb 2024 20:21:27 +0000
(12:21 -0800)
Previous commit
dbfbda3bd6bf
("riscv: mm: update T-Head memory type
definitions") from patch [1] missed a `<` for bit shifting, result in
bit(61) does not set in _PAGE_NOCACHE_THEAD and leaves bit(0) set instead.
This patch get this fixed.
Link:
https://lore.kernel.org/linux-riscv/20230912072510.2510-1-jszhang@kernel.org/
Fixes:
dbfbda3bd6bf
("riscv: mm: update T-Head memory type definitions")
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Reviewed-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Link:
https://lore.kernel.org/r/tencent_E19FA1A095768063102E654C6FC858A32F06@qq.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/include/asm/pgtable-64.h
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diff --git
a/arch/riscv/include/asm/pgtable-64.h
b/arch/riscv/include/asm/pgtable-64.h
index b42017d76924f74386bc712719280af21781bb5d..b99bd66107a69038c835ead6b77725aaeaf882c3 100644
(file)
--- a/
arch/riscv/include/asm/pgtable-64.h
+++ b/
arch/riscv/include/asm/pgtable-64.h
@@
-136,7
+136,7
@@
enum napot_cont_order {
* 10010 - IO Strongly-ordered, Non-cacheable, Non-bufferable, Shareable, Non-trustable
*/
#define _PAGE_PMA_THEAD ((1UL << 62) | (1UL << 61) | (1UL << 60))
-#define _PAGE_NOCACHE_THEAD ((1UL < 61) | (1UL << 60))
+#define _PAGE_NOCACHE_THEAD ((1UL <
<
61) | (1UL << 60))
#define _PAGE_IO_THEAD ((1UL << 63) | (1UL << 60))
#define _PAGE_MTMASK_THEAD (_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL << 59))