MIPS: pci-mt7620: fix PLL lock check

Upstream a long-standing OpenWrt patch [0] that fixes MT7620 PCIe PLL
lock check. The existing code checks the wrong register bit: PPLL_SW_SET
is not defined in PPLL_CFG1 and bit 31 of PPLL_CFG1 is marked as reserved
in the MT7620 Programming Guide. The correct bit to check for PLL lock
is PPLL_LD (bit 23).

Also reword the error message for clarity.

Without this change it is unlikely that this driver ever worked with
mainline kernel.

[0]: https://lists.infradead.org/pipermail/lede-commits/2017-July/004441.html

Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
Cc: John Crispin <john@phrozen.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-mediatek@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: stable@vger.kernel.org
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/pci/pci-mt7620.c b/arch/mips/pci/pci-mt7620.c
index d3606160375254a1dd12981084faeea30acbf407..e032932348d6f89ab9cd5518c876d58bb6fa92ad 100644 (file)
--- a/arch/mips/pci/pci-mt7620.c
+++ b/arch/mips/pci/pci-mt7620.c
@@ -30,6 +30,7 @@
 #define RALINK_GPIOMODE                        0x60
 
 #define PPLL_CFG1                      0x9c
+#define PPLL_LD                                BIT(23)
 
 #define PPLL_DRV                       0xa0
 #define PDRV_SW_SET                    BIT(31)
@@ -239,8 +240,8 @@ static int mt7620_pci_hw_init(struct platform_device *pdev)
        rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
        mdelay(100);
 
-       if (!(rt_sysc_r32(PPLL_CFG1) & PDRV_SW_SET)) {
-               dev_err(&pdev->dev, "MT7620 PPLL unlock\n");
+       if (!(rt_sysc_r32(PPLL_CFG1) & PPLL_LD)) {
+               dev_err(&pdev->dev, "pcie PLL not locked, aborting init\n");
                reset_control_assert(rstpcie0);
                rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
                return -1;