drm/i915/gt: Use to_gt() helper
authorMichał Winiarski <michal.winiarski@intel.com>
Tue, 14 Dec 2021 19:33:34 +0000 (21:33 +0200)
committerMatt Roper <matthew.d.roper@intel.com>
Sat, 18 Dec 2021 05:50:06 +0000 (21:50 -0800)
Use to_gt() helper consistently throughout the codebase.
Pure mechanical s/i915->gt/to_gt(i915). No functional changes.

Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211214193346.21231-5-andi.shyti@linux.intel.com
23 files changed:
drivers/gpu/drm/i915/gt/intel_engine_user.c
drivers/gpu/drm/i915/gt/intel_ggtt.c
drivers/gpu/drm/i915/gt/intel_rps.c
drivers/gpu/drm/i915/gt/intel_workarounds.c
drivers/gpu/drm/i915/gt/mock_engine.c
drivers/gpu/drm/i915/gt/selftest_context.c
drivers/gpu/drm/i915/gt/selftest_engine.c
drivers/gpu/drm/i915/gt/selftest_engine_cs.c
drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
drivers/gpu/drm/i915/gt/selftest_execlists.c
drivers/gpu/drm/i915/gt/selftest_gt_pm.c
drivers/gpu/drm/i915/gt/selftest_hangcheck.c
drivers/gpu/drm/i915/gt/selftest_lrc.c
drivers/gpu/drm/i915/gt/selftest_migrate.c
drivers/gpu/drm/i915/gt/selftest_mocs.c
drivers/gpu/drm/i915/gt/selftest_reset.c
drivers/gpu/drm/i915/gt/selftest_ring_submission.c
drivers/gpu/drm/i915/gt/selftest_slpc.c
drivers/gpu/drm/i915/gt/selftest_timeline.c
drivers/gpu/drm/i915/gt/selftest_workarounds.c
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
drivers/gpu/drm/i915/gt/uc/selftest_guc.c
drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c

index 8f8bea08e734d349604bd4a48b8a1eed3193c065..9ce85a845105c99000f7fca64a030f12bed6ec85 100644 (file)
@@ -116,7 +116,7 @@ static void set_scheduler_caps(struct drm_i915_private *i915)
                        disabled |= (I915_SCHEDULER_CAP_ENABLED |
                                     I915_SCHEDULER_CAP_PRIORITY);
 
-               if (intel_uc_uses_guc_submission(&i915->gt.uc))
+               if (intel_uc_uses_guc_submission(&to_gt(i915)->uc))
                        enabled |= I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP;
 
                for (i = 0; i < ARRAY_SIZE(map); i++) {
index 60b9b8b73758da40148b3c122c649e6c0c05c1d2..b1bb3c9f08cec32b5b3b08b694a362a3256d6567 100644 (file)
@@ -1215,7 +1215,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
 {
        int ret;
 
-       ret = ggtt_probe_hw(&i915->ggtt, &i915->gt);
+       ret = ggtt_probe_hw(&i915->ggtt, to_gt(i915));
        if (ret)
                return ret;
 
index 07ff7ba7b2b715678f3c22c86eb4f6605bea1792..36eb980d757e60a0108a5f41e9c0089c6b66ec69 100644 (file)
@@ -2302,7 +2302,7 @@ unsigned long i915_read_mch_val(void)
                return 0;
 
        with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
-               struct intel_ips *ips = &i915->gt.rps.ips;
+               struct intel_ips *ips = &to_gt(i915)->rps.ips;
 
                spin_lock_irq(&mchdev_lock);
                chipset_val = __ips_chipset_val(ips);
@@ -2329,7 +2329,7 @@ bool i915_gpu_raise(void)
        if (!i915)
                return false;
 
-       rps = &i915->gt.rps;
+       rps = &to_gt(i915)->rps;
 
        spin_lock_irq(&mchdev_lock);
        if (rps->max_freq_softlimit < rps->max_freq)
@@ -2356,7 +2356,7 @@ bool i915_gpu_lower(void)
        if (!i915)
                return false;
 
-       rps = &i915->gt.rps;
+       rps = &to_gt(i915)->rps;
 
        spin_lock_irq(&mchdev_lock);
        if (rps->max_freq_softlimit > rps->min_freq)
@@ -2382,7 +2382,7 @@ bool i915_gpu_busy(void)
        if (!i915)
                return false;
 
-       ret = i915->gt.awake;
+       ret = to_gt(i915)->awake;
 
        drm_dev_put(&i915->drm);
        return ret;
@@ -2405,11 +2405,11 @@ bool i915_gpu_turbo_disable(void)
        if (!i915)
                return false;
 
-       rps = &i915->gt.rps;
+       rps = &to_gt(i915)->rps;
 
        spin_lock_irq(&mchdev_lock);
        rps->max_freq_softlimit = rps->min_freq;
-       ret = !__gen5_rps_set(&i915->gt.rps, rps->min_freq);
+       ret = !__gen5_rps_set(&to_gt(i915)->rps, rps->min_freq);
        spin_unlock_irq(&mchdev_lock);
 
        drm_dev_put(&i915->drm);
index 3113266c286e9a7926c1ac4cb4a11064e51b4bfe..ab3277a3d5939916a9b624ed23af977547ba4f26 100644 (file)
@@ -929,7 +929,7 @@ hsw_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 static void
 gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
 {
-       const struct sseu_dev_info *sseu = &i915->gt.info.sseu;
+       const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu;
        unsigned int slice, subslice;
        u32 mcr, mcr_mask;
 
index bb99fc03f5039713e40485c0c89222c3206e8b52..a94b8d56c4bb16d326c28e4e5eb622ce76adaa64 100644 (file)
@@ -345,7 +345,7 @@ struct intel_engine_cs *mock_engine(struct drm_i915_private *i915,
        struct mock_engine *engine;
 
        GEM_BUG_ON(id >= I915_NUM_ENGINES);
-       GEM_BUG_ON(!i915->gt.uncore);
+       GEM_BUG_ON(!to_gt(i915)->uncore);
 
        engine = kzalloc(sizeof(*engine) + PAGE_SIZE, GFP_KERNEL);
        if (!engine)
@@ -353,8 +353,8 @@ struct intel_engine_cs *mock_engine(struct drm_i915_private *i915,
 
        /* minimal engine setup for requests */
        engine->base.i915 = i915;
-       engine->base.gt = &i915->gt;
-       engine->base.uncore = i915->gt.uncore;
+       engine->base.gt = to_gt(i915);
+       engine->base.uncore = to_gt(i915)->uncore;
        snprintf(engine->base.name, sizeof(engine->base.name), "%s", name);
        engine->base.id = id;
        engine->base.mask = BIT(id);
@@ -377,8 +377,8 @@ struct intel_engine_cs *mock_engine(struct drm_i915_private *i915,
 
        engine->base.release = mock_engine_release;
 
-       i915->gt.engine[id] = &engine->base;
-       i915->gt.engine_class[0][id] = &engine->base;
+       to_gt(i915)->engine[id] = &engine->base;
+       to_gt(i915)->engine_class[0][id] = &engine->base;
 
        /* fake hw queue */
        spin_lock_init(&engine->hw_lock);
index fa7b99a671dddf9fe36f26df73ec9d7e36121c93..76fbae358072df64a90547ab7abee27f7ad15abd 100644 (file)
@@ -442,7 +442,7 @@ int intel_context_live_selftests(struct drm_i915_private *i915)
                SUBTEST(live_active_context),
                SUBTEST(live_remote_context),
        };
-       struct intel_gt *gt = &i915->gt;
+       struct intel_gt *gt = to_gt(i915);
 
        if (intel_gt_is_wedged(gt))
                return 0;
index 262764f6d90a6a482664d6a780fff3676308491a..57fea9ea1705846a1eacc39190eb18238d77bb29 100644 (file)
@@ -12,7 +12,7 @@ int intel_engine_live_selftests(struct drm_i915_private *i915)
                live_engine_pm_selftests,
                NULL,
        };
-       struct intel_gt *gt = &i915->gt;
+       struct intel_gt *gt = to_gt(i915);
        typeof(*tests) *fn;
 
        for (fn = tests; *fn; fn++) {
index 64abf5feabfaaa6bd68c391b404f4d32de04d517..1b75f478d1b83421924e9fa7b0b6afc1f16cde2d 100644 (file)
@@ -361,10 +361,10 @@ int intel_engine_cs_perf_selftests(struct drm_i915_private *i915)
                SUBTEST(perf_mi_noop),
        };
 
-       if (intel_gt_is_wedged(&i915->gt))
+       if (intel_gt_is_wedged(to_gt(i915)))
                return 0;
 
-       return intel_gt_live_subtests(tests, &i915->gt);
+       return intel_gt_live_subtests(tests, to_gt(i915));
 }
 
 static int intel_mmio_bases_check(void *arg)
index 6e6e4d747ccaf9d185e7b3d2f216b2abb9f9f905..273d440a53e3f4c4d75bfdafdf1cef8c5fef386a 100644 (file)
@@ -378,13 +378,13 @@ int intel_heartbeat_live_selftests(struct drm_i915_private *i915)
        int saved_hangcheck;
        int err;
 
-       if (intel_gt_is_wedged(&i915->gt))
+       if (intel_gt_is_wedged(to_gt(i915)))
                return 0;
 
        saved_hangcheck = i915->params.enable_hangcheck;
        i915->params.enable_hangcheck = INT_MAX;
 
-       err = intel_gt_live_subtests(tests, &i915->gt);
+       err = intel_gt_live_subtests(tests, to_gt(i915));
 
        i915->params.enable_hangcheck = saved_hangcheck;
        return err;
index b367ecfa42de9fdd0f0f54cfd79dc3375e2dc382..e10da897e07a419cc2ea4e6dcbd89e8a8a44a67c 100644 (file)
@@ -4502,11 +4502,11 @@ int intel_execlists_live_selftests(struct drm_i915_private *i915)
                SUBTEST(live_virtual_reset),
        };
 
-       if (i915->gt.submission_method != INTEL_SUBMISSION_ELSP)
+       if (to_gt(i915)->submission_method != INTEL_SUBMISSION_ELSP)
                return 0;
 
-       if (intel_gt_is_wedged(&i915->gt))
+       if (intel_gt_is_wedged(to_gt(i915)))
                return 0;
 
-       return intel_gt_live_subtests(tests, &i915->gt);
+       return intel_gt_live_subtests(tests, to_gt(i915));
 }
index b9441217ca3d4de4af74b2ee0b796bb25616bbfe..ff86920eec82814d5d4ad82c0fa53c90e398dc7d 100644 (file)
@@ -193,10 +193,10 @@ int intel_gt_pm_live_selftests(struct drm_i915_private *i915)
                SUBTEST(live_gt_resume),
        };
 
-       if (intel_gt_is_wedged(&i915->gt))
+       if (intel_gt_is_wedged(to_gt(i915)))
                return 0;
 
-       return intel_gt_live_subtests(tests, &i915->gt);
+       return intel_gt_live_subtests(tests, to_gt(i915));
 }
 
 int intel_gt_pm_late_selftests(struct drm_i915_private *i915)
@@ -210,8 +210,8 @@ int intel_gt_pm_late_selftests(struct drm_i915_private *i915)
                SUBTEST(live_rc6_ctx_wa),
        };
 
-       if (intel_gt_is_wedged(&i915->gt))
+       if (intel_gt_is_wedged(to_gt(i915)))
                return 0;
 
-       return intel_gt_live_subtests(tests, &i915->gt);
+       return intel_gt_live_subtests(tests, to_gt(i915));
 }
index e5ad4d5a91c05a331e922a2d1890db31c27ba8b0..15d63435ec4d26d3d38a6b37401a1c20564cd2a2 100644 (file)
@@ -2018,7 +2018,7 @@ int intel_hangcheck_live_selftests(struct drm_i915_private *i915)
                SUBTEST(igt_reset_evict_fence),
                SUBTEST(igt_handle_error),
        };
-       struct intel_gt *gt = &i915->gt;
+       struct intel_gt *gt = to_gt(i915);
        intel_wakeref_t wakeref;
        int err;
 
index b0977a3b699b856cd63336defc0309feff16c6a5..618c905daa19c4c84ae890ed79ab17f7adf4a59b 100644 (file)
@@ -1847,5 +1847,5 @@ int intel_lrc_live_selftests(struct drm_i915_private *i915)
        if (!HAS_LOGICAL_RING_CONTEXTS(i915))
                return 0;
 
-       return intel_gt_live_subtests(tests, &i915->gt);
+       return intel_gt_live_subtests(tests, to_gt(i915));
 }
index e21787301bbddc65bfbe01c515bb34ca82ee20d6..f637691b5bcb155d2d74180fb56b721d5c1c33bb 100644 (file)
@@ -442,7 +442,7 @@ int intel_migrate_live_selftests(struct drm_i915_private *i915)
                SUBTEST(thread_global_copy),
                SUBTEST(thread_global_clear),
        };
-       struct intel_gt *gt = &i915->gt;
+       struct intel_gt *gt = to_gt(i915);
 
        if (!gt->migrate.context)
                return 0;
@@ -658,7 +658,7 @@ int intel_migrate_perf_selftests(struct drm_i915_private *i915)
                SUBTEST(perf_clear_blt),
                SUBTEST(perf_copy_blt),
        };
-       struct intel_gt *gt = &i915->gt;
+       struct intel_gt *gt = to_gt(i915);
 
        if (intel_gt_is_wedged(gt))
                return 0;
index 13d25bf2a94aaff73e8926cdf6c99750695ee09b..c1d861333c44cc0821c4223f57fe06ba20750e7b 100644 (file)
@@ -451,5 +451,5 @@ int intel_mocs_live_selftests(struct drm_i915_private *i915)
        if (!get_mocs_settings(i915, &table))
                return 0;
 
-       return intel_gt_live_subtests(tests, &i915->gt);
+       return intel_gt_live_subtests(tests, to_gt(i915));
 }
index 7a50c9f4071b42e56aaaef421ac04724501355a7..8a873f6bda7fd9e9560eef42aade86563bc10def 100644 (file)
@@ -376,7 +376,7 @@ int intel_reset_live_selftests(struct drm_i915_private *i915)
                SUBTEST(igt_atomic_reset),
                SUBTEST(igt_atomic_engine_reset),
        };
-       struct intel_gt *gt = &i915->gt;
+       struct intel_gt *gt = to_gt(i915);
 
        if (!intel_has_gpu_reset(gt))
                return 0;
index 041954408d0fdbfe8988e82189c655043b921990..70f9ac1ec2c76ffc7ca35a3c1ec1a51e7a6c59d8 100644 (file)
@@ -291,8 +291,8 @@ int intel_ring_submission_live_selftests(struct drm_i915_private *i915)
                SUBTEST(live_ctx_switch_wa),
        };
 
-       if (i915->gt.submission_method > INTEL_SUBMISSION_RING)
+       if (to_gt(i915)->submission_method > INTEL_SUBMISSION_RING)
                return 0;
 
-       return intel_gt_live_subtests(tests, &i915->gt);
+       return intel_gt_live_subtests(tests, to_gt(i915));
 }
index 9334bad131a26b8157bf0097a3744d14901e5b52..b768cea5943ddcf014bd121cb4a63309c2806e86 100644 (file)
@@ -39,7 +39,7 @@ static int slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 freq)
 static int live_slpc_clamp_min(void *arg)
 {
        struct drm_i915_private *i915 = arg;
-       struct intel_gt *gt = &i915->gt;
+       struct intel_gt *gt = to_gt(i915);
        struct intel_guc_slpc *slpc = &gt->uc.guc.slpc;
        struct intel_rps *rps = &gt->rps;
        struct intel_engine_cs *engine;
@@ -166,7 +166,7 @@ static int live_slpc_clamp_min(void *arg)
 static int live_slpc_clamp_max(void *arg)
 {
        struct drm_i915_private *i915 = arg;
-       struct intel_gt *gt = &i915->gt;
+       struct intel_gt *gt = to_gt(i915);
        struct intel_guc_slpc *slpc;
        struct intel_rps *rps;
        struct intel_engine_cs *engine;
@@ -304,7 +304,7 @@ int intel_slpc_live_selftests(struct drm_i915_private *i915)
                SUBTEST(live_slpc_clamp_min),
        };
 
-       if (intel_gt_is_wedged(&i915->gt))
+       if (intel_gt_is_wedged(to_gt(i915)))
                return 0;
 
        return i915_live_subtests(tests, i915);
index d0b6a3afcf44e0c1028c780b9c4049359b4bced5..e2eb686a9763e8f1c191dda6d85993f28909699a 100644 (file)
@@ -159,7 +159,7 @@ static int mock_hwsp_freelist(void *arg)
        INIT_RADIX_TREE(&state.cachelines, GFP_KERNEL);
        state.prng = I915_RND_STATE_INITIALIZER(i915_selftest.random_seed);
 
-       state.gt = &i915->gt;
+       state.gt = to_gt(i915);
 
        /*
         * Create a bunch of timelines and check that their HWSP do not overlap.
@@ -1416,8 +1416,8 @@ int intel_timeline_live_selftests(struct drm_i915_private *i915)
                SUBTEST(live_hwsp_rollover_user),
        };
 
-       if (intel_gt_is_wedged(&i915->gt))
+       if (intel_gt_is_wedged(to_gt(i915)))
                return 0;
 
-       return intel_gt_live_subtests(tests, &i915->gt);
+       return intel_gt_live_subtests(tests, to_gt(i915));
 }
index 962e91ba3be4969a76e4e9191b291c6a45c48dc5..0287c2573c51bc03750380f5cba1abebe741e78a 100644 (file)
@@ -1387,8 +1387,8 @@ int intel_workarounds_live_selftests(struct drm_i915_private *i915)
                SUBTEST(live_engine_reset_workarounds),
        };
 
-       if (intel_gt_is_wedged(&i915->gt))
+       if (intel_gt_is_wedged(to_gt(i915)))
                return 0;
 
-       return intel_gt_live_subtests(tests, &i915->gt);
+       return intel_gt_live_subtests(tests, to_gt(i915));
 }
index 22c1c12369f2ffcabe96e7a07e58b3a3c70d3b3c..13b27b8ff74e5ddd019fb07e5ec4ad5dcd83a234 100644 (file)
@@ -623,7 +623,7 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
        if (unlikely(ret < 0))
                return ret;
 
-       intel_guc_pm_intrmsk_enable(&i915->gt);
+       intel_guc_pm_intrmsk_enable(to_gt(i915));
 
        slpc_get_rp_values(slpc);
 
index 2ae414446112ce97bdcff3bdcea647656c4b5a8e..d3327b802b76146e0b6801d25d5d45052a0baea6 100644 (file)
@@ -288,7 +288,7 @@ int intel_guc_live_selftests(struct drm_i915_private *i915)
                SUBTEST(intel_guc_scrub_ctbs),
                SUBTEST(intel_guc_steal_guc_ids),
        };
-       struct intel_gt *gt = &i915->gt;
+       struct intel_gt *gt = to_gt(i915);
 
        if (intel_gt_is_wedged(gt))
                return 0;
index 50953c8e8b5372ebef9c8780401a109947bf8c7d..1297ddbf7f889b56aaa94739b1bf55d581a93bbc 100644 (file)
@@ -167,7 +167,7 @@ int intel_guc_multi_lrc_live_selftests(struct drm_i915_private *i915)
        static const struct i915_subtest tests[] = {
                SUBTEST(intel_guc_multi_lrc_basic),
        };
-       struct intel_gt *gt = &i915->gt;
+       struct intel_gt *gt = to_gt(i915);
 
        if (intel_gt_is_wedged(gt))
                return 0;