#define REG_RSVD3_8723B 0x0168
#define REG_C2HEVT_MSG_NORMAL_8723B 0x01A0
#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1
-#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2
+#define REG_C2HEVT_CMD_CONTENT_88XX 0x01A2
#define REG_C2HEVT_CMD_LEN_88XX 0x01AE
#define REG_C2HEVT_CLEAR_8723B 0x01AF
#define REG_MCUTST_1_8723B 0x01C0
#define IMR_RXFOVW_8723B BIT8 /* Receive FIFO Overflow */
/* 2 ACMHWCTRL 0x05C0 */
-#define AcmHw_HwEn_8723B BIT(0)
-#define AcmHw_VoqEn_8723B BIT(1)
-#define AcmHw_ViqEn_8723B BIT(2)
-#define AcmHw_BeqEn_8723B BIT(3)
-#define AcmHw_VoqStatus_8723B BIT(5)
-#define AcmHw_ViqStatus_8723B BIT(6)
-#define AcmHw_BeqStatus_8723B BIT(7)
+#define ACMHW_HWEN_8723B BIT(0)
+#define ACMHW_VOQEN_8723B BIT(1)
+#define ACMHW_VIQEN_8723B BIT(2)
+#define ACMHW_BEQEN_8723B BIT(3)
+#define ACMHW_VOQSTATUS_8723B BIT(5)
+#define ACMHW_VIQSTATUS_8723B BIT(6)
+#define ACMHW_BEQSTATUS_8723B BIT(7)
/* 8195 (RCR) Receive Configuration Register (Offset 0x608, 32 bits) */
#define RCR_TCPOFLD_EN BIT25 /* Enable TCP checksum offload */