Merge tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux
authorLinus Torvalds <torvalds@linux-foundation.org>
Sun, 21 Dec 2014 00:42:36 +0000 (16:42 -0800)
committerLinus Torvalds <torvalds@linux-foundation.org>
Sun, 21 Dec 2014 00:42:36 +0000 (16:42 -0800)
Pull clk framework updates from Mike Turquette:
 "This is much later than usual due to several last minute bugs that had
  to be addressed.  As usual the majority of changes are new drivers and
  modifications to existing drivers.  The core recieved many fixes along
  with the groundwork for several large changes coming in the future
  which will better parition clock providers from clock consumers"

* tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux: (86 commits)
  clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated
  ARM: OMAP3: clock: fix boot breakage in legacy mode
  ARM: OMAP2+: clock: fix DPLL code to use new determine rate APIs
  clk: Really fix deadlock with mmap_sem
  clk: mmp: fix sparse non static symbol warning
  clk: Change clk_ops->determine_rate to return a clk_hw as the best parent
  clk: change clk_debugfs_add_file to take a struct clk_hw
  clk: Don't expose __clk_get_accuracy
  clk: Don't try to use a struct clk* after it could have been freed
  clk: Remove unused function __clk_get_prepare_count
  clk: samsung: Fix double add of syscore ops after driver rebind
  clk: samsung: exynos4: set parent of sclk_hdmiphy to hdmi
  clk: samsung: exynos4415: Fix build with PM_SLEEP disabled
  clk: samsung: remove unnecessary inclusion of header files from clk.h
  clk: samsung: remove unnecessary CONFIG_OF from clk.c
  clk: samsung: Spelling s/bwtween/between/
  clk: rockchip: Add support for the mmc clock phases using the framework
  clk: rockchip: add bindings for the mmc clocks
  clk: rockchip: rk3288 export i2s0_clkout for use in DT
  clk: rockchip: use clock ID for DMC (memory controller) on rk3288
  ...

94 files changed:
Documentation/clk.txt
Documentation/devicetree/bindings/clock/exynos4415-clock.txt [new file with mode: 0644]
Documentation/devicetree/bindings/clock/exynos7-clock.txt [new file with mode: 0644]
Documentation/devicetree/bindings/clock/marvell,mmp2.txt [new file with mode: 0644]
Documentation/devicetree/bindings/clock/marvell,pxa168.txt [new file with mode: 0644]
Documentation/devicetree/bindings/clock/marvell,pxa910.txt [new file with mode: 0644]
Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
Documentation/devicetree/bindings/clock/sunxi.txt
MAINTAINERS
arch/arm/boot/dts/Makefile
arch/arm/boot/dts/mmp2-brownstone.dts
arch/arm/boot/dts/mmp2.dtsi
arch/arm/boot/dts/pxa168-aspenite.dts
arch/arm/boot/dts/pxa168.dtsi
arch/arm/boot/dts/pxa910-dkb.dts
arch/arm/boot/dts/pxa910.dtsi
arch/arm/boot/dts/sun4i-a10.dtsi
arch/arm/boot/dts/sun5i-a10s.dtsi
arch/arm/boot/dts/sun5i-a13.dtsi
arch/arm/boot/dts/sun6i-a31.dtsi
arch/arm/boot/dts/sun7i-a20.dtsi
arch/arm/boot/dts/sun8i-a23.dtsi
arch/arm/mach-mmp/Kconfig
arch/arm/mach-mmp/mmp-dt.c
arch/arm/mach-mmp/mmp2-dt.c
arch/arm/mach-omap2/cclock3xxx_data.c
arch/arm/mach-omap2/dpll3xxx.c
arch/arm/mach-omap2/dpll44xx.c
arch/mips/alchemy/common/clock.c
drivers/clk/at91/clk-programmable.c
drivers/clk/bcm/clk-kona.c
drivers/clk/clk-composite.c
drivers/clk/clk-mux.c
drivers/clk/clk-s2mps11.c
drivers/clk/clk.c
drivers/clk/hisilicon/clk-hi3620.c
drivers/clk/mmp/Makefile
drivers/clk/mmp/clk-frac.c
drivers/clk/mmp/clk-gate.c [new file with mode: 0644]
drivers/clk/mmp/clk-mix.c [new file with mode: 0644]
drivers/clk/mmp/clk-mmp2.c
drivers/clk/mmp/clk-of-mmp2.c [new file with mode: 0644]
drivers/clk/mmp/clk-of-pxa168.c [new file with mode: 0644]
drivers/clk/mmp/clk-of-pxa910.c [new file with mode: 0644]
drivers/clk/mmp/clk-pxa168.c
drivers/clk/mmp/clk-pxa910.c
drivers/clk/mmp/clk.c [new file with mode: 0644]
drivers/clk/mmp/clk.h
drivers/clk/mmp/reset.c [new file with mode: 0644]
drivers/clk/mmp/reset.h [new file with mode: 0644]
drivers/clk/pxa/Makefile
drivers/clk/pxa/clk-pxa.c
drivers/clk/pxa/clk-pxa.h
drivers/clk/pxa/clk-pxa25x.c [new file with mode: 0644]
drivers/clk/pxa/clk-pxa27x.c
drivers/clk/qcom/clk-pll.c
drivers/clk/qcom/clk-rcg.c
drivers/clk/qcom/clk-rcg2.c
drivers/clk/rockchip/Makefile
drivers/clk/rockchip/clk-mmc-phase.c [new file with mode: 0644]
drivers/clk/rockchip/clk-pll.c
drivers/clk/rockchip/clk-rk3188.c
drivers/clk/rockchip/clk-rk3288.c
drivers/clk/rockchip/clk.c
drivers/clk/rockchip/clk.h
drivers/clk/samsung/Makefile
drivers/clk/samsung/clk-exynos-audss.c
drivers/clk/samsung/clk-exynos4.c
drivers/clk/samsung/clk-exynos4415.c [new file with mode: 0644]
drivers/clk/samsung/clk-exynos5260.c
drivers/clk/samsung/clk-exynos7.c [new file with mode: 0644]
drivers/clk/samsung/clk-pll.c
drivers/clk/samsung/clk-pll.h
drivers/clk/samsung/clk.c
drivers/clk/samsung/clk.h
drivers/clk/shmobile/clk-div6.c
drivers/clk/sunxi/Makefile
drivers/clk/sunxi/clk-a20-gmac.c
drivers/clk/sunxi/clk-factors.c
drivers/clk/sunxi/clk-factors.h
drivers/clk/sunxi/clk-mod0.c
drivers/clk/sunxi/clk-sun6i-ar100.c
drivers/clk/sunxi/clk-sun8i-mbus.c
drivers/clk/sunxi/clk-sun9i-core.c [new file with mode: 0644]
drivers/clk/sunxi/clk-sunxi.c
include/dt-bindings/clock/exynos4415.h [new file with mode: 0644]
include/dt-bindings/clock/exynos7-clk.h [new file with mode: 0644]
include/dt-bindings/clock/marvell,mmp2.h [new file with mode: 0644]
include/dt-bindings/clock/marvell,pxa168.h [new file with mode: 0644]
include/dt-bindings/clock/marvell,pxa910.h [new file with mode: 0644]
include/dt-bindings/clock/rk3288-cru.h
include/linux/clk-provider.h
include/linux/clk/ti.h

index 1fee72f4d3319715f9efc2e258458cd807f3a537..4ff84623d5e16eb42c17f90eb1851eea19b9d82f 100644 (file)
@@ -74,7 +74,7 @@ the operations defined in clk.h:
                long            (*determine_rate)(struct clk_hw *hw,
                                                unsigned long rate,
                                                unsigned long *best_parent_rate,
-                                               struct clk **best_parent_clk);
+                                               struct clk_hw **best_parent_clk);
                int             (*set_parent)(struct clk_hw *hw, u8 index);
                u8              (*get_parent)(struct clk_hw *hw);
                int             (*set_rate)(struct clk_hw *hw,
diff --git a/Documentation/devicetree/bindings/clock/exynos4415-clock.txt b/Documentation/devicetree/bindings/clock/exynos4415-clock.txt
new file mode 100644 (file)
index 0000000..847d98b
--- /dev/null
@@ -0,0 +1,38 @@
+* Samsung Exynos4415 Clock Controller
+
+The Exynos4415 clock controller generates and supplies clock to various
+consumer devices within the Exynos4415 SoC.
+
+Required properties:
+
+- compatible: should be one of the following:
+  - "samsung,exynos4415-cmu" - for the main system clocks controller
+    (CMU_LEFTBUS, CMU_RIGHTBUS, CMU_TOP, CMU_CPU clock domains).
+  - "samsung,exynos4415-cmu-dmc" - for the Exynos4415 SoC DRAM Memory
+    Controller (DMC) domain clock controller.
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos4415.h header and can be used in device
+tree sources.
+
+Example 1: An example of a clock controller node is listed below.
+
+       cmu: clock-controller@10030000 {
+               compatible = "samsung,exynos4415-cmu";
+               reg = <0x10030000 0x18000>;
+               #clock-cells = <1>;
+       };
+
+       cmu-dmc: clock-controller@105C0000 {
+               compatible = "samsung,exynos4415-cmu-dmc";
+               reg = <0x105C0000 0x3000>;
+               #clock-cells = <1>;
+       };
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
new file mode 100644 (file)
index 0000000..6d3d5f8
--- /dev/null
@@ -0,0 +1,93 @@
+* Samsung Exynos7 Clock Controller
+
+Exynos7 clock controller has various blocks which are instantiated
+independently from the device-tree. These clock controllers
+generate and supply clocks to various hardware blocks within
+the SoC.
+
+Each clock is assigned an identifier and client nodes can use
+this identifier to specify the clock which they consume. All
+available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos7-clk.h header and can be used in
+device tree sources.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It
+is expected that they are defined using standard clock bindings
+with following clock-output-names:
+
+ - "fin_pll" - PLL input clock from XXTI
+
+Required Properties for Clock Controller:
+
+ - compatible: clock controllers will use one of the following
+       compatible strings to indicate the clock controller
+       functionality.
+
+       - "samsung,exynos7-clock-topc"
+       - "samsung,exynos7-clock-top0"
+       - "samsung,exynos7-clock-top1"
+       - "samsung,exynos7-clock-ccore"
+       - "samsung,exynos7-clock-peric0"
+       - "samsung,exynos7-clock-peric1"
+       - "samsung,exynos7-clock-peris"
+       - "samsung,exynos7-clock-fsys0"
+       - "samsung,exynos7-clock-fsys1"
+
+ - reg: physical base address of the controller and the length of
+       memory mapped region.
+
+ - #clock-cells: should be 1.
+
+ - clocks: list of clock identifiers which are fed as the input to
+       the given clock controller. Please refer the next section to
+       find the input clocks for a given controller.
+
+- clock-names: list of names of clocks which are fed as the input
+       to the given clock controller.
+
+Input clocks for top0 clock controller:
+       - fin_pll
+       - dout_sclk_bus0_pll
+       - dout_sclk_bus1_pll
+       - dout_sclk_cc_pll
+       - dout_sclk_mfc_pll
+
+Input clocks for top1 clock controller:
+       - fin_pll
+       - dout_sclk_bus0_pll
+       - dout_sclk_bus1_pll
+       - dout_sclk_cc_pll
+       - dout_sclk_mfc_pll
+
+Input clocks for ccore clock controller:
+       - fin_pll
+       - dout_aclk_ccore_133
+
+Input clocks for peric0 clock controller:
+       - fin_pll
+       - dout_aclk_peric0_66
+       - sclk_uart0
+
+Input clocks for peric1 clock controller:
+       - fin_pll
+       - dout_aclk_peric1_66
+       - sclk_uart1
+       - sclk_uart2
+       - sclk_uart3
+
+Input clocks for peris clock controller:
+       - fin_pll
+       - dout_aclk_peris_66
+
+Input clocks for fsys0 clock controller:
+       - fin_pll
+       - dout_aclk_fsys0_200
+       - dout_sclk_mmc2
+
+Input clocks for fsys1 clock controller:
+       - fin_pll
+       - dout_aclk_fsys1_200
+       - dout_sclk_mmc0
+       - dout_sclk_mmc1
diff --git a/Documentation/devicetree/bindings/clock/marvell,mmp2.txt b/Documentation/devicetree/bindings/clock/marvell,mmp2.txt
new file mode 100644 (file)
index 0000000..af376a0
--- /dev/null
@@ -0,0 +1,21 @@
+* Marvell MMP2 Clock Controller
+
+The MMP2 clock subsystem generates and supplies clock to various
+controllers within the MMP2 SoC.
+
+Required Properties:
+
+- compatible: should be one of the following.
+  - "marvell,mmp2-clock" - controller compatible with MMP2 SoC.
+
+- reg: physical base address of the clock subsystem and length of memory mapped
+  region. There are 3 places in SOC has clock control logic:
+  "mpmu", "apmu", "apbc". So three reg spaces need to be defined.
+
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in <dt-bindings/clock/marvell-mmp2.h>.
diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa168.txt b/Documentation/devicetree/bindings/clock/marvell,pxa168.txt
new file mode 100644 (file)
index 0000000..c62eb1d
--- /dev/null
@@ -0,0 +1,21 @@
+* Marvell PXA168 Clock Controller
+
+The PXA168 clock subsystem generates and supplies clock to various
+controllers within the PXA168 SoC.
+
+Required Properties:
+
+- compatible: should be one of the following.
+  - "marvell,pxa168-clock" - controller compatible with PXA168 SoC.
+
+- reg: physical base address of the clock subsystem and length of memory mapped
+  region. There are 3 places in SOC has clock control logic:
+  "mpmu", "apmu", "apbc". So three reg spaces need to be defined.
+
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in <dt-bindings/clock/marvell,pxa168.h>.
diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa910.txt b/Documentation/devicetree/bindings/clock/marvell,pxa910.txt
new file mode 100644 (file)
index 0000000..d9f41f3
--- /dev/null
@@ -0,0 +1,21 @@
+* Marvell PXA910 Clock Controller
+
+The PXA910 clock subsystem generates and supplies clock to various
+controllers within the PXA910 SoC.
+
+Required Properties:
+
+- compatible: should be one of the following.
+  - "marvell,pxa910-clock" - controller compatible with PXA910 SoC.
+
+- reg: physical base address of the clock subsystem and length of memory mapped
+  region. There are 4 places in SOC has clock control logic:
+  "mpmu", "apmu", "apbc", "apbcp". So four reg spaces need to be defined.
+
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in <dt-bindings/clock/marvell-pxa910.h>.
index 952e373178d27b10d4fca3bdffc8519d5f4531ae..054f65f9319cd71c74936dcab565901559a9d280 100644 (file)
@@ -7,11 +7,16 @@ to 64.
 Required Properties:
 
   - compatible: Must be one of the following
+    - "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks
+    - "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks
     - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
     - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks
+    - "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks
     - "renesas,cpg-div6-clock" for generic DIV6 clocks
   - reg: Base address and length of the memory resource used by the DIV6 clock
-  - clocks: Reference to the parent clock
+  - clocks: Reference to the parent clock(s); either one, four, or eight
+    clocks must be specified.  For clocks with multiple parents, invalid
+    settings must be specified as "<0>".
   - #clock-cells: Must be 0
   - clock-output-names: The name of the clock as a free-form string
 
@@ -19,10 +24,11 @@ Required Properties:
 Example
 -------
 
-       sd2_clk: sd2_clk@e6150078 {
-               compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
-               reg = <0 0xe6150078 0 4>;
-               clocks = <&pll1_div2_clk>;
+       sdhi2_clk: sdhi2_clk@e615007c {
+               compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
+               reg = <0 0xe615007c 0 4>;
+               clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
+                        <0>, <&extal2_clk>;
                #clock-cells = <0>;
-               clock-output-names = "sd2";
+               clock-output-names = "sdhi2ck";
        };
index a5f52238c80d5f9b9560914f59e653e772b42bea..2e18676bd4b56503ce42ec4b4d368c32041fe1d0 100644 (file)
@@ -26,11 +26,11 @@ Required Properties:
     must appear in the same order as the output clocks.
   - #clock-cells: Must be 1
   - clock-output-names: The name of the clocks as free-form strings
-  - renesas,clock-indices: Indices of the gate clocks into the group (0 to 31)
+  - clock-indices: Indices of the gate clocks into the group (0 to 31)
 
-The clocks, clock-output-names and renesas,clock-indices properties contain one
-entry per gate clock. The MSTP groups are sparsely populated. Unimplemented
-gate clocks must not be declared.
+The clocks, clock-output-names and clock-indices properties contain one entry
+per gate clock. The MSTP groups are sparsely populated. Unimplemented gate
+clocks must not be declared.
 
 
 Example
index ed116df9c3e769a2ceef9cb4d1dd1eaf44473f38..67b2b99f2b339f0a35a8fddfd9127779542ca76b 100644 (file)
@@ -10,14 +10,17 @@ Required properties:
        "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
        "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
        "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
+       "allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80
        "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
        "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
        "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
+       "allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80
        "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
        "allwinner,sun4i-a10-axi-clk" - for the AXI clock
        "allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23
        "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
        "allwinner,sun4i-a10-ahb-clk" - for the AHB clock
+       "allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80
        "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
        "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
        "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
@@ -26,24 +29,29 @@ Required properties:
        "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
        "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
        "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
+       "allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
+       "allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80
+       "allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80
        "allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
        "allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
        "allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23
+       "allwinner,sun9i-a80-apb0-clk" - for the APB0 bus clock on A80
        "allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
        "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
        "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
        "allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
        "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
        "allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
+       "allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80
        "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
-       "allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing
+       "allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80
        "allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
        "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
        "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
        "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
        "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
        "allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23
-       "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
+       "allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
        "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
        "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
        "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
@@ -63,8 +71,9 @@ Required properties for all clocks:
        multiplexed clocks, the list order must match the hardware
        programming order.
 - #clock-cells : from common clock binding; shall be set to 0 except for
-       "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk" and
-       "allwinner,sun4i-pll6-clk" where it shall be set to 1
+       the following compatibles where it shall be set to 1:
+       "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk",
+       "allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk"
 - clock-output-names : shall be the corresponding names of the outputs.
        If the clock module only has one output, the name shall be the
        module name.
@@ -79,6 +88,12 @@ Clock consumers should specify the desired clocks they use with a
 "clocks" phandle cell. Consumers that are using a gated clock should
 provide an additional ID in their clock property. This ID is the
 offset of the bit controlling this particular gate in the register.
+For the other clocks with "#clock-cells" = 1, the additional ID shall
+refer to the index of the output.
+
+For "allwinner,sun6i-a31-pll6-clk", there are 2 outputs. The first output
+is the normal PLL6 output, or "pll6". The second output is rate doubled
+PLL6, or "pll6x2".
 
 For example:
 
@@ -106,6 +121,14 @@ pll5: clk@01c20020 {
        clock-output-names = "pll5_ddr", "pll5_other";
 };
 
+pll6: clk@01c20028 {
+       #clock-cells = <1>;
+       compatible = "allwinner,sun6i-a31-pll6-clk";
+       reg = <0x01c20028 0x4>;
+       clocks = <&osc24M>;
+       clock-output-names = "pll6", "pll6x2";
+};
+
 cpu: cpu@01c20054 {
        #clock-cells = <0>;
        compatible = "allwinner,sun4i-a10-cpu-clk";
index 08f671dad3e935850a8eb636b0c2afb195ce1461..ddb9ac8d32b3eddc46d66bd408392ae09b637ea7 100644 (file)
@@ -2576,8 +2576,9 @@ F:        drivers/media/platform/coda/
 
 COMMON CLK FRAMEWORK
 M:     Mike Turquette <mturquette@linaro.org>
+M:     Stephen Boyd <sboyd@codeaurora.org>
 L:     linux-kernel@vger.kernel.org
-T:     git git://git.linaro.org/people/mturquette/linux.git
+T:     git git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
 S:     Maintained
 F:     drivers/clk/
 X:     drivers/clk/clkdev.c
index 6a3d9a6c4497915587d4deceac8829e4736ea3f0..91bd5bd628576d6da17a10aa87afb52232087d06 100644 (file)
@@ -177,6 +177,9 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \
 dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
 dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
 dtb-$(CONFIG_MACH_MESON6) += meson6-atv1200.dtb
+dtb-$(CONFIG_ARCH_MMP) += pxa168-aspenite.dtb \
+       pxa910-dkb.dtb \
+       mmp2-brownstone.dtb
 dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
 dtb-$(CONFIG_ARCH_MXC) += \
        imx1-ads.dtb \
index 7f70a39459f649d7051b5423c754e356686762db..350208c5e1ed2f6d27d192d1c256ab58db5ecb27 100644 (file)
@@ -8,7 +8,7 @@
  */
 
 /dts-v1/;
-/include/ "mmp2.dtsi"
+#include "mmp2.dtsi"
 
 / {
        model = "Marvell MMP2 Brownstone Development Board";
index 4e8b08c628c7ee405efd864f743cbadc8a617321..766bbb8495b60d796ccd857c4965ab4f8d09721c 100644 (file)
@@ -7,7 +7,8 @@
  *  publishhed by the Free Software Foundation.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/marvell,mmp2.h>
 
 / {
        aliases {
                                compatible = "mrvl,mmp-uart";
                                reg = <0xd4030000 0x1000>;
                                interrupts = <27>;
+                               clocks = <&soc_clocks MMP2_CLK_UART0>;
+                               resets = <&soc_clocks MMP2_CLK_UART0>;
                                status = "disabled";
                        };
 
                                compatible = "mrvl,mmp-uart";
                                reg = <0xd4017000 0x1000>;
                                interrupts = <28>;
+                               clocks = <&soc_clocks MMP2_CLK_UART1>;
+                               resets = <&soc_clocks MMP2_CLK_UART1>;
                                status = "disabled";
                        };
 
                                compatible = "mrvl,mmp-uart";
                                reg = <0xd4018000 0x1000>;
                                interrupts = <24>;
+                               clocks = <&soc_clocks MMP2_CLK_UART2>;
+                               resets = <&soc_clocks MMP2_CLK_UART2>;
                                status = "disabled";
                        };
 
                                compatible = "mrvl,mmp-uart";
                                reg = <0xd4016000 0x1000>;
                                interrupts = <46>;
+                               clocks = <&soc_clocks MMP2_CLK_UART3>;
+                               resets = <&soc_clocks MMP2_CLK_UART3>;
                                status = "disabled";
                        };
 
                                #gpio-cells = <2>;
                                interrupts = <49>;
                                interrupt-names = "gpio_mux";
+                               clocks = <&soc_clocks MMP2_CLK_GPIO>;
+                               resets = <&soc_clocks MMP2_CLK_GPIO>;
                                interrupt-controller;
                                #interrupt-cells = <1>;
                                ranges;
                                compatible = "mrvl,mmp-twsi";
                                reg = <0xd4011000 0x1000>;
                                interrupts = <7>;
+                               clocks = <&soc_clocks MMP2_CLK_TWSI0>;
+                               resets = <&soc_clocks MMP2_CLK_TWSI0>;
                                #address-cells = <1>;
                                #size-cells = <0>;
                                mrvl,i2c-fast-mode;
                                compatible = "mrvl,mmp-twsi";
                                reg = <0xd4025000 0x1000>;
                                interrupts = <58>;
+                               clocks = <&soc_clocks MMP2_CLK_TWSI1>;
+                               resets = <&soc_clocks MMP2_CLK_TWSI1>;
                                status = "disabled";
                        };
 
                                interrupts = <1 0>;
                                interrupt-names = "rtc 1Hz", "rtc alarm";
                                interrupt-parent = <&intcmux5>;
+                               clocks = <&soc_clocks MMP2_CLK_RTC>;
+                               resets = <&soc_clocks MMP2_CLK_RTC>;
                                status = "disabled";
                        };
                };
+
+               soc_clocks: clocks{
+                       compatible = "marvell,mmp2-clock";
+                       reg = <0xd4050000 0x1000>,
+                             <0xd4282800 0x400>,
+                             <0xd4015000 0x1000>;
+                       reg-names = "mpmu", "apmu", "apbc";
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+               };
        };
 };
index e762facb3fa434473e2a1b53ca0a3c68f323c20a..0a988b3fb248ee46658bf1d65780f3f01b4582be 100644 (file)
@@ -8,7 +8,7 @@
  */
 
 /dts-v1/;
-/include/ "pxa168.dtsi"
+#include "pxa168.dtsi"
 
 / {
        model = "Marvell PXA168 Aspenite Development Board";
index 975dad21ac3890d4b81bb23a0d1bf2962a831e09..b899e25cbb1be973c60dc8a8d8c220c02cf3c039 100644 (file)
@@ -7,7 +7,8 @@
  *  publishhed by the Free Software Foundation.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/marvell,pxa168.h>
 
 / {
        aliases {
@@ -59,6 +60,8 @@
                                compatible = "mrvl,mmp-uart";
                                reg = <0xd4017000 0x1000>;
                                interrupts = <27>;
+                               clocks = <&soc_clocks PXA168_CLK_UART0>;
+                               resets = <&soc_clocks PXA168_CLK_UART0>;
                                status = "disabled";
                        };
 
@@ -66,6 +69,8 @@
                                compatible = "mrvl,mmp-uart";
                                reg = <0xd4018000 0x1000>;
                                interrupts = <28>;
+                               clocks = <&soc_clocks PXA168_CLK_UART1>;
+                               resets = <&soc_clocks PXA168_CLK_UART1>;
                                status = "disabled";
                        };
 
@@ -73,6 +78,8 @@
                                compatible = "mrvl,mmp-uart";
                                reg = <0xd4026000 0x1000>;
                                interrupts = <29>;
+                               clocks = <&soc_clocks PXA168_CLK_UART2>;
+                               resets = <&soc_clocks PXA168_CLK_UART2>;
                                status = "disabled";
                        };
 
@@ -84,6 +91,8 @@
                                gpio-controller;
                                #gpio-cells = <2>;
                                interrupts = <49>;
+                               clocks = <&soc_clocks PXA168_CLK_GPIO>;
+                               resets = <&soc_clocks PXA168_CLK_GPIO>;
                                interrupt-names = "gpio_mux";
                                interrupt-controller;
                                #interrupt-cells = <1>;
                                compatible = "mrvl,mmp-twsi";
                                reg = <0xd4011000 0x1000>;
                                interrupts = <7>;
+                               clocks = <&soc_clocks PXA168_CLK_TWSI0>;
+                               resets = <&soc_clocks PXA168_CLK_TWSI0>;
                                mrvl,i2c-fast-mode;
                                status = "disabled";
                        };
                                compatible = "mrvl,mmp-twsi";
                                reg = <0xd4025000 0x1000>;
                                interrupts = <58>;
+                               clocks = <&soc_clocks PXA168_CLK_TWSI1>;
+                               resets = <&soc_clocks PXA168_CLK_TWSI1>;
                                status = "disabled";
                        };
 
                                reg = <0xd4010000 0x1000>;
                                interrupts = <5 6>;
                                interrupt-names = "rtc 1Hz", "rtc alarm";
+                               clocks = <&soc_clocks PXA168_CLK_RTC>;
+                               resets = <&soc_clocks PXA168_CLK_RTC>;
                                status = "disabled";
                        };
                };
+
+               soc_clocks: clocks{
+                       compatible = "marvell,pxa168-clock";
+                       reg = <0xd4050000 0x1000>,
+                             <0xd4282800 0x400>,
+                             <0xd4015000 0x1000>;
+                       reg-names = "mpmu", "apmu", "apbc";
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+               };
        };
 };
index 595492aa505372047aab605aff58b043f16896f6..c82f2810ec73c2274b9c9f4a996cf5a31e530379 100644 (file)
@@ -8,7 +8,7 @@
  */
 
 /dts-v1/;
-/include/ "pxa910.dtsi"
+#include "pxa910.dtsi"
 
 / {
        model = "Marvell PXA910 DKB Development Board";
index 0247c622f580728f77f31dbb36d555d310f524d0..0868f6729be1eaf60fc6df14887f449e92f750c6 100644 (file)
@@ -7,7 +7,8 @@
  *  publishhed by the Free Software Foundation.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/marvell,pxa910.h>
 
 / {
        aliases {
@@ -71,6 +72,8 @@
                                compatible = "mrvl,mmp-uart";
                                reg = <0xd4017000 0x1000>;
                                interrupts = <27>;
+                               clocks = <&soc_clocks PXA910_CLK_UART0>;
+                               resets = <&soc_clocks PXA910_CLK_UART0>;
                                status = "disabled";
                        };
 
@@ -78,6 +81,8 @@
                                compatible = "mrvl,mmp-uart";
                                reg = <0xd4018000 0x1000>;
                                interrupts = <28>;
+                               clocks = <&soc_clocks PXA910_CLK_UART1>;
+                               resets = <&soc_clocks PXA910_CLK_UART1>;
                                status = "disabled";
                        };
 
@@ -85,6 +90,8 @@
                                compatible = "mrvl,mmp-uart";
                                reg = <0xd4036000 0x1000>;
                                interrupts = <59>;
+                               clocks = <&soc_clocks PXA910_CLK_UART2>;
+                               resets = <&soc_clocks PXA910_CLK_UART2>;
                                status = "disabled";
                        };
 
                                #gpio-cells = <2>;
                                interrupts = <49>;
                                interrupt-names = "gpio_mux";
+                               clocks = <&soc_clocks PXA910_CLK_GPIO>;
+                               resets = <&soc_clocks PXA910_CLK_GPIO>;
                                interrupt-controller;
                                #interrupt-cells = <1>;
                                ranges;
                                #size-cells = <0>;
                                reg = <0xd4011000 0x1000>;
                                interrupts = <7>;
+                               clocks = <&soc_clocks PXA910_CLK_TWSI0>;
+                               resets = <&soc_clocks PXA910_CLK_TWSI0>;
                                mrvl,i2c-fast-mode;
                                status = "disabled";
                        };
                                #size-cells = <0>;
                                reg = <0xd4037000 0x1000>;
                                interrupts = <54>;
+                               clocks = <&soc_clocks PXA910_CLK_TWSI1>;
+                               resets = <&soc_clocks PXA910_CLK_TWSI1>;
                                status = "disabled";
                        };
 
                                reg = <0xd4010000 0x1000>;
                                interrupts = <5 6>;
                                interrupt-names = "rtc 1Hz", "rtc alarm";
+                               clocks = <&soc_clocks PXA910_CLK_RTC>;
+                               resets = <&soc_clocks PXA910_CLK_RTC>;
                                status = "disabled";
                        };
                };
+
+               soc_clocks: clocks{
+                       compatible = "marvell,pxa910-clock";
+                       reg = <0xd4050000 0x1000>,
+                             <0xd4282800 0x400>,
+                             <0xd4015000 0x1000>,
+                             <0xd403b000 0x1000>;
+                       reg-names = "mpmu", "apmu", "apbc", "apbcp";
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+               };
        };
 };
index e3ab942fd1488c974824dc05445ad970158dbc5b..7b4099fcf81788714def505ff009e2b7a4948db2 100644 (file)
                                "apb0_ir1", "apb0_keypad";
                };
 
-               apb1_mux: apb1_mux@01c20058 {
-                       #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-a10-apb1-mux-clk";
-                       reg = <0x01c20058 0x4>;
-                       clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
-                       clock-output-names = "apb1_mux";
-               };
-
-               apb1: apb1@01c20058 {
+               apb1: clk@01c20058 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-apb1-clk";
                        reg = <0x01c20058 0x4>;
-                       clocks = <&apb1_mux>;
+                       clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
                        clock-output-names = "apb1";
                };
 
index 81ad4b94e812c7f16e1e885cfff7181249d5f61a..1b76667f3182694ffb7d055cb8f8e7230809a0bf 100644 (file)
                                "apb0_ir", "apb0_keypad";
                };
 
-               apb1_mux: apb1_mux@01c20058 {
-                       #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-a10-apb1-mux-clk";
-                       reg = <0x01c20058 0x4>;
-                       clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
-                       clock-output-names = "apb1_mux";
-               };
-
-               apb1: apb1@01c20058 {
+               apb1: clk@01c20058 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-apb1-clk";
                        reg = <0x01c20058 0x4>;
-                       clocks = <&apb1_mux>;
+                       clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
                        clock-output-names = "apb1";
                };
 
index b131068f4f351ca92e7df07d63641cec143c5fc2..c35217ea1f6473653b4d67ce953f3c761fa043a0 100644 (file)
                        clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
                };
 
-               apb1_mux: apb1_mux@01c20058 {
-                       #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-a10-apb1-mux-clk";
-                       reg = <0x01c20058 0x4>;
-                       clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
-                       clock-output-names = "apb1_mux";
-               };
-
-               apb1: apb1@01c20058 {
+               apb1: clk@01c20058 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-apb1-clk";
                        reg = <0x01c20058 0x4>;
-                       clocks = <&apb1_mux>;
+                       clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
                        clock-output-names = "apb1";
                };
 
index a400172a8a52255c6ed7bd4226e3f9ee016d2dfc..f47156b6572bbaf09872686b70f09268200c3cc9 100644 (file)
                                        "apb1_daudio1";
                };
 
-               apb2_mux: apb2_mux@01c20058 {
+               apb2: clk@01c20058 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-a10-apb1-mux-clk";
+                       compatible = "allwinner,sun4i-a10-apb1-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
-                       clock-output-names = "apb2_mux";
-               };
-
-               apb2: apb2@01c20058 {
-                       #clock-cells = <0>;
-                       compatible = "allwinner,sun6i-a31-apb2-div-clk";
-                       reg = <0x01c20058 0x4>;
-                       clocks = <&apb2_mux>;
                        clock-output-names = "apb2";
                };
 
index 82a524ce28ad1502c5aee93accdb649aeede8821..e21ce5992d565c348ae3b798ad232cd8f6c16c6b 100644 (file)
                                "apb0_iis2", "apb0_keypad";
                };
 
-               apb1_mux: apb1_mux@01c20058 {
-                       #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-a10-apb1-mux-clk";
-                       reg = <0x01c20058 0x4>;
-                       clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
-                       clock-output-names = "apb1_mux";
-               };
-
-               apb1: apb1@01c20058 {
+               apb1: clk@01c20058 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-apb1-clk";
                        reg = <0x01c20058 0x4>;
-                       clocks = <&apb1_mux>;
+                       clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
                        clock-output-names = "apb1";
                };
 
index 6086adbf9d749adf1fb2040fb76675e84292bab9..0746cd1024d7a73b32bcbf6002954a4859d77ee5 100644 (file)
                                        "apb1_daudio0", "apb1_daudio1";
                };
 
-               apb2_mux: apb2_mux_clk@01c20058 {
+               apb2clk@01c20058 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-a10-apb1-mux-clk";
+                       compatible = "allwinner,sun4i-a10-apb1-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
-                       clock-output-names = "apb2_mux";
-               };
-
-               apb2: apb2_clk@01c20058 {
-                       #clock-cells = <0>;
-                       compatible = "allwinner,sun6i-a31-apb2-div-clk";
-                       reg = <0x01c20058 0x4>;
-                       clocks = <&apb2_mux>;
                        clock-output-names = "apb2";
                };
 
index ebdba87b96711a4a2a3970bcd824253ea9273327..fdbfadf00c84b492bb032f3ca47cf94f78f9c0d7 100644 (file)
@@ -86,11 +86,12 @@ config MACH_GPLUGD
 
 config MACH_MMP_DT
        bool "Support MMP (ARMv5) platforms from device tree"
-       select CPU_PXA168
-       select CPU_PXA910
        select USE_OF
        select PINCTRL
        select PINCTRL_SINGLE
+       select COMMON_CLK
+       select ARCH_HAS_RESET_CONTROLLER
+       select CPU_MOHAWK
        help
          Include support for Marvell MMP2 based platforms using
          the device tree. Needn't select any other machine while
@@ -99,10 +100,12 @@ config MACH_MMP_DT
 config MACH_MMP2_DT
        bool "Support MMP2 (ARMv7) platforms from device tree"
        depends on !CPU_MOHAWK
-       select CPU_MMP2
        select USE_OF
        select PINCTRL
        select PINCTRL_SINGLE
+       select COMMON_CLK
+       select ARCH_HAS_RESET_CONTROLLER
+       select CPU_PJ4
        help
          Include support for Marvell MMP2 based platforms using
          the device tree.
@@ -111,21 +114,18 @@ endmenu
 
 config CPU_PXA168
        bool
-       select COMMON_CLK
        select CPU_MOHAWK
        help
          Select code specific to PXA168
 
 config CPU_PXA910
        bool
-       select COMMON_CLK
        select CPU_MOHAWK
        help
          Select code specific to PXA910
 
 config CPU_MMP2
        bool
-       select COMMON_CLK
        select CPU_PJ4
        help
          Select code specific to MMP2. MMP2 is ARMv7 compatible.
index cca529ceecb758101f0120faa547c2790b004e80..b2296c9309b87659566992548a2a177888f1cf03 100644 (file)
 
 #include <linux/irqchip.h>
 #include <linux/of_platform.h>
+#include <linux/clk-provider.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
+#include <asm/hardware/cache-tauros2.h>
 
 #include "common.h"
 
 extern void __init mmp_dt_init_timer(void);
 
-static const struct of_dev_auxdata pxa168_auxdata_lookup[] __initconst = {
-       OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL),
-       OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL),
-       OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4026000, "pxa2xx-uart.2", NULL),
-       OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
-       OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4025000, "pxa2xx-i2c.1", NULL),
-       OF_DEV_AUXDATA("marvell,mmp-gpio", 0xd4019000, "mmp-gpio", NULL),
-       OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
-       {}
+static const char *pxa168_dt_board_compat[] __initdata = {
+       "mrvl,pxa168-aspenite",
+       NULL,
 };
 
-static const struct of_dev_auxdata pxa910_auxdata_lookup[] __initconst = {
-       OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL),
-       OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL),
-       OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4036000, "pxa2xx-uart.2", NULL),
-       OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
-       OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4037000, "pxa2xx-i2c.1", NULL),
-       OF_DEV_AUXDATA("marvell,mmp-gpio", 0xd4019000, "mmp-gpio", NULL),
-       OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
-       {}
+static const char *pxa910_dt_board_compat[] __initdata = {
+       "mrvl,pxa910-dkb",
+       NULL,
 };
 
-static void __init pxa168_dt_init(void)
-{
-       of_platform_populate(NULL, of_default_bus_match_table,
-                            pxa168_auxdata_lookup, NULL);
-}
-
-static void __init pxa910_dt_init(void)
+static void __init mmp_init_time(void)
 {
-       of_platform_populate(NULL, of_default_bus_match_table,
-                            pxa910_auxdata_lookup, NULL);
+#ifdef CONFIG_CACHE_TAUROS2
+       tauros2_init(0);
+#endif
+       mmp_dt_init_timer();
+       of_clk_init(NULL);
 }
 
-static const char *mmp_dt_board_compat[] __initdata = {
-       "mrvl,pxa168-aspenite",
-       "mrvl,pxa910-dkb",
-       NULL,
-};
-
 DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)")
        .map_io         = mmp_map_io,
-       .init_time      = mmp_dt_init_timer,
-       .init_machine   = pxa168_dt_init,
-       .dt_compat      = mmp_dt_board_compat,
+       .init_time      = mmp_init_time,
+       .dt_compat      = pxa168_dt_board_compat,
 MACHINE_END
 
 DT_MACHINE_START(PXA910_DT, "Marvell PXA910 (Device Tree Support)")
        .map_io         = mmp_map_io,
-       .init_time      = mmp_dt_init_timer,
-       .init_machine   = pxa910_dt_init,
-       .dt_compat      = mmp_dt_board_compat,
+       .init_time      = mmp_init_time,
+       .dt_compat      = pxa910_dt_board_compat,
 MACHINE_END
index 023cb453f157ff621110d6c17b6f0cc185b8d8ba..998c0f533abc842659b7f4bcb0d05e2a873a9b58 100644 (file)
 #include <linux/io.h>
 #include <linux/irqchip.h>
 #include <linux/of_platform.h>
+#include <linux/clk-provider.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
+#include <asm/hardware/cache-tauros2.h>
 
 #include "common.h"
 
 extern void __init mmp_dt_init_timer(void);
 
-static const struct of_dev_auxdata mmp2_auxdata_lookup[] __initconst = {
-       OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4030000, "pxa2xx-uart.0", NULL),
-       OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.1", NULL),
-       OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.2", NULL),
-       OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4016000, "pxa2xx-uart.3", NULL),
-       OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
-       OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4025000, "pxa2xx-i2c.1", NULL),
-       OF_DEV_AUXDATA("marvell,mmp-gpio", 0xd4019000, "mmp2-gpio", NULL),
-       OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
-       {}
-};
-
-static void __init mmp2_dt_init(void)
+static void __init mmp_init_time(void)
 {
-       of_platform_populate(NULL, of_default_bus_match_table,
-                            mmp2_auxdata_lookup, NULL);
+#ifdef CONFIG_CACHE_TAUROS2
+       tauros2_init(0);
+#endif
+       mmp_dt_init_timer();
+       of_clk_init(NULL);
 }
 
 static const char *mmp2_dt_board_compat[] __initdata = {
@@ -44,7 +37,6 @@ static const char *mmp2_dt_board_compat[] __initdata = {
 
 DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)")
        .map_io         = mmp_map_io,
-       .init_time      = mmp_dt_init_timer,
-       .init_machine   = mmp2_dt_init,
+       .init_time      = mmp_init_time,
        .dt_compat      = mmp2_dt_board_compat,
 MACHINE_END
index 5c5ebb4db5f73031b5ba25a960e8efee5ec885fb..644ff3231bb8d1975c051f248e1d78c4007741cb 100644 (file)
@@ -111,6 +111,7 @@ static struct clk dpll3_ck;
 
 static const char *dpll3_ck_parent_names[] = {
        "sys_ck",
+       "sys_ck",
 };
 
 static const struct clk_ops dpll3_ck_ops = {
@@ -733,6 +734,10 @@ static const char *corex2_fck_parent_names[] = {
 DEFINE_STRUCT_CLK_HW_OMAP(corex2_fck, NULL);
 DEFINE_STRUCT_CLK(corex2_fck, corex2_fck_parent_names, core_ck_ops);
 
+static const char *cpefuse_fck_parent_names[] = {
+       "sys_ck",
+};
+
 static struct clk cpefuse_fck;
 
 static struct clk_hw_omap cpefuse_fck_hw = {
@@ -744,7 +749,7 @@ static struct clk_hw_omap cpefuse_fck_hw = {
        .clkdm_name     = "core_l4_clkdm",
 };
 
-DEFINE_STRUCT_CLK(cpefuse_fck, dpll3_ck_parent_names, aes2_ick_ops);
+DEFINE_STRUCT_CLK(cpefuse_fck, cpefuse_fck_parent_names, aes2_ick_ops);
 
 static struct clk csi2_96m_fck;
 
@@ -775,7 +780,7 @@ static struct clk_hw_omap d2d_26m_fck_hw = {
        .clkdm_name     = "d2d_clkdm",
 };
 
-DEFINE_STRUCT_CLK(d2d_26m_fck, dpll3_ck_parent_names, aes2_ick_ops);
+DEFINE_STRUCT_CLK(d2d_26m_fck, cpefuse_fck_parent_names, aes2_ick_ops);
 
 static struct clk des1_ick;
 
@@ -1046,7 +1051,7 @@ static struct clk_hw_omap dss2_alwon_fck_hw = {
        .clkdm_name     = "dss_clkdm",
 };
 
-DEFINE_STRUCT_CLK(dss2_alwon_fck, dpll3_ck_parent_names, aes2_ick_ops);
+DEFINE_STRUCT_CLK(dss2_alwon_fck, cpefuse_fck_parent_names, aes2_ick_ops);
 
 static struct clk dss_96m_fck;
 
@@ -1368,7 +1373,7 @@ DEFINE_STRUCT_CLK(gpio1_dbck, gpio1_dbck_parent_names, aes2_ick_ops);
 static struct clk wkup_l4_ick;
 
 DEFINE_STRUCT_CLK_HW_OMAP(wkup_l4_ick, "wkup_clkdm");
-DEFINE_STRUCT_CLK(wkup_l4_ick, dpll3_ck_parent_names, core_l4_ick_ops);
+DEFINE_STRUCT_CLK(wkup_l4_ick, cpefuse_fck_parent_names, core_l4_ick_ops);
 
 static struct clk gpio1_ick;
 
@@ -1862,7 +1867,7 @@ static struct clk_hw_omap hecc_ck_hw = {
        .clkdm_name     = "core_l3_clkdm",
 };
 
-DEFINE_STRUCT_CLK(hecc_ck, dpll3_ck_parent_names, aes2_ick_ops);
+DEFINE_STRUCT_CLK(hecc_ck, cpefuse_fck_parent_names, aes2_ick_ops);
 
 static struct clk hsotgusb_fck_am35xx;
 
@@ -1875,7 +1880,7 @@ static struct clk_hw_omap hsotgusb_fck_am35xx_hw = {
        .clkdm_name     = "core_l3_clkdm",
 };
 
-DEFINE_STRUCT_CLK(hsotgusb_fck_am35xx, dpll3_ck_parent_names, aes2_ick_ops);
+DEFINE_STRUCT_CLK(hsotgusb_fck_am35xx, cpefuse_fck_parent_names, aes2_ick_ops);
 
 static struct clk hsotgusb_ick_3430es1;
 
@@ -2411,7 +2416,7 @@ static struct clk_hw_omap modem_fck_hw = {
        .clkdm_name     = "d2d_clkdm",
 };
 
-DEFINE_STRUCT_CLK(modem_fck, dpll3_ck_parent_names, aes2_ick_ops);
+DEFINE_STRUCT_CLK(modem_fck, cpefuse_fck_parent_names, aes2_ick_ops);
 
 static struct clk mspro_fck;
 
@@ -2710,7 +2715,7 @@ static struct clk_hw_omap sr1_fck_hw = {
        .clkdm_name     = "wkup_clkdm",
 };
 
-DEFINE_STRUCT_CLK(sr1_fck, dpll3_ck_parent_names, aes2_ick_ops);
+DEFINE_STRUCT_CLK(sr1_fck, cpefuse_fck_parent_names, aes2_ick_ops);
 
 static struct clk sr2_fck;
 
@@ -2724,7 +2729,7 @@ static struct clk_hw_omap sr2_fck_hw = {
        .clkdm_name     = "wkup_clkdm",
 };
 
-DEFINE_STRUCT_CLK(sr2_fck, dpll3_ck_parent_names, aes2_ick_ops);
+DEFINE_STRUCT_CLK(sr2_fck, cpefuse_fck_parent_names, aes2_ick_ops);
 
 static struct clk sr_l4_ick;
 
index 20e120d071dd5853b228106d1164c0e251b2cf45..c2da2a0fe5ad64df80d6290f45658c697cfd4c96 100644 (file)
@@ -474,7 +474,7 @@ void omap3_noncore_dpll_disable(struct clk_hw *hw)
  */
 long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate,
                                       unsigned long *best_parent_rate,
-                                      struct clk **best_parent_clk)
+                                      struct clk_hw **best_parent_clk)
 {
        struct clk_hw_omap *clk = to_clk_hw_omap(hw);
        struct dpll_data *dd;
@@ -488,10 +488,10 @@ long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate,
 
        if (__clk_get_rate(dd->clk_bypass) == rate &&
            (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
-               *best_parent_clk = dd->clk_bypass;
+               *best_parent_clk = __clk_get_hw(dd->clk_bypass);
        } else {
                rate = omap2_dpll_round_rate(hw, rate, best_parent_rate);
-               *best_parent_clk = dd->clk_ref;
+               *best_parent_clk = __clk_get_hw(dd->clk_ref);
        }
 
        *best_parent_rate = rate;
index 535822fcf4bbbd1e57a1211d122449d0a8a5807d..0e58e5a85d5309abf55d74a65d4ef47b28910c0f 100644 (file)
@@ -223,7 +223,7 @@ out:
  */
 long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate,
                                        unsigned long *best_parent_rate,
-                                       struct clk **best_parent_clk)
+                                       struct clk_hw **best_parent_clk)
 {
        struct clk_hw_omap *clk = to_clk_hw_omap(hw);
        struct dpll_data *dd;
@@ -237,11 +237,11 @@ long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate,
 
        if (__clk_get_rate(dd->clk_bypass) == rate &&
            (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
-               *best_parent_clk = dd->clk_bypass;
+               *best_parent_clk = __clk_get_hw(dd->clk_bypass);
        } else {
                rate = omap4_dpll_regm4xen_round_rate(hw, rate,
                                                      best_parent_rate);
-               *best_parent_clk = dd->clk_ref;
+               *best_parent_clk = __clk_get_hw(dd->clk_ref);
        }
 
        *best_parent_rate = rate;
index 203e4403c366869ed1acbd99cbf4e82c92b83942..48a9dfc55b51aa4a3819bae6c686b0cd5f38a7f0 100644 (file)
@@ -374,7 +374,7 @@ static long alchemy_calc_div(unsigned long rate, unsigned long prate,
 
 static long alchemy_clk_fgcs_detr(struct clk_hw *hw, unsigned long rate,
                                        unsigned long *best_parent_rate,
-                                       struct clk **best_parent_clk,
+                                       struct clk_hw **best_parent_clk,
                                        int scale, int maxdiv)
 {
        struct clk *pc, *bpc, *free;
@@ -453,7 +453,7 @@ static long alchemy_clk_fgcs_detr(struct clk_hw *hw, unsigned long rate,
        }
 
        *best_parent_rate = bpr;
-       *best_parent_clk = bpc;
+       *best_parent_clk = __clk_get_hw(bpc);
        return br;
 }
 
@@ -547,7 +547,7 @@ static unsigned long alchemy_clk_fgv1_recalc(struct clk_hw *hw,
 
 static long alchemy_clk_fgv1_detr(struct clk_hw *hw, unsigned long rate,
                                        unsigned long *best_parent_rate,
-                                       struct clk **best_parent_clk)
+                                       struct clk_hw **best_parent_clk)
 {
        return alchemy_clk_fgcs_detr(hw, rate, best_parent_rate,
                                     best_parent_clk, 2, 512);
@@ -679,7 +679,7 @@ static unsigned long alchemy_clk_fgv2_recalc(struct clk_hw *hw,
 
 static long alchemy_clk_fgv2_detr(struct clk_hw *hw, unsigned long rate,
                                        unsigned long *best_parent_rate,
-                                       struct clk **best_parent_clk)
+                                       struct clk_hw **best_parent_clk)
 {
        struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
        int scale, maxdiv;
@@ -898,7 +898,7 @@ static int alchemy_clk_csrc_setr(struct clk_hw *hw, unsigned long rate,
 
 static long alchemy_clk_csrc_detr(struct clk_hw *hw, unsigned long rate,
                                        unsigned long *best_parent_rate,
-                                       struct clk **best_parent_clk)
+                                       struct clk_hw **best_parent_clk)
 {
        struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
        int scale = c->dt[2] == 3 ? 1 : 2; /* au1300 check */
index 62e2509f9df16d52352da1d4aaa13b06d65b4824..bbdb1b985c9146a5e82013fd8d8ab20ea3ebc5fc 100644 (file)
@@ -57,7 +57,7 @@ static unsigned long clk_programmable_recalc_rate(struct clk_hw *hw,
 static long clk_programmable_determine_rate(struct clk_hw *hw,
                                            unsigned long rate,
                                            unsigned long *best_parent_rate,
-                                           struct clk **best_parent_clk)
+                                           struct clk_hw **best_parent_hw)
 {
        struct clk *parent = NULL;
        long best_rate = -EINVAL;
@@ -84,7 +84,7 @@ static long clk_programmable_determine_rate(struct clk_hw *hw,
                if (best_rate < 0 || (rate - tmp_rate) < (rate - best_rate)) {
                        best_rate = tmp_rate;
                        *best_parent_rate = parent_rate;
-                       *best_parent_clk = parent;
+                       *best_parent_hw = __clk_get_hw(parent);
                }
 
                if (!best_rate)
index 95af2e665dd33cf769da657fc918949ef04a36f3..1c06f6f3a8c59959b90e90f554c048e1535a1893 100644 (file)
@@ -1032,7 +1032,7 @@ static long kona_peri_clk_round_rate(struct clk_hw *hw, unsigned long rate,
 }
 
 static long kona_peri_clk_determine_rate(struct clk_hw *hw, unsigned long rate,
-               unsigned long *best_parent_rate, struct clk **best_parent)
+               unsigned long *best_parent_rate, struct clk_hw **best_parent)
 {
        struct kona_clk *bcm_clk = to_kona_clk(hw);
        struct clk *clk = hw->clk;
@@ -1075,7 +1075,7 @@ static long kona_peri_clk_determine_rate(struct clk_hw *hw, unsigned long rate,
                if (delta < best_delta) {
                        best_delta = delta;
                        best_rate = other_rate;
-                       *best_parent = parent;
+                       *best_parent = __clk_get_hw(parent);
                        *best_parent_rate = parent_rate;
                }
        }
index b9355daf8065fcbb6de7db2ca9cbb3593134c892..4386697236a78dc23aea66d0c4792873d558f71e 100644 (file)
@@ -57,7 +57,7 @@ static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
 
 static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate,
                                        unsigned long *best_parent_rate,
-                                       struct clk **best_parent_p)
+                                       struct clk_hw **best_parent_p)
 {
        struct clk_composite *composite = to_clk_composite(hw);
        const struct clk_ops *rate_ops = composite->rate_ops;
@@ -80,8 +80,9 @@ static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate,
                *best_parent_p = NULL;
 
                if (__clk_get_flags(hw->clk) & CLK_SET_RATE_NO_REPARENT) {
-                       *best_parent_p = clk_get_parent(mux_hw->clk);
-                       *best_parent_rate = __clk_get_rate(*best_parent_p);
+                       parent = clk_get_parent(mux_hw->clk);
+                       *best_parent_p = __clk_get_hw(parent);
+                       *best_parent_rate = __clk_get_rate(parent);
 
                        return rate_ops->round_rate(rate_hw, rate,
                                                    best_parent_rate);
@@ -103,7 +104,7 @@ static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate,
 
                        if (!rate_diff || !*best_parent_p
                                       || best_rate_diff > rate_diff) {
-                               *best_parent_p = parent;
+                               *best_parent_p = __clk_get_hw(parent);
                                *best_parent_rate = parent_rate;
                                best_rate_diff = rate_diff;
                                best_rate = tmp_rate;
index 4f96ff3ba728321563cbdc6b728f9a25c65d74c6..6e1ecf94bf58daa279cb47e42065da9a9db3c581 100644 (file)
@@ -77,7 +77,7 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
 
        else {
                if (mux->flags & CLK_MUX_INDEX_BIT)
-                       index = (1 << ffs(index));
+                       index = 1 << index;
 
                if (mux->flags & CLK_MUX_INDEX_ONE)
                        index++;
index 87a41038237d64634a2372231ebf08654ea7c1a5..bfa1e64e267d36a9286d5701069305133b5a092c 100644 (file)
@@ -218,7 +218,7 @@ static int s2mps11_clk_probe(struct platform_device *pdev)
        default:
                dev_err(&pdev->dev, "Invalid device type\n");
                return -EINVAL;
-       };
+       }
 
        /* Store clocks of_node in first element of s2mps11_clks array */
        s2mps11_clks->clk_np = s2mps11_clk_parse_dt(pdev, clks_init);
index 4896ae9e23da0c23ed52872cf1992f95609e1b59..f4963b7d4e17d41b6a6553854c5250a7e90bfdef 100644 (file)
@@ -240,7 +240,6 @@ static const struct file_operations clk_dump_fops = {
        .release        = single_release,
 };
 
-/* caller must hold prepare_lock */
 static int clk_debug_create_one(struct clk *clk, struct dentry *pdentry)
 {
        struct dentry *d;
@@ -354,13 +353,13 @@ out:
        mutex_unlock(&clk_debug_lock);
 }
 
-struct dentry *clk_debugfs_add_file(struct clk *clk, char *name, umode_t mode,
+struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode,
                                void *data, const struct file_operations *fops)
 {
        struct dentry *d = NULL;
 
-       if (clk->dentry)
-               d = debugfs_create_file(name, mode, clk->dentry, data, fops);
+       if (hw->clk->dentry)
+               d = debugfs_create_file(name, mode, hw->clk->dentry, data, fops);
 
        return d;
 }
@@ -574,11 +573,6 @@ unsigned int __clk_get_enable_count(struct clk *clk)
        return !clk ? 0 : clk->enable_count;
 }
 
-unsigned int __clk_get_prepare_count(struct clk *clk)
-{
-       return !clk ? 0 : clk->prepare_count;
-}
-
 unsigned long __clk_get_rate(struct clk *clk)
 {
        unsigned long ret;
@@ -601,7 +595,7 @@ out:
 }
 EXPORT_SYMBOL_GPL(__clk_get_rate);
 
-unsigned long __clk_get_accuracy(struct clk *clk)
+static unsigned long __clk_get_accuracy(struct clk *clk)
 {
        if (!clk)
                return 0;
@@ -707,7 +701,7 @@ struct clk *__clk_lookup(const char *name)
  */
 long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
                              unsigned long *best_parent_rate,
-                             struct clk **best_parent_p)
+                             struct clk_hw **best_parent_p)
 {
        struct clk *clk = hw->clk, *parent, *best_parent = NULL;
        int i, num_parents;
@@ -743,7 +737,7 @@ long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
 
 out:
        if (best_parent)
-               *best_parent_p = best_parent;
+               *best_parent_p = best_parent->hw;
        *best_parent_rate = best;
 
        return best;
@@ -951,6 +945,7 @@ unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
 {
        unsigned long parent_rate = 0;
        struct clk *parent;
+       struct clk_hw *parent_hw;
 
        if (!clk)
                return 0;
@@ -959,10 +954,11 @@ unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
        if (parent)
                parent_rate = parent->rate;
 
-       if (clk->ops->determine_rate)
+       if (clk->ops->determine_rate) {
+               parent_hw = parent ? parent->hw : NULL;
                return clk->ops->determine_rate(clk->hw, rate, &parent_rate,
-                                               &parent);
-       else if (clk->ops->round_rate)
+                                               &parent_hw);
+       else if (clk->ops->round_rate)
                return clk->ops->round_rate(clk->hw, rate, &parent_rate);
        else if (clk->flags & CLK_SET_RATE_PARENT)
                return __clk_round_rate(clk->parent, rate);
@@ -1350,6 +1346,7 @@ static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
 {
        struct clk *top = clk;
        struct clk *old_parent, *parent;
+       struct clk_hw *parent_hw;
        unsigned long best_parent_rate = 0;
        unsigned long new_rate;
        int p_index = 0;
@@ -1365,9 +1362,11 @@ static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
 
        /* find the closest rate and parent clk/rate */
        if (clk->ops->determine_rate) {
+               parent_hw = parent ? parent->hw : NULL;
                new_rate = clk->ops->determine_rate(clk->hw, rate,
                                                    &best_parent_rate,
-                                                   &parent);
+                                                   &parent_hw);
+               parent = parent_hw->clk;
        } else if (clk->ops->round_rate) {
                new_rate = clk->ops->round_rate(clk->hw, rate,
                                                &best_parent_rate);
@@ -1614,7 +1613,7 @@ static struct clk *__clk_init_parent(struct clk *clk)
 
        if (clk->num_parents == 1) {
                if (IS_ERR_OR_NULL(clk->parent))
-                       ret = clk->parent = __clk_lookup(clk->parent_names[0]);
+                       clk->parent = __clk_lookup(clk->parent_names[0]);
                ret = clk->parent;
                goto out;
        }
@@ -1944,7 +1943,6 @@ int __clk_init(struct device *dev, struct clk *clk)
        else
                clk->rate = 0;
 
-       clk_debug_register(clk);
        /*
         * walk the list of orphan clocks and reparent any that are children of
         * this clock
@@ -1979,6 +1977,9 @@ int __clk_init(struct device *dev, struct clk *clk)
 out:
        clk_prepare_unlock();
 
+       if (!ret)
+               clk_debug_register(clk);
+
        return ret;
 }
 
@@ -2273,14 +2274,17 @@ int __clk_get(struct clk *clk)
 
 void __clk_put(struct clk *clk)
 {
+       struct module *owner;
+
        if (!clk || WARN_ON_ONCE(IS_ERR(clk)))
                return;
 
        clk_prepare_lock();
+       owner = clk->owner;
        kref_put(&clk->ref, __clk_release);
        clk_prepare_unlock();
 
-       module_put(clk->owner);
+       module_put(owner);
 }
 
 /***        clk rate change notifiers        ***/
index 339945d2503b33798ca4e98b51e140f2b8f658ae..007144f81f50b63301f211103dd200f7f21a4ec4 100644 (file)
 #include "clk.h"
 
 /* clock parent list */
-static const char *timer0_mux_p[] __initdata = { "osc32k", "timerclk01", };
-static const char *timer1_mux_p[] __initdata = { "osc32k", "timerclk01", };
-static const char *timer2_mux_p[] __initdata = { "osc32k", "timerclk23", };
-static const char *timer3_mux_p[] __initdata = { "osc32k", "timerclk23", };
-static const char *timer4_mux_p[] __initdata = { "osc32k", "timerclk45", };
-static const char *timer5_mux_p[] __initdata = { "osc32k", "timerclk45", };
-static const char *timer6_mux_p[] __initdata = { "osc32k", "timerclk67", };
-static const char *timer7_mux_p[] __initdata = { "osc32k", "timerclk67", };
-static const char *timer8_mux_p[] __initdata = { "osc32k", "timerclk89", };
-static const char *timer9_mux_p[] __initdata = { "osc32k", "timerclk89", };
-static const char *uart0_mux_p[] __initdata = { "osc26m", "pclk", };
-static const char *uart1_mux_p[] __initdata = { "osc26m", "pclk", };
-static const char *uart2_mux_p[] __initdata = { "osc26m", "pclk", };
-static const char *uart3_mux_p[] __initdata = { "osc26m", "pclk", };
-static const char *uart4_mux_p[] __initdata = { "osc26m", "pclk", };
-static const char *spi0_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", };
-static const char *spi1_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", };
-static const char *spi2_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", };
+static const char *timer0_mux_p[] __initconst = { "osc32k", "timerclk01", };
+static const char *timer1_mux_p[] __initconst = { "osc32k", "timerclk01", };
+static const char *timer2_mux_p[] __initconst = { "osc32k", "timerclk23", };
+static const char *timer3_mux_p[] __initconst = { "osc32k", "timerclk23", };
+static const char *timer4_mux_p[] __initconst = { "osc32k", "timerclk45", };
+static const char *timer5_mux_p[] __initconst = { "osc32k", "timerclk45", };
+static const char *timer6_mux_p[] __initconst = { "osc32k", "timerclk67", };
+static const char *timer7_mux_p[] __initconst = { "osc32k", "timerclk67", };
+static const char *timer8_mux_p[] __initconst = { "osc32k", "timerclk89", };
+static const char *timer9_mux_p[] __initconst = { "osc32k", "timerclk89", };
+static const char *uart0_mux_p[] __initconst = { "osc26m", "pclk", };
+static const char *uart1_mux_p[] __initconst = { "osc26m", "pclk", };
+static const char *uart2_mux_p[] __initconst = { "osc26m", "pclk", };
+static const char *uart3_mux_p[] __initconst = { "osc26m", "pclk", };
+static const char *uart4_mux_p[] __initconst = { "osc26m", "pclk", };
+static const char *spi0_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", };
+static const char *spi1_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", };
+static const char *spi2_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", };
 /* share axi parent */
-static const char *saxi_mux_p[] __initdata = { "armpll3", "armpll2", };
-static const char *pwm0_mux_p[] __initdata = { "osc32k", "osc26m", };
-static const char *pwm1_mux_p[] __initdata = { "osc32k", "osc26m", };
-static const char *sd_mux_p[] __initdata = { "armpll2", "armpll3", };
-static const char *mmc1_mux_p[] __initdata = { "armpll2", "armpll3", };
-static const char *mmc1_mux2_p[] __initdata = { "osc26m", "mmc1_div", };
-static const char *g2d_mux_p[] __initdata = { "armpll2", "armpll3", };
-static const char *venc_mux_p[] __initdata = { "armpll2", "armpll3", };
-static const char *vdec_mux_p[] __initdata = { "armpll2", "armpll3", };
-static const char *vpp_mux_p[] __initdata = { "armpll2", "armpll3", };
-static const char *edc0_mux_p[] __initdata = { "armpll2", "armpll3", };
-static const char *ldi0_mux_p[] __initdata = { "armpll2", "armpll4",
+static const char *saxi_mux_p[] __initconst = { "armpll3", "armpll2", };
+static const char *pwm0_mux_p[] __initconst = { "osc32k", "osc26m", };
+static const char *pwm1_mux_p[] __initconst = { "osc32k", "osc26m", };
+static const char *sd_mux_p[] __initconst = { "armpll2", "armpll3", };
+static const char *mmc1_mux_p[] __initconst = { "armpll2", "armpll3", };
+static const char *mmc1_mux2_p[] __initconst = { "osc26m", "mmc1_div", };
+static const char *g2d_mux_p[] __initconst = { "armpll2", "armpll3", };
+static const char *venc_mux_p[] __initconst = { "armpll2", "armpll3", };
+static const char *vdec_mux_p[] __initconst = { "armpll2", "armpll3", };
+static const char *vpp_mux_p[] __initconst = { "armpll2", "armpll3", };
+static const char *edc0_mux_p[] __initconst = { "armpll2", "armpll3", };
+static const char *ldi0_mux_p[] __initconst = { "armpll2", "armpll4",
                                             "armpll3", "armpll5", };
-static const char *edc1_mux_p[] __initdata = { "armpll2", "armpll3", };
-static const char *ldi1_mux_p[] __initdata = { "armpll2", "armpll4",
+static const char *edc1_mux_p[] __initconst = { "armpll2", "armpll3", };
+static const char *ldi1_mux_p[] __initconst = { "armpll2", "armpll4",
                                             "armpll3", "armpll5", };
-static const char *rclk_hsic_p[] __initdata = { "armpll3", "armpll2", };
-static const char *mmc2_mux_p[] __initdata = { "armpll2", "armpll3", };
-static const char *mmc3_mux_p[] __initdata = { "armpll2", "armpll3", };
+static const char *rclk_hsic_p[] __initconst = { "armpll3", "armpll2", };
+static const char *mmc2_mux_p[] __initconst = { "armpll2", "armpll3", };
+static const char *mmc3_mux_p[] __initconst = { "armpll2", "armpll3", };
 
 
 /* fixed rate clocks */
@@ -296,7 +296,7 @@ static unsigned long mmc_clk_recalc_rate(struct clk_hw *hw,
 
 static long mmc_clk_determine_rate(struct clk_hw *hw, unsigned long rate,
                              unsigned long *best_parent_rate,
-                             struct clk **best_parent_p)
+                             struct clk_hw **best_parent_p)
 {
        struct clk_mmc *mclk = to_mmc(hw);
        unsigned long best = 0;
index 392d78044ce3748903ad1614ffc4589a7cdb168c..3caaf7cc169c684559973f105317dea76bbd1d54 100644 (file)
@@ -2,7 +2,12 @@
 # Makefile for mmp specific clk
 #
 
-obj-y += clk-apbc.o clk-apmu.o clk-frac.o
+obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o clk-gate.o clk.o
+
+obj-$(CONFIG_RESET_CONTROLLER) += reset.o
+
+obj-$(CONFIG_MACH_MMP_DT) += clk-of-pxa168.o clk-of-pxa910.o
+obj-$(CONFIG_MACH_MMP2_DT) += clk-of-mmp2.o
 
 obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
 obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
index 23a56f561812decc149624fe72b803a7bbb726ab..584a9927993b41f73df73f40ec598f4e7d45ca1d 100644 (file)
  * numerator/denominator = Fin / (Fout * factor)
  */
 
-#define to_clk_factor(hw) container_of(hw, struct clk_factor, hw)
-struct clk_factor {
-       struct clk_hw           hw;
-       void __iomem            *base;
-       struct clk_factor_masks *masks;
-       struct clk_factor_tbl   *ftbl;
-       unsigned int            ftbl_cnt;
-};
+#define to_clk_factor(hw) container_of(hw, struct mmp_clk_factor, hw)
 
 static long clk_factor_round_rate(struct clk_hw *hw, unsigned long drate,
                unsigned long *prate)
 {
-       struct clk_factor *factor = to_clk_factor(hw);
+       struct mmp_clk_factor *factor = to_clk_factor(hw);
        unsigned long rate = 0, prev_rate;
        int i;
 
@@ -58,8 +51,8 @@ static long clk_factor_round_rate(struct clk_hw *hw, unsigned long drate,
 static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
                unsigned long parent_rate)
 {
-       struct clk_factor *factor = to_clk_factor(hw);
-       struct clk_factor_masks *masks = factor->masks;
+       struct mmp_clk_factor *factor = to_clk_factor(hw);
+       struct mmp_clk_factor_masks *masks = factor->masks;
        unsigned int val, num, den;
 
        val = readl_relaxed(factor->base);
@@ -81,11 +74,12 @@ static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
 static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate,
                                unsigned long prate)
 {
-       struct clk_factor *factor = to_clk_factor(hw);
-       struct clk_factor_masks *masks = factor->masks;
+       struct mmp_clk_factor *factor = to_clk_factor(hw);
+       struct mmp_clk_factor_masks *masks = factor->masks;
        int i;
        unsigned long val;
        unsigned long prev_rate, rate = 0;
+       unsigned long flags = 0;
 
        for (i = 0; i < factor->ftbl_cnt; i++) {
                prev_rate = rate;
@@ -97,6 +91,9 @@ static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate,
        if (i > 0)
                i--;
 
+       if (factor->lock)
+               spin_lock_irqsave(factor->lock, flags);
+
        val = readl_relaxed(factor->base);
 
        val &= ~(masks->num_mask << masks->num_shift);
@@ -107,21 +104,65 @@ static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate,
 
        writel_relaxed(val, factor->base);
 
+       if (factor->lock)
+               spin_unlock_irqrestore(factor->lock, flags);
+
        return 0;
 }
 
+static void clk_factor_init(struct clk_hw *hw)
+{
+       struct mmp_clk_factor *factor = to_clk_factor(hw);
+       struct mmp_clk_factor_masks *masks = factor->masks;
+       u32 val, num, den;
+       int i;
+       unsigned long flags = 0;
+
+       if (factor->lock)
+               spin_lock_irqsave(factor->lock, flags);
+
+       val = readl(factor->base);
+
+       /* calculate numerator */
+       num = (val >> masks->num_shift) & masks->num_mask;
+
+       /* calculate denominator */
+       den = (val >> masks->den_shift) & masks->den_mask;
+
+       for (i = 0; i < factor->ftbl_cnt; i++)
+               if (den == factor->ftbl[i].den && num == factor->ftbl[i].num)
+                       break;
+
+       if (i >= factor->ftbl_cnt) {
+               val &= ~(masks->num_mask << masks->num_shift);
+               val |= (factor->ftbl[0].num & masks->num_mask) <<
+                       masks->num_shift;
+
+               val &= ~(masks->den_mask << masks->den_shift);
+               val |= (factor->ftbl[0].den & masks->den_mask) <<
+                       masks->den_shift;
+
+               writel(val, factor->base);
+       }
+
+       if (factor->lock)
+               spin_unlock_irqrestore(factor->lock, flags);
+}
+
 static struct clk_ops clk_factor_ops = {
        .recalc_rate = clk_factor_recalc_rate,
        .round_rate = clk_factor_round_rate,
        .set_rate = clk_factor_set_rate,
+       .init = clk_factor_init,
 };
 
 struct clk *mmp_clk_register_factor(const char *name, const char *parent_name,
                unsigned long flags, void __iomem *base,
-               struct clk_factor_masks *masks, struct clk_factor_tbl *ftbl,
-               unsigned int ftbl_cnt)
+               struct mmp_clk_factor_masks *masks,
+               struct mmp_clk_factor_tbl *ftbl,
+               unsigned int ftbl_cnt, spinlock_t *lock)
 {
-       struct clk_factor *factor;
+       struct mmp_clk_factor *factor;
        struct clk_init_data init;
        struct clk *clk;
 
@@ -142,6 +183,7 @@ struct clk *mmp_clk_register_factor(const char *name, const char *parent_name,
        factor->ftbl = ftbl;
        factor->ftbl_cnt = ftbl_cnt;
        factor->hw.init = &init;
+       factor->lock = lock;
 
        init.name = name;
        init.ops = &clk_factor_ops;
diff --git a/drivers/clk/mmp/clk-gate.c b/drivers/clk/mmp/clk-gate.c
new file mode 100644 (file)
index 0000000..adbd9d6
--- /dev/null
@@ -0,0 +1,133 @@
+/*
+ * mmp gate clock operation source file
+ *
+ * Copyright (C) 2014 Marvell
+ * Chao Xie <chao.xie@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+
+#include "clk.h"
+
+/*
+ * Some clocks will have mutiple bits to enable the clocks, and
+ * the bits to disable the clock is not same as enabling bits.
+ */
+
+#define to_clk_mmp_gate(hw)    container_of(hw, struct mmp_clk_gate, hw)
+
+static int mmp_clk_gate_enable(struct clk_hw *hw)
+{
+       struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
+       struct clk *clk = hw->clk;
+       unsigned long flags = 0;
+       unsigned long rate;
+       u32 tmp;
+
+       if (gate->lock)
+               spin_lock_irqsave(gate->lock, flags);
+
+       tmp = readl(gate->reg);
+       tmp &= ~gate->mask;
+       tmp |= gate->val_enable;
+       writel(tmp, gate->reg);
+
+       if (gate->lock)
+               spin_unlock_irqrestore(gate->lock, flags);
+
+       if (gate->flags & MMP_CLK_GATE_NEED_DELAY) {
+               rate = __clk_get_rate(clk);
+               /* Need delay 2 cycles. */
+               udelay(2000000/rate);
+       }
+
+       return 0;
+}
+
+static void mmp_clk_gate_disable(struct clk_hw *hw)
+{
+       struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
+       unsigned long flags = 0;
+       u32 tmp;
+
+       if (gate->lock)
+               spin_lock_irqsave(gate->lock, flags);
+
+       tmp = readl(gate->reg);
+       tmp &= ~gate->mask;
+       tmp |= gate->val_disable;
+       writel(tmp, gate->reg);
+
+       if (gate->lock)
+               spin_unlock_irqrestore(gate->lock, flags);
+}
+
+static int mmp_clk_gate_is_enabled(struct clk_hw *hw)
+{
+       struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
+       unsigned long flags = 0;
+       u32 tmp;
+
+       if (gate->lock)
+               spin_lock_irqsave(gate->lock, flags);
+
+       tmp = readl(gate->reg);
+
+       if (gate->lock)
+               spin_unlock_irqrestore(gate->lock, flags);
+
+       return (tmp & gate->mask) == gate->val_enable;
+}
+
+const struct clk_ops mmp_clk_gate_ops = {
+       .enable = mmp_clk_gate_enable,
+       .disable = mmp_clk_gate_disable,
+       .is_enabled = mmp_clk_gate_is_enabled,
+};
+
+struct clk *mmp_clk_register_gate(struct device *dev, const char *name,
+               const char *parent_name, unsigned long flags,
+               void __iomem *reg, u32 mask, u32 val_enable, u32 val_disable,
+               unsigned int gate_flags, spinlock_t *lock)
+{
+       struct mmp_clk_gate *gate;
+       struct clk *clk;
+       struct clk_init_data init;
+
+       /* allocate the gate */
+       gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+       if (!gate) {
+               pr_err("%s:%s could not allocate gate clk\n", __func__, name);
+               return ERR_PTR(-ENOMEM);
+       }
+
+       init.name = name;
+       init.ops = &mmp_clk_gate_ops;
+       init.flags = flags | CLK_IS_BASIC;
+       init.parent_names = (parent_name ? &parent_name : NULL);
+       init.num_parents = (parent_name ? 1 : 0);
+
+       /* struct clk_gate assignments */
+       gate->reg = reg;
+       gate->mask = mask;
+       gate->val_enable = val_enable;
+       gate->val_disable = val_disable;
+       gate->flags = gate_flags;
+       gate->lock = lock;
+       gate->hw.init = &init;
+
+       clk = clk_register(dev, &gate->hw);
+
+       if (IS_ERR(clk))
+               kfree(gate);
+
+       return clk;
+}
diff --git a/drivers/clk/mmp/clk-mix.c b/drivers/clk/mmp/clk-mix.c
new file mode 100644 (file)
index 0000000..48fa53c
--- /dev/null
@@ -0,0 +1,513 @@
+/*
+ * mmp mix(div and mux) clock operation source file
+ *
+ * Copyright (C) 2014 Marvell
+ * Chao Xie <chao.xie@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+
+#include "clk.h"
+
+/*
+ * The mix clock is a clock combined mux and div type clock.
+ * Because the div field and mux field need to be set at same
+ * time, we can not divide it into 2 types of clock
+ */
+
+#define to_clk_mix(hw) container_of(hw, struct mmp_clk_mix, hw)
+
+static unsigned int _get_maxdiv(struct mmp_clk_mix *mix)
+{
+       unsigned int div_mask = (1 << mix->reg_info.width_div) - 1;
+       unsigned int maxdiv = 0;
+       struct clk_div_table *clkt;
+
+       if (mix->div_flags & CLK_DIVIDER_ONE_BASED)
+               return div_mask;
+       if (mix->div_flags & CLK_DIVIDER_POWER_OF_TWO)
+               return 1 << div_mask;
+       if (mix->div_table) {
+               for (clkt = mix->div_table; clkt->div; clkt++)
+                       if (clkt->div > maxdiv)
+                               maxdiv = clkt->div;
+               return maxdiv;
+       }
+       return div_mask + 1;
+}
+
+static unsigned int _get_div(struct mmp_clk_mix *mix, unsigned int val)
+{
+       struct clk_div_table *clkt;
+
+       if (mix->div_flags & CLK_DIVIDER_ONE_BASED)
+               return val;
+       if (mix->div_flags & CLK_DIVIDER_POWER_OF_TWO)
+               return 1 << val;
+       if (mix->div_table) {
+               for (clkt = mix->div_table; clkt->div; clkt++)
+                       if (clkt->val == val)
+                               return clkt->div;
+               if (clkt->div == 0)
+                       return 0;
+       }
+       return val + 1;
+}
+
+static unsigned int _get_mux(struct mmp_clk_mix *mix, unsigned int val)
+{
+       int num_parents = __clk_get_num_parents(mix->hw.clk);
+       int i;
+
+       if (mix->mux_flags & CLK_MUX_INDEX_BIT)
+               return ffs(val) - 1;
+       if (mix->mux_flags & CLK_MUX_INDEX_ONE)
+               return val - 1;
+       if (mix->mux_table) {
+               for (i = 0; i < num_parents; i++)
+                       if (mix->mux_table[i] == val)
+                               return i;
+               if (i == num_parents)
+                       return 0;
+       }
+
+       return val;
+}
+static unsigned int _get_div_val(struct mmp_clk_mix *mix, unsigned int div)
+{
+       struct clk_div_table *clkt;
+
+       if (mix->div_flags & CLK_DIVIDER_ONE_BASED)
+               return div;
+       if (mix->div_flags & CLK_DIVIDER_POWER_OF_TWO)
+               return __ffs(div);
+       if (mix->div_table) {
+               for (clkt = mix->div_table; clkt->div; clkt++)
+                       if (clkt->div == div)
+                               return clkt->val;
+               if (clkt->div == 0)
+                       return 0;
+       }
+
+       return div - 1;
+}
+
+static unsigned int _get_mux_val(struct mmp_clk_mix *mix, unsigned int mux)
+{
+       if (mix->mux_table)
+               return mix->mux_table[mux];
+
+       return mux;
+}
+
+static void _filter_clk_table(struct mmp_clk_mix *mix,
+                               struct mmp_clk_mix_clk_table *table,
+                               unsigned int table_size)
+{
+       int i;
+       struct mmp_clk_mix_clk_table *item;
+       struct clk *parent, *clk;
+       unsigned long parent_rate;
+
+       clk = mix->hw.clk;
+
+       for (i = 0; i < table_size; i++) {
+               item = &table[i];
+               parent = clk_get_parent_by_index(clk, item->parent_index);
+               parent_rate = __clk_get_rate(parent);
+               if (parent_rate % item->rate) {
+                       item->valid = 0;
+               } else {
+                       item->divisor = parent_rate / item->rate;
+                       item->valid = 1;
+               }
+       }
+}
+
+static int _set_rate(struct mmp_clk_mix *mix, u32 mux_val, u32 div_val,
+                       unsigned int change_mux, unsigned int change_div)
+{
+       struct mmp_clk_mix_reg_info *ri = &mix->reg_info;
+       u8 width, shift;
+       u32 mux_div, fc_req;
+       int ret, timeout = 50;
+       unsigned long flags = 0;
+
+       if (!change_mux && !change_div)
+               return -EINVAL;
+
+       if (mix->lock)
+               spin_lock_irqsave(mix->lock, flags);
+
+       if (mix->type == MMP_CLK_MIX_TYPE_V1
+               || mix->type == MMP_CLK_MIX_TYPE_V2)
+               mux_div = readl(ri->reg_clk_ctrl);
+       else
+               mux_div = readl(ri->reg_clk_sel);
+
+       if (change_div) {
+               width = ri->width_div;
+               shift = ri->shift_div;
+               mux_div &= ~MMP_CLK_BITS_MASK(width, shift);
+               mux_div |= MMP_CLK_BITS_SET_VAL(div_val, width, shift);
+       }
+
+       if (change_mux) {
+               width = ri->width_mux;
+               shift = ri->shift_mux;
+               mux_div &= ~MMP_CLK_BITS_MASK(width, shift);
+               mux_div |= MMP_CLK_BITS_SET_VAL(mux_val, width, shift);
+       }
+
+       if (mix->type == MMP_CLK_MIX_TYPE_V1) {
+               writel(mux_div, ri->reg_clk_ctrl);
+       } else if (mix->type == MMP_CLK_MIX_TYPE_V2) {
+               mux_div |= (1 << ri->bit_fc);
+               writel(mux_div, ri->reg_clk_ctrl);
+
+               do {
+                       fc_req = readl(ri->reg_clk_ctrl);
+                       timeout--;
+                       if (!(fc_req & (1 << ri->bit_fc)))
+                               break;
+               } while (timeout);
+
+               if (timeout == 0) {
+                       pr_err("%s:%s cannot do frequency change\n",
+                               __func__, __clk_get_name(mix->hw.clk));
+                       ret = -EBUSY;
+                       goto error;
+               }
+       } else {
+               fc_req = readl(ri->reg_clk_ctrl);
+               fc_req |= 1 << ri->bit_fc;
+               writel(fc_req, ri->reg_clk_ctrl);
+               writel(mux_div, ri->reg_clk_sel);
+               fc_req &= ~(1 << ri->bit_fc);
+       }
+
+       ret = 0;
+error:
+       if (mix->lock)
+               spin_unlock_irqrestore(mix->lock, flags);
+
+       return ret;
+}
+
+static long mmp_clk_mix_determine_rate(struct clk_hw *hw, unsigned long rate,
+                                       unsigned long *best_parent_rate,
+                                       struct clk_hw **best_parent_clk)
+{
+       struct mmp_clk_mix *mix = to_clk_mix(hw);
+       struct mmp_clk_mix_clk_table *item;
+       struct clk *parent, *parent_best, *mix_clk;
+       unsigned long parent_rate, mix_rate, mix_rate_best, parent_rate_best;
+       unsigned long gap, gap_best;
+       u32 div_val_max;
+       unsigned int div;
+       int i, j;
+
+       mix_clk = hw->clk;
+
+       parent = NULL;
+       mix_rate_best = 0;
+       parent_rate_best = 0;
+       gap_best = rate;
+       parent_best = NULL;
+
+       if (mix->table) {
+               for (i = 0; i < mix->table_size; i++) {
+                       item = &mix->table[i];
+                       if (item->valid == 0)
+                               continue;
+                       parent = clk_get_parent_by_index(mix_clk,
+                                                       item->parent_index);
+                       parent_rate = __clk_get_rate(parent);
+                       mix_rate = parent_rate / item->divisor;
+                       gap = abs(mix_rate - rate);
+                       if (parent_best == NULL || gap < gap_best) {
+                               parent_best = parent;
+                               parent_rate_best = parent_rate;
+                               mix_rate_best = mix_rate;
+                               gap_best = gap;
+                               if (gap_best == 0)
+                                       goto found;
+                       }
+               }
+       } else {
+               for (i = 0; i < __clk_get_num_parents(mix_clk); i++) {
+                       parent = clk_get_parent_by_index(mix_clk, i);
+                       parent_rate = __clk_get_rate(parent);
+                       div_val_max = _get_maxdiv(mix);
+                       for (j = 0; j < div_val_max; j++) {
+                               div = _get_div(mix, j);
+                               mix_rate = parent_rate / div;
+                               gap = abs(mix_rate - rate);
+                               if (parent_best == NULL || gap < gap_best) {
+                                       parent_best = parent;
+                                       parent_rate_best = parent_rate;
+                                       mix_rate_best = mix_rate;
+                                       gap_best = gap;
+                                       if (gap_best == 0)
+                                               goto found;
+                               }
+                       }
+               }
+       }
+
+found:
+       *best_parent_rate = parent_rate_best;
+       *best_parent_clk = __clk_get_hw(parent_best);
+
+       return mix_rate_best;
+}
+
+static int mmp_clk_mix_set_rate_and_parent(struct clk_hw *hw,
+                                               unsigned long rate,
+                                               unsigned long parent_rate,
+                                               u8 index)
+{
+       struct mmp_clk_mix *mix = to_clk_mix(hw);
+       unsigned int div;
+       u32 div_val, mux_val;
+
+       div = parent_rate / rate;
+       div_val = _get_div_val(mix, div);
+       mux_val = _get_mux_val(mix, index);
+
+       return _set_rate(mix, mux_val, div_val, 1, 1);
+}
+
+static u8 mmp_clk_mix_get_parent(struct clk_hw *hw)
+{
+       struct mmp_clk_mix *mix = to_clk_mix(hw);
+       struct mmp_clk_mix_reg_info *ri = &mix->reg_info;
+       unsigned long flags = 0;
+       u32 mux_div = 0;
+       u8 width, shift;
+       u32 mux_val;
+
+       if (mix->lock)
+               spin_lock_irqsave(mix->lock, flags);
+
+       if (mix->type == MMP_CLK_MIX_TYPE_V1
+               || mix->type == MMP_CLK_MIX_TYPE_V2)
+               mux_div = readl(ri->reg_clk_ctrl);
+       else
+               mux_div = readl(ri->reg_clk_sel);
+
+       if (mix->lock)
+               spin_unlock_irqrestore(mix->lock, flags);
+
+       width = mix->reg_info.width_mux;
+       shift = mix->reg_info.shift_mux;
+
+       mux_val = MMP_CLK_BITS_GET_VAL(mux_div, width, shift);
+
+       return _get_mux(mix, mux_val);
+}
+
+static unsigned long mmp_clk_mix_recalc_rate(struct clk_hw *hw,
+                                       unsigned long parent_rate)
+{
+       struct mmp_clk_mix *mix = to_clk_mix(hw);
+       struct mmp_clk_mix_reg_info *ri = &mix->reg_info;
+       unsigned long flags = 0;
+       u32 mux_div = 0;
+       u8 width, shift;
+       unsigned int div;
+
+       if (mix->lock)
+               spin_lock_irqsave(mix->lock, flags);
+
+       if (mix->type == MMP_CLK_MIX_TYPE_V1
+               || mix->type == MMP_CLK_MIX_TYPE_V2)
+               mux_div = readl(ri->reg_clk_ctrl);
+       else
+               mux_div = readl(ri->reg_clk_sel);
+
+       if (mix->lock)
+               spin_unlock_irqrestore(mix->lock, flags);
+
+       width = mix->reg_info.width_div;
+       shift = mix->reg_info.shift_div;
+
+       div = _get_div(mix, MMP_CLK_BITS_GET_VAL(mux_div, width, shift));
+
+       return parent_rate / div;
+}
+
+static int mmp_clk_set_parent(struct clk_hw *hw, u8 index)
+{
+       struct mmp_clk_mix *mix = to_clk_mix(hw);
+       struct mmp_clk_mix_clk_table *item;
+       int i;
+       u32 div_val, mux_val;
+
+       if (mix->table) {
+               for (i = 0; i < mix->table_size; i++) {
+                       item = &mix->table[i];
+                       if (item->valid == 0)
+                               continue;
+                       if (item->parent_index == index)
+                               break;
+               }
+               if (i < mix->table_size) {
+                       div_val = _get_div_val(mix, item->divisor);
+                       mux_val = _get_mux_val(mix, item->parent_index);
+               } else
+                       return -EINVAL;
+       } else {
+               mux_val = _get_mux_val(mix, index);
+               div_val = 0;
+       }
+
+       return _set_rate(mix, mux_val, div_val, 1, div_val ? 1 : 0);
+}
+
+static int mmp_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                               unsigned long best_parent_rate)
+{
+       struct mmp_clk_mix *mix = to_clk_mix(hw);
+       struct mmp_clk_mix_clk_table *item;
+       unsigned long parent_rate;
+       unsigned int best_divisor;
+       struct clk *mix_clk, *parent;
+       int i;
+
+       best_divisor = best_parent_rate / rate;
+
+       mix_clk = hw->clk;
+       if (mix->table) {
+               for (i = 0; i < mix->table_size; i++) {
+                       item = &mix->table[i];
+                       if (item->valid == 0)
+                               continue;
+                       parent = clk_get_parent_by_index(mix_clk,
+                                                       item->parent_index);
+                       parent_rate = __clk_get_rate(parent);
+                       if (parent_rate == best_parent_rate
+                               && item->divisor == best_divisor)
+                               break;
+               }
+               if (i < mix->table_size)
+                       return _set_rate(mix,
+                                       _get_mux_val(mix, item->parent_index),
+                                       _get_div_val(mix, item->divisor),
+                                       1, 1);
+               else
+                       return -EINVAL;
+       } else {
+               for (i = 0; i < __clk_get_num_parents(mix_clk); i++) {
+                       parent = clk_get_parent_by_index(mix_clk, i);
+                       parent_rate = __clk_get_rate(parent);
+                       if (parent_rate == best_parent_rate)
+                               break;
+               }
+               if (i < __clk_get_num_parents(mix_clk))
+                       return _set_rate(mix, _get_mux_val(mix, i),
+                                       _get_div_val(mix, best_divisor), 1, 1);
+               else
+                       return -EINVAL;
+       }
+}
+
+static void mmp_clk_mix_init(struct clk_hw *hw)
+{
+       struct mmp_clk_mix *mix = to_clk_mix(hw);
+
+       if (mix->table)
+               _filter_clk_table(mix, mix->table, mix->table_size);
+}
+
+const struct clk_ops mmp_clk_mix_ops = {
+       .determine_rate = mmp_clk_mix_determine_rate,
+       .set_rate_and_parent = mmp_clk_mix_set_rate_and_parent,
+       .set_rate = mmp_clk_set_rate,
+       .set_parent = mmp_clk_set_parent,
+       .get_parent = mmp_clk_mix_get_parent,
+       .recalc_rate = mmp_clk_mix_recalc_rate,
+       .init = mmp_clk_mix_init,
+};
+
+struct clk *mmp_clk_register_mix(struct device *dev,
+                                       const char *name,
+                                       const char **parent_names,
+                                       u8 num_parents,
+                                       unsigned long flags,
+                                       struct mmp_clk_mix_config *config,
+                                       spinlock_t *lock)
+{
+       struct mmp_clk_mix *mix;
+       struct clk *clk;
+       struct clk_init_data init;
+       size_t table_bytes;
+
+       mix = kzalloc(sizeof(*mix), GFP_KERNEL);
+       if (!mix) {
+               pr_err("%s:%s: could not allocate mmp mix clk\n",
+                       __func__, name);
+               return ERR_PTR(-ENOMEM);
+       }
+
+       init.name = name;
+       init.flags = flags | CLK_GET_RATE_NOCACHE;
+       init.parent_names = parent_names;
+       init.num_parents = num_parents;
+       init.ops = &mmp_clk_mix_ops;
+
+       memcpy(&mix->reg_info, &config->reg_info, sizeof(config->reg_info));
+       if (config->table) {
+               table_bytes = sizeof(*config->table) * config->table_size;
+               mix->table = kzalloc(table_bytes, GFP_KERNEL);
+               if (!mix->table) {
+                       pr_err("%s:%s: could not allocate mmp mix table\n",
+                               __func__, name);
+                       kfree(mix);
+                       return ERR_PTR(-ENOMEM);
+               }
+               memcpy(mix->table, config->table, table_bytes);
+               mix->table_size = config->table_size;
+       }
+
+       if (config->mux_table) {
+               table_bytes = sizeof(u32) * num_parents;
+               mix->mux_table = kzalloc(table_bytes, GFP_KERNEL);
+               if (!mix->mux_table) {
+                       pr_err("%s:%s: could not allocate mmp mix mux-table\n",
+                               __func__, name);
+                       kfree(mix->table);
+                       kfree(mix);
+                       return ERR_PTR(-ENOMEM);
+               }
+               memcpy(mix->mux_table, config->mux_table, table_bytes);
+       }
+
+       mix->div_flags = config->div_flags;
+       mix->mux_flags = config->mux_flags;
+       mix->lock = lock;
+       mix->hw.init = &init;
+
+       if (config->reg_info.bit_fc >= 32)
+               mix->type = MMP_CLK_MIX_TYPE_V1;
+       else if (config->reg_info.reg_clk_sel)
+               mix->type = MMP_CLK_MIX_TYPE_V3;
+       else
+               mix->type = MMP_CLK_MIX_TYPE_V2;
+       clk = clk_register(dev, &mix->hw);
+
+       if (IS_ERR(clk)) {
+               kfree(mix->mux_table);
+               kfree(mix->table);
+               kfree(mix);
+       }
+
+       return clk;
+}
index b2721cae257adcca4a106cee4e9a9e443bf5d808..5c90a4230fa3d3f2718c7ed6452c32c51df70b24 100644 (file)
@@ -54,7 +54,7 @@
 
 static DEFINE_SPINLOCK(clk_lock);
 
-static struct clk_factor_masks uart_factor_masks = {
+static struct mmp_clk_factor_masks uart_factor_masks = {
        .factor = 2,
        .num_mask = 0x1fff,
        .den_mask = 0x1fff,
@@ -62,7 +62,7 @@ static struct clk_factor_masks uart_factor_masks = {
        .den_shift = 0,
 };
 
-static struct clk_factor_tbl uart_factor_tbl[] = {
+static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
        {.num = 14634, .den = 2165},    /*14.745MHZ */
        {.num = 3521, .den = 689},      /*19.23MHZ */
        {.num = 9679, .den = 5728},     /*58.9824MHZ */
@@ -191,7 +191,7 @@ void __init mmp2_clk_init(void)
        clk = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
                                mpmu_base + MPMU_UART_PLL,
                                &uart_factor_masks, uart_factor_tbl,
-                               ARRAY_SIZE(uart_factor_tbl));
+                               ARRAY_SIZE(uart_factor_tbl), &clk_lock);
        clk_set_rate(clk, 14745600);
        clk_register_clkdev(clk, "uart_pll", NULL);
 
diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c
new file mode 100644 (file)
index 0000000..2cbc2b4
--- /dev/null
@@ -0,0 +1,334 @@
+/*
+ * mmp2 clock framework source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/of_address.h>
+
+#include <dt-bindings/clock/marvell,mmp2.h>
+
+#include "clk.h"
+#include "reset.h"
+
+#define APBC_RTC       0x0
+#define APBC_TWSI0     0x4
+#define APBC_TWSI1     0x8
+#define APBC_TWSI2     0xc
+#define APBC_TWSI3     0x10
+#define APBC_TWSI4     0x7c
+#define APBC_TWSI5     0x80
+#define APBC_KPC       0x18
+#define APBC_UART0     0x2c
+#define APBC_UART1     0x30
+#define APBC_UART2     0x34
+#define APBC_UART3     0x88
+#define APBC_GPIO      0x38
+#define APBC_PWM0      0x3c
+#define APBC_PWM1      0x40
+#define APBC_PWM2      0x44
+#define APBC_PWM3      0x48
+#define APBC_SSP0      0x50
+#define APBC_SSP1      0x54
+#define APBC_SSP2      0x58
+#define APBC_SSP3      0x5c
+#define APMU_SDH0      0x54
+#define APMU_SDH1      0x58
+#define APMU_SDH2      0xe8
+#define APMU_SDH3      0xec
+#define APMU_USB       0x5c
+#define APMU_DISP0     0x4c
+#define APMU_DISP1     0x110
+#define APMU_CCIC0     0x50
+#define APMU_CCIC1     0xf4
+#define MPMU_UART_PLL  0x14
+
+struct mmp2_clk_unit {
+       struct mmp_clk_unit unit;
+       void __iomem *mpmu_base;
+       void __iomem *apmu_base;
+       void __iomem *apbc_base;
+};
+
+static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
+       {MMP2_CLK_CLK32, "clk32", NULL, CLK_IS_ROOT, 32768},
+       {MMP2_CLK_VCTCXO, "vctcxo", NULL, CLK_IS_ROOT, 26000000},
+       {MMP2_CLK_PLL1, "pll1", NULL, CLK_IS_ROOT, 800000000},
+       {MMP2_CLK_PLL2, "pll2", NULL, CLK_IS_ROOT, 960000000},
+       {MMP2_CLK_USB_PLL, "usb_pll", NULL, CLK_IS_ROOT, 480000000},
+};
+
+static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
+       {MMP2_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
+       {MMP2_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0},
+       {MMP2_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0},
+       {MMP2_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0},
+       {MMP2_CLK_PLL1_20, "pll1_20", "pll1_4", 1, 5, 0},
+       {MMP2_CLK_PLL1_3, "pll1_3", "pll1", 1, 3, 0},
+       {MMP2_CLK_PLL1_6, "pll1_6", "pll1_3", 1, 2, 0},
+       {MMP2_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0},
+       {MMP2_CLK_PLL2_2, "pll2_2", "pll2", 1, 2, 0},
+       {MMP2_CLK_PLL2_4, "pll2_4", "pll2_2", 1, 2, 0},
+       {MMP2_CLK_PLL2_8, "pll2_8", "pll2_4", 1, 2, 0},
+       {MMP2_CLK_PLL2_16, "pll2_16", "pll2_8", 1, 2, 0},
+       {MMP2_CLK_PLL2_3, "pll2_3", "pll2", 1, 3, 0},
+       {MMP2_CLK_PLL2_6, "pll2_6", "pll2_3", 1, 2, 0},
+       {MMP2_CLK_PLL2_12, "pll2_12", "pll2_6", 1, 2, 0},
+       {MMP2_CLK_VCTCXO_2, "vctcxo_2", "vctcxo", 1, 2, 0},
+       {MMP2_CLK_VCTCXO_4, "vctcxo_4", "vctcxo_2", 1, 2, 0},
+};
+
+static struct mmp_clk_factor_masks uart_factor_masks = {
+       .factor = 2,
+       .num_mask = 0x1fff,
+       .den_mask = 0x1fff,
+       .num_shift = 16,
+       .den_shift = 0,
+};
+
+static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
+       {.num = 14634, .den = 2165},    /*14.745MHZ */
+       {.num = 3521, .den = 689},      /*19.23MHZ */
+       {.num = 9679, .den = 5728},     /*58.9824MHZ */
+       {.num = 15850, .den = 9451},    /*59.429MHZ */
+};
+
+static void mmp2_pll_init(struct mmp2_clk_unit *pxa_unit)
+{
+       struct clk *clk;
+       struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+       mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
+                                       ARRAY_SIZE(fixed_rate_clks));
+
+       mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
+                                       ARRAY_SIZE(fixed_factor_clks));
+
+       clk = mmp_clk_register_factor("uart_pll", "pll1_4",
+                               CLK_SET_RATE_PARENT,
+                               pxa_unit->mpmu_base + MPMU_UART_PLL,
+                               &uart_factor_masks, uart_factor_tbl,
+                               ARRAY_SIZE(uart_factor_tbl), NULL);
+       mmp_clk_add(unit, MMP2_CLK_UART_PLL, clk);
+}
+
+static DEFINE_SPINLOCK(uart0_lock);
+static DEFINE_SPINLOCK(uart1_lock);
+static DEFINE_SPINLOCK(uart2_lock);
+static const char *uart_parent_names[] = {"uart_pll", "vctcxo"};
+
+static DEFINE_SPINLOCK(ssp0_lock);
+static DEFINE_SPINLOCK(ssp1_lock);
+static DEFINE_SPINLOCK(ssp2_lock);
+static DEFINE_SPINLOCK(ssp3_lock);
+static const char *ssp_parent_names[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
+
+static DEFINE_SPINLOCK(reset_lock);
+
+static struct mmp_param_mux_clk apbc_mux_clks[] = {
+       {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
+       {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
+       {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2, 4, 3, 0, &uart2_lock},
+       {0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART3, 4, 3, 0, &uart2_lock},
+       {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
+       {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
+       {0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP2, 4, 3, 0, &ssp2_lock},
+       {0, "ssp3_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP3, 4, 3, 0, &ssp3_lock},
+};
+
+static struct mmp_param_gate_clk apbc_gate_clks[] = {
+       {MMP2_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x7, 0x3, 0x0, 0, &reset_lock},
+       {MMP2_CLK_TWSI1, "twsi1_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x7, 0x3, 0x0, 0, &reset_lock},
+       {MMP2_CLK_TWSI2, "twsi2_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI2, 0x7, 0x3, 0x0, 0, &reset_lock},
+       {MMP2_CLK_TWSI3, "twsi3_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI3, 0x7, 0x3, 0x0, 0, &reset_lock},
+       {MMP2_CLK_TWSI4, "twsi4_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI4, 0x7, 0x3, 0x0, 0, &reset_lock},
+       {MMP2_CLK_TWSI5, "twsi5_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI5, 0x7, 0x3, 0x0, 0, &reset_lock},
+       {MMP2_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x7, 0x3, 0x0, 0, &reset_lock},
+       {MMP2_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
+       {MMP2_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x87, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
+       {MMP2_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x7, 0x3, 0x0, 0, &reset_lock},
+       {MMP2_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x7, 0x3, 0x0, 0, &reset_lock},
+       {MMP2_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x7, 0x3, 0x0, 0, &reset_lock},
+       {MMP2_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x7, 0x3, 0x0, 0, &reset_lock},
+       /* The gate clocks has mux parent. */
+       {MMP2_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x7, 0x3, 0x0, 0, &uart0_lock},
+       {MMP2_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x7, 0x3, 0x0, 0, &uart1_lock},
+       {MMP2_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBC_UART2, 0x7, 0x3, 0x0, 0, &uart2_lock},
+       {MMP2_CLK_UART3, "uart3_clk", "uart3_mux", CLK_SET_RATE_PARENT, APBC_UART3, 0x7, 0x3, 0x0, 0, &uart2_lock},
+       {MMP2_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x7, 0x3, 0x0, 0, &ssp0_lock},
+       {MMP2_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x7, 0x3, 0x0, 0, &ssp1_lock},
+       {MMP2_CLK_SSP2, "ssp2_clk", "ssp2_mux", CLK_SET_RATE_PARENT, APBC_SSP2, 0x7, 0x3, 0x0, 0, &ssp2_lock},
+       {MMP2_CLK_SSP3, "ssp3_clk", "ssp3_mux", CLK_SET_RATE_PARENT, APBC_SSP3, 0x7, 0x3, 0x0, 0, &ssp3_lock},
+};
+
+static void mmp2_apb_periph_clk_init(struct mmp2_clk_unit *pxa_unit)
+{
+       struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+       mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base,
+                               ARRAY_SIZE(apbc_mux_clks));
+
+       mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,
+                               ARRAY_SIZE(apbc_gate_clks));
+}
+
+static DEFINE_SPINLOCK(sdh_lock);
+static const char *sdh_parent_names[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
+static struct mmp_clk_mix_config sdh_mix_config = {
+       .reg_info = DEFINE_MIX_REG_INFO(4, 10, 2, 8, 32),
+};
+
+static DEFINE_SPINLOCK(usb_lock);
+
+static DEFINE_SPINLOCK(disp0_lock);
+static DEFINE_SPINLOCK(disp1_lock);
+static const char *disp_parent_names[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
+
+static DEFINE_SPINLOCK(ccic0_lock);
+static DEFINE_SPINLOCK(ccic1_lock);
+static const char *ccic_parent_names[] = {"pll1_2", "pll1_16", "vctcxo"};
+static struct mmp_clk_mix_config ccic0_mix_config = {
+       .reg_info = DEFINE_MIX_REG_INFO(4, 17, 2, 6, 32),
+};
+static struct mmp_clk_mix_config ccic1_mix_config = {
+       .reg_info = DEFINE_MIX_REG_INFO(4, 16, 2, 6, 32),
+};
+
+static struct mmp_param_mux_clk apmu_mux_clks[] = {
+       {MMP2_CLK_DISP0_MUX, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 2, 0, &disp0_lock},
+       {MMP2_CLK_DISP1_MUX, "disp1_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP1, 6, 2, 0, &disp1_lock},
+};
+
+static struct mmp_param_div_clk apmu_div_clks[] = {
+       {0, "disp0_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 8, 4, 0, &disp0_lock},
+       {0, "disp0_sphy_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 15, 5, 0, &disp0_lock},
+       {0, "disp1_div", "disp1_mux", CLK_SET_RATE_PARENT, APMU_DISP1, 8, 4, 0, &disp1_lock},
+       {0, "ccic0_sphy_div", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
+       {0, "ccic1_sphy_div", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 10, 5, 0, &ccic1_lock},
+};
+
+static struct mmp_param_gate_clk apmu_gate_clks[] = {
+       {MMP2_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock},
+       /* The gate clocks has mux parent. */
+       {MMP2_CLK_SDH0, "sdh0_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
+       {MMP2_CLK_SDH1, "sdh1_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
+       {MMP2_CLK_SDH1, "sdh2_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH2, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
+       {MMP2_CLK_SDH1, "sdh3_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH3, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
+       {MMP2_CLK_DISP0, "disp0_clk", "disp0_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, &disp0_lock},
+       {MMP2_CLK_DISP0_SPHY, "disp0_sphy_clk", "disp0_sphy_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1024, 0x1024, 0x0, 0, &disp0_lock},
+       {MMP2_CLK_DISP1, "disp1_clk", "disp1_div", CLK_SET_RATE_PARENT, APMU_DISP1, 0x1b, 0x1b, 0x0, 0, &disp1_lock},
+       {MMP2_CLK_CCIC_ARBITER, "ccic_arbiter", "vctcxo", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1800, 0x1800, 0x0, 0, &ccic0_lock},
+       {MMP2_CLK_CCIC0, "ccic0_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock},
+       {MMP2_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock},
+       {MMP2_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock},
+       {MMP2_CLK_CCIC1, "ccic1_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x1b, 0x1b, 0x0, 0, &ccic1_lock},
+       {MMP2_CLK_CCIC1_PHY, "ccic1_phy_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x24, 0x24, 0x0, 0, &ccic1_lock},
+       {MMP2_CLK_CCIC1_SPHY, "ccic1_sphy_clk", "ccic1_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x300, 0x300, 0x0, 0, &ccic1_lock},
+};
+
+static void mmp2_axi_periph_clk_init(struct mmp2_clk_unit *pxa_unit)
+{
+       struct clk *clk;
+       struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+       sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_SDH0;
+       clk = mmp_clk_register_mix(NULL, "sdh_mix_clk", sdh_parent_names,
+                                       ARRAY_SIZE(sdh_parent_names),
+                                       CLK_SET_RATE_PARENT,
+                                       &sdh_mix_config, &sdh_lock);
+
+       ccic0_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_CCIC0;
+       clk = mmp_clk_register_mix(NULL, "ccic0_mix_clk", ccic_parent_names,
+                                       ARRAY_SIZE(ccic_parent_names),
+                                       CLK_SET_RATE_PARENT,
+                                       &ccic0_mix_config, &ccic0_lock);
+       mmp_clk_add(unit, MMP2_CLK_CCIC0_MIX, clk);
+
+       ccic1_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_CCIC1;
+       clk = mmp_clk_register_mix(NULL, "ccic1_mix_clk", ccic_parent_names,
+                                       ARRAY_SIZE(ccic_parent_names),
+                                       CLK_SET_RATE_PARENT,
+                                       &ccic1_mix_config, &ccic1_lock);
+       mmp_clk_add(unit, MMP2_CLK_CCIC1_MIX, clk);
+
+       mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base,
+                               ARRAY_SIZE(apmu_mux_clks));
+
+       mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base,
+                               ARRAY_SIZE(apmu_div_clks));
+
+       mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,
+                               ARRAY_SIZE(apmu_gate_clks));
+}
+
+static void mmp2_clk_reset_init(struct device_node *np,
+                               struct mmp2_clk_unit *pxa_unit)
+{
+       struct mmp_clk_reset_cell *cells;
+       int i, nr_resets;
+
+       nr_resets = ARRAY_SIZE(apbc_gate_clks);
+       cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL);
+       if (!cells)
+               return;
+
+       for (i = 0; i < nr_resets; i++) {
+               cells[i].clk_id = apbc_gate_clks[i].id;
+               cells[i].reg = pxa_unit->apbc_base + apbc_gate_clks[i].offset;
+               cells[i].flags = 0;
+               cells[i].lock = apbc_gate_clks[i].lock;
+               cells[i].bits = 0x4;
+       }
+
+       mmp_clk_reset_register(np, cells, nr_resets);
+}
+
+static void __init mmp2_clk_init(struct device_node *np)
+{
+       struct mmp2_clk_unit *pxa_unit;
+
+       pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
+       if (!pxa_unit)
+               return;
+
+       pxa_unit->mpmu_base = of_iomap(np, 0);
+       if (!pxa_unit->mpmu_base) {
+               pr_err("failed to map mpmu registers\n");
+               return;
+       }
+
+       pxa_unit->apmu_base = of_iomap(np, 1);
+       if (!pxa_unit->mpmu_base) {
+               pr_err("failed to map apmu registers\n");
+               return;
+       }
+
+       pxa_unit->apbc_base = of_iomap(np, 2);
+       if (!pxa_unit->apbc_base) {
+               pr_err("failed to map apbc registers\n");
+               return;
+       }
+
+       mmp_clk_init(np, &pxa_unit->unit, MMP2_NR_CLKS);
+
+       mmp2_pll_init(pxa_unit);
+
+       mmp2_apb_periph_clk_init(pxa_unit);
+
+       mmp2_axi_periph_clk_init(pxa_unit);
+
+       mmp2_clk_reset_init(np, pxa_unit);
+}
+
+CLK_OF_DECLARE(mmp2_clk, "marvell,mmp2-clock", mmp2_clk_init);
diff --git a/drivers/clk/mmp/clk-of-pxa168.c b/drivers/clk/mmp/clk-of-pxa168.c
new file mode 100644 (file)
index 0000000..5b1810d
--- /dev/null
@@ -0,0 +1,279 @@
+/*
+ * pxa168 clock framework source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/of_address.h>
+
+#include <dt-bindings/clock/marvell,pxa168.h>
+
+#include "clk.h"
+#include "reset.h"
+
+#define APBC_RTC       0x28
+#define APBC_TWSI0     0x2c
+#define APBC_KPC       0x30
+#define APBC_UART0     0x0
+#define APBC_UART1     0x4
+#define APBC_GPIO      0x8
+#define APBC_PWM0      0xc
+#define APBC_PWM1      0x10
+#define APBC_PWM2      0x14
+#define APBC_PWM3      0x18
+#define APBC_SSP0      0x81c
+#define APBC_SSP1      0x820
+#define APBC_SSP2      0x84c
+#define APBC_SSP3      0x858
+#define APBC_SSP4      0x85c
+#define APBC_TWSI1     0x6c
+#define APBC_UART2     0x70
+#define APMU_SDH0      0x54
+#define APMU_SDH1      0x58
+#define APMU_USB       0x5c
+#define APMU_DISP0     0x4c
+#define APMU_CCIC0     0x50
+#define APMU_DFC       0x60
+#define MPMU_UART_PLL  0x14
+
+struct pxa168_clk_unit {
+       struct mmp_clk_unit unit;
+       void __iomem *mpmu_base;
+       void __iomem *apmu_base;
+       void __iomem *apbc_base;
+};
+
+static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
+       {PXA168_CLK_CLK32, "clk32", NULL, CLK_IS_ROOT, 32768},
+       {PXA168_CLK_VCTCXO, "vctcxo", NULL, CLK_IS_ROOT, 26000000},
+       {PXA168_CLK_PLL1, "pll1", NULL, CLK_IS_ROOT, 624000000},
+};
+
+static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
+       {PXA168_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
+       {PXA168_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0},
+       {PXA168_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0},
+       {PXA168_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0},
+       {PXA168_CLK_PLL1_6, "pll1_6", "pll1_2", 1, 3, 0},
+       {PXA168_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0},
+       {PXA168_CLK_PLL1_24, "pll1_24", "pll1_12", 1, 2, 0},
+       {PXA168_CLK_PLL1_48, "pll1_48", "pll1_24", 1, 2, 0},
+       {PXA168_CLK_PLL1_96, "pll1_96", "pll1_48", 1, 2, 0},
+       {PXA168_CLK_PLL1_13, "pll1_13", "pll1", 1, 13, 0},
+       {PXA168_CLK_PLL1_13_1_5, "pll1_13_1_5", "pll1_13", 2, 3, 0},
+       {PXA168_CLK_PLL1_2_1_5, "pll1_2_1_5", "pll1_2", 2, 3, 0},
+       {PXA168_CLK_PLL1_3_16, "pll1_3_16", "pll1", 3, 16, 0},
+};
+
+static struct mmp_clk_factor_masks uart_factor_masks = {
+       .factor = 2,
+       .num_mask = 0x1fff,
+       .den_mask = 0x1fff,
+       .num_shift = 16,
+       .den_shift = 0,
+};
+
+static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
+       {.num = 8125, .den = 1536},     /*14.745MHZ */
+};
+
+static void pxa168_pll_init(struct pxa168_clk_unit *pxa_unit)
+{
+       struct clk *clk;
+       struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+       mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
+                                       ARRAY_SIZE(fixed_rate_clks));
+
+       mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
+                                       ARRAY_SIZE(fixed_factor_clks));
+
+       clk = mmp_clk_register_factor("uart_pll", "pll1_4",
+                               CLK_SET_RATE_PARENT,
+                               pxa_unit->mpmu_base + MPMU_UART_PLL,
+                               &uart_factor_masks, uart_factor_tbl,
+                               ARRAY_SIZE(uart_factor_tbl), NULL);
+       mmp_clk_add(unit, PXA168_CLK_UART_PLL, clk);
+}
+
+static DEFINE_SPINLOCK(uart0_lock);
+static DEFINE_SPINLOCK(uart1_lock);
+static DEFINE_SPINLOCK(uart2_lock);
+static const char *uart_parent_names[] = {"pll1_3_16", "uart_pll"};
+
+static DEFINE_SPINLOCK(ssp0_lock);
+static DEFINE_SPINLOCK(ssp1_lock);
+static DEFINE_SPINLOCK(ssp2_lock);
+static DEFINE_SPINLOCK(ssp3_lock);
+static DEFINE_SPINLOCK(ssp4_lock);
+static const char *ssp_parent_names[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
+
+static DEFINE_SPINLOCK(reset_lock);
+
+static struct mmp_param_mux_clk apbc_mux_clks[] = {
+       {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
+       {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
+       {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2, 4, 3, 0, &uart2_lock},
+       {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
+       {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
+       {0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP2, 4, 3, 0, &ssp2_lock},
+       {0, "ssp3_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP3, 4, 3, 0, &ssp3_lock},
+       {0, "ssp4_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP4, 4, 3, 0, &ssp4_lock},
+};
+
+static struct mmp_param_gate_clk apbc_gate_clks[] = {
+       {PXA168_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, &reset_lock},
+       {PXA168_CLK_TWSI1, "twsi1_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x3, 0x3, 0x0, 0, &reset_lock},
+       {PXA168_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_lock},
+       {PXA168_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x3, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
+       {PXA168_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x83, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
+       {PXA168_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_lock},
+       {PXA168_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &reset_lock},
+       {PXA168_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x3, 0x3, 0x0, 0, &reset_lock},
+       {PXA168_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &reset_lock},
+       /* The gate clocks has mux parent. */
+       {PXA168_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x3, 0x3, 0x0, 0, &uart0_lock},
+       {PXA168_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x3, 0x3, 0x0, 0, &uart1_lock},
+       {PXA168_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBC_UART2, 0x3, 0x3, 0x0, 0, &uart2_lock},
+       {PXA168_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x3, 0x3, 0x0, 0, &ssp0_lock},
+       {PXA168_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x3, 0x3, 0x0, 0, &ssp1_lock},
+       {PXA168_CLK_SSP2, "ssp2_clk", "ssp2_mux", CLK_SET_RATE_PARENT, APBC_SSP2, 0x3, 0x3, 0x0, 0, &ssp2_lock},
+       {PXA168_CLK_SSP3, "ssp3_clk", "ssp3_mux", CLK_SET_RATE_PARENT, APBC_SSP3, 0x3, 0x3, 0x0, 0, &ssp3_lock},
+       {PXA168_CLK_SSP4, "ssp4_clk", "ssp4_mux", CLK_SET_RATE_PARENT, APBC_SSP4, 0x3, 0x3, 0x0, 0, &ssp4_lock},
+};
+
+static void pxa168_apb_periph_clk_init(struct pxa168_clk_unit *pxa_unit)
+{
+       struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+       mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base,
+                               ARRAY_SIZE(apbc_mux_clks));
+
+       mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,
+                               ARRAY_SIZE(apbc_gate_clks));
+
+}
+
+static DEFINE_SPINLOCK(sdh0_lock);
+static DEFINE_SPINLOCK(sdh1_lock);
+static const char *sdh_parent_names[] = {"pll1_12", "pll1_13"};
+
+static DEFINE_SPINLOCK(usb_lock);
+
+static DEFINE_SPINLOCK(disp0_lock);
+static const char *disp_parent_names[] = {"pll1_2", "pll1_12"};
+
+static DEFINE_SPINLOCK(ccic0_lock);
+static const char *ccic_parent_names[] = {"pll1_2", "pll1_12"};
+static const char *ccic_phy_parent_names[] = {"pll1_6", "pll1_12"};
+
+static struct mmp_param_mux_clk apmu_mux_clks[] = {
+       {0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6, 1, 0, &sdh0_lock},
+       {0, "sdh1_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH1, 6, 1, 0, &sdh1_lock},
+       {0, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 1, 0, &disp0_lock},
+       {0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 6, 1, 0, &ccic0_lock},
+       {0, "ccic0_phy_mux", ccic_phy_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0_lock},
+};
+
+static struct mmp_param_div_clk apmu_div_clks[] = {
+       {0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
+};
+
+static struct mmp_param_gate_clk apmu_gate_clks[] = {
+       {PXA168_CLK_DFC, "dfc_clk", "pll1_4", CLK_SET_RATE_PARENT, APMU_DFC, 0x19b, 0x19b, 0x0, 0, NULL},
+       {PXA168_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock},
+       {PXA168_CLK_SPH, "sph_clk", "usb_pll", 0, APMU_USB, 0x12, 0x12, 0x0, 0, &usb_lock},
+       /* The gate clocks has mux parent. */
+       {PXA168_CLK_SDH0, "sdh0_clk", "sdh0_mux", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh0_lock},
+       {PXA168_CLK_SDH1, "sdh1_clk", "sdh1_mux", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh1_lock},
+       {PXA168_CLK_DISP0, "disp0_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, &disp0_lock},
+       {PXA168_CLK_CCIC0, "ccic0_clk", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock},
+       {PXA168_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_phy_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock},
+       {PXA168_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock},
+};
+
+static void pxa168_axi_periph_clk_init(struct pxa168_clk_unit *pxa_unit)
+{
+       struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+       mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base,
+                               ARRAY_SIZE(apmu_mux_clks));
+
+       mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base,
+                               ARRAY_SIZE(apmu_div_clks));
+
+       mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,
+                               ARRAY_SIZE(apmu_gate_clks));
+}
+
+static void pxa168_clk_reset_init(struct device_node *np,
+                               struct pxa168_clk_unit *pxa_unit)
+{
+       struct mmp_clk_reset_cell *cells;
+       int i, nr_resets;
+
+       nr_resets = ARRAY_SIZE(apbc_gate_clks);
+       cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL);
+       if (!cells)
+               return;
+
+       for (i = 0; i < nr_resets; i++) {
+               cells[i].clk_id = apbc_gate_clks[i].id;
+               cells[i].reg = pxa_unit->apbc_base + apbc_gate_clks[i].offset;
+               cells[i].flags = 0;
+               cells[i].lock = apbc_gate_clks[i].lock;
+               cells[i].bits = 0x4;
+       }
+
+       mmp_clk_reset_register(np, cells, nr_resets);
+}
+
+static void __init pxa168_clk_init(struct device_node *np)
+{
+       struct pxa168_clk_unit *pxa_unit;
+
+       pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
+       if (!pxa_unit)
+               return;
+
+       pxa_unit->mpmu_base = of_iomap(np, 0);
+       if (!pxa_unit->mpmu_base) {
+               pr_err("failed to map mpmu registers\n");
+               return;
+       }
+
+       pxa_unit->apmu_base = of_iomap(np, 1);
+       if (!pxa_unit->mpmu_base) {
+               pr_err("failed to map apmu registers\n");
+               return;
+       }
+
+       pxa_unit->apbc_base = of_iomap(np, 2);
+       if (!pxa_unit->apbc_base) {
+               pr_err("failed to map apbc registers\n");
+               return;
+       }
+
+       mmp_clk_init(np, &pxa_unit->unit, PXA168_NR_CLKS);
+
+       pxa168_pll_init(pxa_unit);
+
+       pxa168_apb_periph_clk_init(pxa_unit);
+
+       pxa168_axi_periph_clk_init(pxa_unit);
+
+       pxa168_clk_reset_init(np, pxa_unit);
+}
+
+CLK_OF_DECLARE(pxa168_clk, "marvell,pxa168-clock", pxa168_clk_init);
diff --git a/drivers/clk/mmp/clk-of-pxa910.c b/drivers/clk/mmp/clk-of-pxa910.c
new file mode 100644 (file)
index 0000000..5e3c80d
--- /dev/null
@@ -0,0 +1,301 @@
+/*
+ * pxa910 clock framework source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/of_address.h>
+
+#include <dt-bindings/clock/marvell,pxa910.h>
+
+#include "clk.h"
+#include "reset.h"
+
+#define APBC_RTC       0x28
+#define APBC_TWSI0     0x2c
+#define APBC_KPC       0x18
+#define APBC_UART0     0x0
+#define APBC_UART1     0x4
+#define APBC_GPIO      0x8
+#define APBC_PWM0      0xc
+#define APBC_PWM1      0x10
+#define APBC_PWM2      0x14
+#define APBC_PWM3      0x18
+#define APBC_SSP0      0x1c
+#define APBC_SSP1      0x20
+#define APBC_SSP2      0x4c
+#define APBCP_TWSI1    0x28
+#define APBCP_UART2    0x1c
+#define APMU_SDH0      0x54
+#define APMU_SDH1      0x58
+#define APMU_USB       0x5c
+#define APMU_DISP0     0x4c
+#define APMU_CCIC0     0x50
+#define APMU_DFC       0x60
+#define MPMU_UART_PLL  0x14
+
+struct pxa910_clk_unit {
+       struct mmp_clk_unit unit;
+       void __iomem *mpmu_base;
+       void __iomem *apmu_base;
+       void __iomem *apbc_base;
+       void __iomem *apbcp_base;
+};
+
+static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
+       {PXA910_CLK_CLK32, "clk32", NULL, CLK_IS_ROOT, 32768},
+       {PXA910_CLK_VCTCXO, "vctcxo", NULL, CLK_IS_ROOT, 26000000},
+       {PXA910_CLK_PLL1, "pll1", NULL, CLK_IS_ROOT, 624000000},
+};
+
+static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
+       {PXA910_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
+       {PXA910_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0},
+       {PXA910_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0},
+       {PXA910_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0},
+       {PXA910_CLK_PLL1_6, "pll1_6", "pll1_2", 1, 3, 0},
+       {PXA910_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0},
+       {PXA910_CLK_PLL1_24, "pll1_24", "pll1_12", 1, 2, 0},
+       {PXA910_CLK_PLL1_48, "pll1_48", "pll1_24", 1, 2, 0},
+       {PXA910_CLK_PLL1_96, "pll1_96", "pll1_48", 1, 2, 0},
+       {PXA910_CLK_PLL1_13, "pll1_13", "pll1", 1, 13, 0},
+       {PXA910_CLK_PLL1_13_1_5, "pll1_13_1_5", "pll1_13", 2, 3, 0},
+       {PXA910_CLK_PLL1_2_1_5, "pll1_2_1_5", "pll1_2", 2, 3, 0},
+       {PXA910_CLK_PLL1_3_16, "pll1_3_16", "pll1", 3, 16, 0},
+};
+
+static struct mmp_clk_factor_masks uart_factor_masks = {
+       .factor = 2,
+       .num_mask = 0x1fff,
+       .den_mask = 0x1fff,
+       .num_shift = 16,
+       .den_shift = 0,
+};
+
+static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
+       {.num = 8125, .den = 1536},     /*14.745MHZ */
+};
+
+static void pxa910_pll_init(struct pxa910_clk_unit *pxa_unit)
+{
+       struct clk *clk;
+       struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+       mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
+                                       ARRAY_SIZE(fixed_rate_clks));
+
+       mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
+                                       ARRAY_SIZE(fixed_factor_clks));
+
+       clk = mmp_clk_register_factor("uart_pll", "pll1_4",
+                               CLK_SET_RATE_PARENT,
+                               pxa_unit->mpmu_base + MPMU_UART_PLL,
+                               &uart_factor_masks, uart_factor_tbl,
+                               ARRAY_SIZE(uart_factor_tbl), NULL);
+       mmp_clk_add(unit, PXA910_CLK_UART_PLL, clk);
+}
+
+static DEFINE_SPINLOCK(uart0_lock);
+static DEFINE_SPINLOCK(uart1_lock);
+static DEFINE_SPINLOCK(uart2_lock);
+static const char *uart_parent_names[] = {"pll1_3_16", "uart_pll"};
+
+static DEFINE_SPINLOCK(ssp0_lock);
+static DEFINE_SPINLOCK(ssp1_lock);
+static const char *ssp_parent_names[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
+
+static DEFINE_SPINLOCK(reset_lock);
+
+static struct mmp_param_mux_clk apbc_mux_clks[] = {
+       {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
+       {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
+       {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
+       {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
+};
+
+static struct mmp_param_mux_clk apbcp_mux_clks[] = {
+       {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBCP_UART2, 4, 3, 0, &uart2_lock},
+};
+
+static struct mmp_param_gate_clk apbc_gate_clks[] = {
+       {PXA910_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, &reset_lock},
+       {PXA910_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_lock},
+       {PXA910_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x3, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
+       {PXA910_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x83, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
+       {PXA910_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_lock},
+       {PXA910_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &reset_lock},
+       {PXA910_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x3, 0x3, 0x0, 0, &reset_lock},
+       {PXA910_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &reset_lock},
+       /* The gate clocks has mux parent. */
+       {PXA910_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x3, 0x3, 0x0, 0, &uart0_lock},
+       {PXA910_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x3, 0x3, 0x0, 0, &uart1_lock},
+       {PXA910_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x3, 0x3, 0x0, 0, &ssp0_lock},
+       {PXA910_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x3, 0x3, 0x0, 0, &ssp1_lock},
+};
+
+static struct mmp_param_gate_clk apbcp_gate_clks[] = {
+       {PXA910_CLK_TWSI1, "twsi1_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBCP_TWSI1, 0x3, 0x3, 0x0, 0, &reset_lock},
+       /* The gate clocks has mux parent. */
+       {PXA910_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBCP_UART2, 0x3, 0x3, 0x0, 0, &uart2_lock},
+};
+
+static void pxa910_apb_periph_clk_init(struct pxa910_clk_unit *pxa_unit)
+{
+       struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+       mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base,
+                               ARRAY_SIZE(apbc_mux_clks));
+
+       mmp_register_mux_clks(unit, apbcp_mux_clks, pxa_unit->apbcp_base,
+                               ARRAY_SIZE(apbcp_mux_clks));
+
+       mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,
+                               ARRAY_SIZE(apbc_gate_clks));
+
+       mmp_register_gate_clks(unit, apbcp_gate_clks, pxa_unit->apbcp_base,
+                               ARRAY_SIZE(apbcp_gate_clks));
+}
+
+static DEFINE_SPINLOCK(sdh0_lock);
+static DEFINE_SPINLOCK(sdh1_lock);
+static const char *sdh_parent_names[] = {"pll1_12", "pll1_13"};
+
+static DEFINE_SPINLOCK(usb_lock);
+
+static DEFINE_SPINLOCK(disp0_lock);
+static const char *disp_parent_names[] = {"pll1_2", "pll1_12"};
+
+static DEFINE_SPINLOCK(ccic0_lock);
+static const char *ccic_parent_names[] = {"pll1_2", "pll1_12"};
+static const char *ccic_phy_parent_names[] = {"pll1_6", "pll1_12"};
+
+static struct mmp_param_mux_clk apmu_mux_clks[] = {
+       {0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6, 1, 0, &sdh0_lock},
+       {0, "sdh1_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH1, 6, 1, 0, &sdh1_lock},
+       {0, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 1, 0, &disp0_lock},
+       {0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 6, 1, 0, &ccic0_lock},
+       {0, "ccic0_phy_mux", ccic_phy_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0_lock},
+};
+
+static struct mmp_param_div_clk apmu_div_clks[] = {
+       {0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
+};
+
+static struct mmp_param_gate_clk apmu_gate_clks[] = {
+       {PXA910_CLK_DFC, "dfc_clk", "pll1_4", CLK_SET_RATE_PARENT, APMU_DFC, 0x19b, 0x19b, 0x0, 0, NULL},
+       {PXA910_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock},
+       {PXA910_CLK_SPH, "sph_clk", "usb_pll", 0, APMU_USB, 0x12, 0x12, 0x0, 0, &usb_lock},
+       /* The gate clocks has mux parent. */
+       {PXA910_CLK_SDH0, "sdh0_clk", "sdh0_mux", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh0_lock},
+       {PXA910_CLK_SDH1, "sdh1_clk", "sdh1_mux", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh1_lock},
+       {PXA910_CLK_DISP0, "disp0_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, &disp0_lock},
+       {PXA910_CLK_CCIC0, "ccic0_clk", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock},
+       {PXA910_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_phy_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock},
+       {PXA910_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock},
+};
+
+static void pxa910_axi_periph_clk_init(struct pxa910_clk_unit *pxa_unit)
+{
+       struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+       mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base,
+                               ARRAY_SIZE(apmu_mux_clks));
+
+       mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base,
+                               ARRAY_SIZE(apmu_div_clks));
+
+       mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,
+                               ARRAY_SIZE(apmu_gate_clks));
+}
+
+static void pxa910_clk_reset_init(struct device_node *np,
+                               struct pxa910_clk_unit *pxa_unit)
+{
+       struct mmp_clk_reset_cell *cells;
+       int i, base, nr_resets_apbc, nr_resets_apbcp, nr_resets;
+
+       nr_resets_apbc = ARRAY_SIZE(apbc_gate_clks);
+       nr_resets_apbcp = ARRAY_SIZE(apbcp_gate_clks);
+       nr_resets = nr_resets_apbc + nr_resets_apbcp;
+       cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL);
+       if (!cells)
+               return;
+
+       base = 0;
+       for (i = 0; i < nr_resets_apbc; i++) {
+               cells[base + i].clk_id = apbc_gate_clks[i].id;
+               cells[base + i].reg =
+                       pxa_unit->apbc_base + apbc_gate_clks[i].offset;
+               cells[base + i].flags = 0;
+               cells[base + i].lock = apbc_gate_clks[i].lock;
+               cells[base + i].bits = 0x4;
+       }
+
+       base = nr_resets_apbc;
+       for (i = 0; i < nr_resets_apbcp; i++) {
+               cells[base + i].clk_id = apbcp_gate_clks[i].id;
+               cells[base + i].reg =
+                       pxa_unit->apbc_base + apbc_gate_clks[i].offset;
+               cells[base + i].flags = 0;
+               cells[base + i].lock = apbc_gate_clks[i].lock;
+               cells[base + i].bits = 0x4;
+       }
+
+       mmp_clk_reset_register(np, cells, nr_resets);
+}
+
+static void __init pxa910_clk_init(struct device_node *np)
+{
+       struct pxa910_clk_unit *pxa_unit;
+
+       pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
+       if (!pxa_unit)
+               return;
+
+       pxa_unit->mpmu_base = of_iomap(np, 0);
+       if (!pxa_unit->mpmu_base) {
+               pr_err("failed to map mpmu registers\n");
+               return;
+       }
+
+       pxa_unit->apmu_base = of_iomap(np, 1);
+       if (!pxa_unit->mpmu_base) {
+               pr_err("failed to map apmu registers\n");
+               return;
+       }
+
+       pxa_unit->apbc_base = of_iomap(np, 2);
+       if (!pxa_unit->apbc_base) {
+               pr_err("failed to map apbc registers\n");
+               return;
+       }
+
+       pxa_unit->apbcp_base = of_iomap(np, 3);
+       if (!pxa_unit->mpmu_base) {
+               pr_err("failed to map apbcp registers\n");
+               return;
+       }
+
+       mmp_clk_init(np, &pxa_unit->unit, PXA910_NR_CLKS);
+
+       pxa910_pll_init(pxa_unit);
+
+       pxa910_apb_periph_clk_init(pxa_unit);
+
+       pxa910_axi_periph_clk_init(pxa_unit);
+
+       pxa910_clk_reset_init(np, pxa_unit);
+}
+
+CLK_OF_DECLARE(pxa910_clk, "marvell,pxa910-clock", pxa910_clk_init);
index 014396b028a2c8c137723ccf2063f2dba6404f02..93e967c0f972f954ef1f7af9bb2f90e0c3241cae 100644 (file)
@@ -47,7 +47,7 @@
 
 static DEFINE_SPINLOCK(clk_lock);
 
-static struct clk_factor_masks uart_factor_masks = {
+static struct mmp_clk_factor_masks uart_factor_masks = {
        .factor = 2,
        .num_mask = 0x1fff,
        .den_mask = 0x1fff,
@@ -55,7 +55,7 @@ static struct clk_factor_masks uart_factor_masks = {
        .den_shift = 0,
 };
 
-static struct clk_factor_tbl uart_factor_tbl[] = {
+static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
        {.num = 8125, .den = 1536},     /*14.745MHZ */
 };
 
@@ -158,7 +158,7 @@ void __init pxa168_clk_init(void)
        uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
                                mpmu_base + MPMU_UART_PLL,
                                &uart_factor_masks, uart_factor_tbl,
-                               ARRAY_SIZE(uart_factor_tbl));
+                               ARRAY_SIZE(uart_factor_tbl), &clk_lock);
        clk_set_rate(uart_pll, 14745600);
        clk_register_clkdev(uart_pll, "uart_pll", NULL);
 
index 9efc6a47535d3bf07747e3373078daef8162794a..993abcdb32cce825fdb1d2ea835cb69f3ecf94fc 100644 (file)
@@ -45,7 +45,7 @@
 
 static DEFINE_SPINLOCK(clk_lock);
 
-static struct clk_factor_masks uart_factor_masks = {
+static struct mmp_clk_factor_masks uart_factor_masks = {
        .factor = 2,
        .num_mask = 0x1fff,
        .den_mask = 0x1fff,
@@ -53,7 +53,7 @@ static struct clk_factor_masks uart_factor_masks = {
        .den_shift = 0,
 };
 
-static struct clk_factor_tbl uart_factor_tbl[] = {
+static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
        {.num = 8125, .den = 1536},     /*14.745MHZ */
 };
 
@@ -163,7 +163,7 @@ void __init pxa910_clk_init(void)
        uart_pll =  mmp_clk_register_factor("uart_pll", "pll1_4", 0,
                                mpmu_base + MPMU_UART_PLL,
                                &uart_factor_masks, uart_factor_tbl,
-                               ARRAY_SIZE(uart_factor_tbl));
+                               ARRAY_SIZE(uart_factor_tbl), &clk_lock);
        clk_set_rate(uart_pll, 14745600);
        clk_register_clkdev(uart_pll, "uart_pll", NULL);
 
diff --git a/drivers/clk/mmp/clk.c b/drivers/clk/mmp/clk.c
new file mode 100644 (file)
index 0000000..cf038ef
--- /dev/null
@@ -0,0 +1,192 @@
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include "clk.h"
+
+void mmp_clk_init(struct device_node *np, struct mmp_clk_unit *unit,
+               int nr_clks)
+{
+       static struct clk **clk_table;
+
+       clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
+       if (!clk_table)
+               return;
+
+       unit->clk_table = clk_table;
+       unit->nr_clks = nr_clks;
+       unit->clk_data.clks = clk_table;
+       unit->clk_data.clk_num = nr_clks;
+       of_clk_add_provider(np, of_clk_src_onecell_get, &unit->clk_data);
+}
+
+void mmp_register_fixed_rate_clks(struct mmp_clk_unit *unit,
+                               struct mmp_param_fixed_rate_clk *clks,
+                               int size)
+{
+       int i;
+       struct clk *clk;
+
+       for (i = 0; i < size; i++) {
+               clk = clk_register_fixed_rate(NULL, clks[i].name,
+                                       clks[i].parent_name,
+                                       clks[i].flags,
+                                       clks[i].fixed_rate);
+               if (IS_ERR(clk)) {
+                       pr_err("%s: failed to register clock %s\n",
+                              __func__, clks[i].name);
+                       continue;
+               }
+               if (clks[i].id)
+                       unit->clk_table[clks[i].id] = clk;
+       }
+}
+
+void mmp_register_fixed_factor_clks(struct mmp_clk_unit *unit,
+                               struct mmp_param_fixed_factor_clk *clks,
+                               int size)
+{
+       struct clk *clk;
+       int i;
+
+       for (i = 0; i < size; i++) {
+               clk = clk_register_fixed_factor(NULL, clks[i].name,
+                                               clks[i].parent_name,
+                                               clks[i].flags, clks[i].mult,
+                                               clks[i].div);
+               if (IS_ERR(clk)) {
+                       pr_err("%s: failed to register clock %s\n",
+                              __func__, clks[i].name);
+                       continue;
+               }
+               if (clks[i].id)
+                       unit->clk_table[clks[i].id] = clk;
+       }
+}
+
+void mmp_register_general_gate_clks(struct mmp_clk_unit *unit,
+                               struct mmp_param_general_gate_clk *clks,
+                               void __iomem *base, int size)
+{
+       struct clk *clk;
+       int i;
+
+       for (i = 0; i < size; i++) {
+               clk = clk_register_gate(NULL, clks[i].name,
+                                       clks[i].parent_name,
+                                       clks[i].flags,
+                                       base + clks[i].offset,
+                                       clks[i].bit_idx,
+                                       clks[i].gate_flags,
+                                       clks[i].lock);
+
+               if (IS_ERR(clk)) {
+                       pr_err("%s: failed to register clock %s\n",
+                              __func__, clks[i].name);
+                       continue;
+               }
+               if (clks[i].id)
+                       unit->clk_table[clks[i].id] = clk;
+       }
+}
+
+void mmp_register_gate_clks(struct mmp_clk_unit *unit,
+                       struct mmp_param_gate_clk *clks,
+                       void __iomem *base, int size)
+{
+       struct clk *clk;
+       int i;
+
+       for (i = 0; i < size; i++) {
+               clk = mmp_clk_register_gate(NULL, clks[i].name,
+                                       clks[i].parent_name,
+                                       clks[i].flags,
+                                       base + clks[i].offset,
+                                       clks[i].mask,
+                                       clks[i].val_enable,
+                                       clks[i].val_disable,
+                                       clks[i].gate_flags,
+                                       clks[i].lock);
+
+               if (IS_ERR(clk)) {
+                       pr_err("%s: failed to register clock %s\n",
+                              __func__, clks[i].name);
+                       continue;
+               }
+               if (clks[i].id)
+                       unit->clk_table[clks[i].id] = clk;
+       }
+}
+
+void mmp_register_mux_clks(struct mmp_clk_unit *unit,
+                       struct mmp_param_mux_clk *clks,
+                       void __iomem *base, int size)
+{
+       struct clk *clk;
+       int i;
+
+       for (i = 0; i < size; i++) {
+               clk = clk_register_mux(NULL, clks[i].name,
+                                       clks[i].parent_name,
+                                       clks[i].num_parents,
+                                       clks[i].flags,
+                                       base + clks[i].offset,
+                                       clks[i].shift,
+                                       clks[i].width,
+                                       clks[i].mux_flags,
+                                       clks[i].lock);
+
+               if (IS_ERR(clk)) {
+                       pr_err("%s: failed to register clock %s\n",
+                              __func__, clks[i].name);
+                       continue;
+               }
+               if (clks[i].id)
+                       unit->clk_table[clks[i].id] = clk;
+       }
+}
+
+void mmp_register_div_clks(struct mmp_clk_unit *unit,
+                       struct mmp_param_div_clk *clks,
+                       void __iomem *base, int size)
+{
+       struct clk *clk;
+       int i;
+
+       for (i = 0; i < size; i++) {
+               clk = clk_register_divider(NULL, clks[i].name,
+                                       clks[i].parent_name,
+                                       clks[i].flags,
+                                       base + clks[i].offset,
+                                       clks[i].shift,
+                                       clks[i].width,
+                                       clks[i].div_flags,
+                                       clks[i].lock);
+
+               if (IS_ERR(clk)) {
+                       pr_err("%s: failed to register clock %s\n",
+                              __func__, clks[i].name);
+                       continue;
+               }
+               if (clks[i].id)
+                       unit->clk_table[clks[i].id] = clk;
+       }
+}
+
+void mmp_clk_add(struct mmp_clk_unit *unit, unsigned int id,
+                       struct clk *clk)
+{
+       if (IS_ERR_OR_NULL(clk)) {
+               pr_err("CLK %d has invalid pointer %p\n", id, clk);
+               return;
+       }
+       if (id > unit->nr_clks) {
+               pr_err("CLK %d is invalid\n", id);
+               return;
+       }
+
+       unit->clk_table[id] = clk;
+}
index ab86dd4a416a5fa6b75aa74d7588894e7b8c4c2e..adf9b711b03702e61c989b315124b66aafa6c07a 100644 (file)
 #define APBC_NO_BUS_CTRL       BIT(0)
 #define APBC_POWER_CTRL                BIT(1)
 
-struct clk_factor_masks {
-       unsigned int    factor;
-       unsigned int    num_mask;
-       unsigned int    den_mask;
-       unsigned int    num_shift;
-       unsigned int    den_shift;
+
+/* Clock type "factor" */
+struct mmp_clk_factor_masks {
+       unsigned int factor;
+       unsigned int num_mask;
+       unsigned int den_mask;
+       unsigned int num_shift;
+       unsigned int den_shift;
 };
 
-struct clk_factor_tbl {
+struct mmp_clk_factor_tbl {
        unsigned int num;
        unsigned int den;
 };
 
+struct mmp_clk_factor {
+       struct clk_hw hw;
+       void __iomem *base;
+       struct mmp_clk_factor_masks *masks;
+       struct mmp_clk_factor_tbl *ftbl;
+       unsigned int ftbl_cnt;
+       spinlock_t *lock;
+};
+
+extern struct clk *mmp_clk_register_factor(const char *name,
+               const char *parent_name, unsigned long flags,
+               void __iomem *base, struct mmp_clk_factor_masks *masks,
+               struct mmp_clk_factor_tbl *ftbl, unsigned int ftbl_cnt,
+               spinlock_t *lock);
+
+/* Clock type "mix" */
+#define MMP_CLK_BITS_MASK(width, shift)                        \
+               (((1 << (width)) - 1) << (shift))
+#define MMP_CLK_BITS_GET_VAL(data, width, shift)       \
+               ((data & MMP_CLK_BITS_MASK(width, shift)) >> (shift))
+#define MMP_CLK_BITS_SET_VAL(val, width, shift)                \
+               (((val) << (shift)) & MMP_CLK_BITS_MASK(width, shift))
+
+enum {
+       MMP_CLK_MIX_TYPE_V1,
+       MMP_CLK_MIX_TYPE_V2,
+       MMP_CLK_MIX_TYPE_V3,
+};
+
+/* The register layout */
+struct mmp_clk_mix_reg_info {
+       void __iomem *reg_clk_ctrl;
+       void __iomem *reg_clk_sel;
+       u8 width_div;
+       u8 shift_div;
+       u8 width_mux;
+       u8 shift_mux;
+       u8 bit_fc;
+};
+
+/* The suggested clock table from user. */
+struct mmp_clk_mix_clk_table {
+       unsigned long rate;
+       u8 parent_index;
+       unsigned int divisor;
+       unsigned int valid;
+};
+
+struct mmp_clk_mix_config {
+       struct mmp_clk_mix_reg_info reg_info;
+       struct mmp_clk_mix_clk_table *table;
+       unsigned int table_size;
+       u32 *mux_table;
+       struct clk_div_table *div_table;
+       u8 div_flags;
+       u8 mux_flags;
+};
+
+struct mmp_clk_mix {
+       struct clk_hw hw;
+       struct mmp_clk_mix_reg_info reg_info;
+       struct mmp_clk_mix_clk_table *table;
+       u32 *mux_table;
+       struct clk_div_table *div_table;
+       unsigned int table_size;
+       u8 div_flags;
+       u8 mux_flags;
+       unsigned int type;
+       spinlock_t *lock;
+};
+
+extern const struct clk_ops mmp_clk_mix_ops;
+extern struct clk *mmp_clk_register_mix(struct device *dev,
+                                       const char *name,
+                                       const char **parent_names,
+                                       u8 num_parents,
+                                       unsigned long flags,
+                                       struct mmp_clk_mix_config *config,
+                                       spinlock_t *lock);
+
+
+/* Clock type "gate". MMP private gate */
+#define MMP_CLK_GATE_NEED_DELAY                BIT(0)
+
+struct mmp_clk_gate {
+       struct clk_hw hw;
+       void __iomem *reg;
+       u32 mask;
+       u32 val_enable;
+       u32 val_disable;
+       unsigned int flags;
+       spinlock_t *lock;
+};
+
+extern const struct clk_ops mmp_clk_gate_ops;
+extern struct clk *mmp_clk_register_gate(struct device *dev, const char *name,
+                       const char *parent_name, unsigned long flags,
+                       void __iomem *reg, u32 mask, u32 val_enable,
+                       u32 val_disable, unsigned int gate_flags,
+                       spinlock_t *lock);
+
+
 extern struct clk *mmp_clk_register_pll2(const char *name,
                const char *parent_name, unsigned long flags);
 extern struct clk *mmp_clk_register_apbc(const char *name,
@@ -28,8 +132,108 @@ extern struct clk *mmp_clk_register_apbc(const char *name,
 extern struct clk *mmp_clk_register_apmu(const char *name,
                const char *parent_name, void __iomem *base, u32 enable_mask,
                spinlock_t *lock);
-extern struct clk *mmp_clk_register_factor(const char *name,
-               const char *parent_name, unsigned long flags,
-               void __iomem *base, struct clk_factor_masks *masks,
-               struct clk_factor_tbl *ftbl, unsigned int ftbl_cnt);
+
+struct mmp_clk_unit {
+       unsigned int nr_clks;
+       struct clk **clk_table;
+       struct clk_onecell_data clk_data;
+};
+
+struct mmp_param_fixed_rate_clk {
+       unsigned int id;
+       char *name;
+       const char *parent_name;
+       unsigned long flags;
+       unsigned long fixed_rate;
+};
+void mmp_register_fixed_rate_clks(struct mmp_clk_unit *unit,
+                               struct mmp_param_fixed_rate_clk *clks,
+                               int size);
+
+struct mmp_param_fixed_factor_clk {
+       unsigned int id;
+       char *name;
+       const char *parent_name;
+       unsigned long mult;
+       unsigned long div;
+       unsigned long flags;
+};
+void mmp_register_fixed_factor_clks(struct mmp_clk_unit *unit,
+                               struct mmp_param_fixed_factor_clk *clks,
+                               int size);
+
+struct mmp_param_general_gate_clk {
+       unsigned int id;
+       const char *name;
+       const char *parent_name;
+       unsigned long flags;
+       unsigned long offset;
+       u8 bit_idx;
+       u8 gate_flags;
+       spinlock_t *lock;
+};
+void mmp_register_general_gate_clks(struct mmp_clk_unit *unit,
+                               struct mmp_param_general_gate_clk *clks,
+                               void __iomem *base, int size);
+
+struct mmp_param_gate_clk {
+       unsigned int id;
+       char *name;
+       const char *parent_name;
+       unsigned long flags;
+       unsigned long offset;
+       u32 mask;
+       u32 val_enable;
+       u32 val_disable;
+       unsigned int gate_flags;
+       spinlock_t *lock;
+};
+void mmp_register_gate_clks(struct mmp_clk_unit *unit,
+                       struct mmp_param_gate_clk *clks,
+                       void __iomem *base, int size);
+
+struct mmp_param_mux_clk {
+       unsigned int id;
+       char *name;
+       const char **parent_name;
+       u8 num_parents;
+       unsigned long flags;
+       unsigned long offset;
+       u8 shift;
+       u8 width;
+       u8 mux_flags;
+       spinlock_t *lock;
+};
+void mmp_register_mux_clks(struct mmp_clk_unit *unit,
+                       struct mmp_param_mux_clk *clks,
+                       void __iomem *base, int size);
+
+struct mmp_param_div_clk {
+       unsigned int id;
+       char *name;
+       const char *parent_name;
+       unsigned long flags;
+       unsigned long offset;
+       u8 shift;
+       u8 width;
+       u8 div_flags;
+       spinlock_t *lock;
+};
+void mmp_register_div_clks(struct mmp_clk_unit *unit,
+                       struct mmp_param_div_clk *clks,
+                       void __iomem *base, int size);
+
+#define DEFINE_MIX_REG_INFO(w_d, s_d, w_m, s_m, fc)    \
+{                                                      \
+       .width_div = (w_d),                             \
+       .shift_div = (s_d),                             \
+       .width_mux = (w_m),                             \
+       .shift_mux = (s_m),                             \
+       .bit_fc = (fc),                                 \
+}
+
+void mmp_clk_init(struct device_node *np, struct mmp_clk_unit *unit,
+               int nr_clks);
+void mmp_clk_add(struct mmp_clk_unit *unit, unsigned int id,
+               struct clk *clk);
 #endif
diff --git a/drivers/clk/mmp/reset.c b/drivers/clk/mmp/reset.c
new file mode 100644 (file)
index 0000000..b54da1f
--- /dev/null
@@ -0,0 +1,99 @@
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/reset-controller.h>
+
+#include "reset.h"
+
+#define rcdev_to_unit(rcdev) container_of(rcdev, struct mmp_clk_reset_unit, rcdev)
+
+static int mmp_of_reset_xlate(struct reset_controller_dev *rcdev,
+                         const struct of_phandle_args *reset_spec)
+{
+       struct mmp_clk_reset_unit *unit = rcdev_to_unit(rcdev);
+       struct mmp_clk_reset_cell *cell;
+       int i;
+
+       if (WARN_ON(reset_spec->args_count != rcdev->of_reset_n_cells))
+               return -EINVAL;
+
+       for (i = 0; i < rcdev->nr_resets; i++) {
+               cell = &unit->cells[i];
+               if (cell->clk_id == reset_spec->args[0])
+                       break;
+       }
+
+       if (i == rcdev->nr_resets)
+               return -EINVAL;
+
+       return i;
+}
+
+static int mmp_clk_reset_assert(struct reset_controller_dev *rcdev,
+                               unsigned long id)
+{
+       struct mmp_clk_reset_unit *unit = rcdev_to_unit(rcdev);
+       struct mmp_clk_reset_cell *cell;
+       unsigned long flags = 0;
+       u32 val;
+
+       cell = &unit->cells[id];
+       if (cell->lock)
+               spin_lock_irqsave(cell->lock, flags);
+
+       val = readl(cell->reg);
+       val |= cell->bits;
+       writel(val, cell->reg);
+
+       if (cell->lock)
+               spin_unlock_irqrestore(cell->lock, flags);
+
+       return 0;
+}
+
+static int mmp_clk_reset_deassert(struct reset_controller_dev *rcdev,
+                               unsigned long id)
+{
+       struct mmp_clk_reset_unit *unit = rcdev_to_unit(rcdev);
+       struct mmp_clk_reset_cell *cell;
+       unsigned long flags = 0;
+       u32 val;
+
+       cell = &unit->cells[id];
+       if (cell->lock)
+               spin_lock_irqsave(cell->lock, flags);
+
+       val = readl(cell->reg);
+       val &= ~cell->bits;
+       writel(val, cell->reg);
+
+       if (cell->lock)
+               spin_unlock_irqrestore(cell->lock, flags);
+
+       return 0;
+}
+
+static struct reset_control_ops mmp_clk_reset_ops = {
+       .assert         = mmp_clk_reset_assert,
+       .deassert       = mmp_clk_reset_deassert,
+};
+
+void mmp_clk_reset_register(struct device_node *np,
+                       struct mmp_clk_reset_cell *cells, int nr_resets)
+{
+       struct mmp_clk_reset_unit *unit;
+
+       unit = kzalloc(sizeof(*unit), GFP_KERNEL);
+       if (!unit)
+               return;
+
+       unit->cells = cells;
+       unit->rcdev.of_reset_n_cells = 1;
+       unit->rcdev.nr_resets = nr_resets;
+       unit->rcdev.ops = &mmp_clk_reset_ops;
+       unit->rcdev.of_node = np;
+       unit->rcdev.of_xlate = mmp_of_reset_xlate;
+
+       reset_controller_register(&unit->rcdev);
+}
diff --git a/drivers/clk/mmp/reset.h b/drivers/clk/mmp/reset.h
new file mode 100644 (file)
index 0000000..be8b1a7
--- /dev/null
@@ -0,0 +1,31 @@
+#ifndef __MACH_MMP_CLK_RESET_H
+#define __MACH_MMP_CLK_RESET_H
+
+#include <linux/reset-controller.h>
+
+#define MMP_RESET_INVERT       1
+
+struct mmp_clk_reset_cell {
+       unsigned int clk_id;
+       void __iomem *reg;
+       u32 bits;
+       unsigned int flags;
+       spinlock_t *lock;
+};
+
+struct mmp_clk_reset_unit {
+       struct reset_controller_dev rcdev;
+       struct mmp_clk_reset_cell *cells;
+};
+
+#ifdef CONFIG_RESET_CONTROLLER
+void mmp_clk_reset_register(struct device_node *np,
+                       struct mmp_clk_reset_cell *cells, int nr_resets);
+#else
+static inline void mmp_clk_reset_register(struct device_node *np,
+                       struct mmp_clk_reset_cell *cells, int nr_resets)
+{
+}
+#endif
+
+#endif
index 4ff2abcd500b8e2109241b56152eeef6dd46f0e0..38e9153446059a1fb0c0728c841517cf99747f40 100644 (file)
@@ -1,2 +1,3 @@
 obj-y                          += clk-pxa.o
+obj-$(CONFIG_PXA25x)           += clk-pxa25x.o
 obj-$(CONFIG_PXA27x)           += clk-pxa27x.o
index ef3c05389c0aeb4704a6f2c2e23720eda6311a83..4e834753ab094500677811702c37ad005503929b 100644 (file)
@@ -26,12 +26,20 @@ static struct clk_onecell_data onecell_data = {
        .clk_num = CLK_MAX,
 };
 
-#define to_pxa_clk(_hw) container_of(_hw, struct pxa_clk_cken, hw)
+struct pxa_clk {
+       struct clk_hw hw;
+       struct clk_fixed_factor lp;
+       struct clk_fixed_factor hp;
+       struct clk_gate gate;
+       bool (*is_in_low_power)(void);
+};
+
+#define to_pxa_clk(_hw) container_of(_hw, struct pxa_clk, hw)
 
 static unsigned long cken_recalc_rate(struct clk_hw *hw,
                                      unsigned long parent_rate)
 {
-       struct pxa_clk_cken *pclk = to_pxa_clk(hw);
+       struct pxa_clk *pclk = to_pxa_clk(hw);
        struct clk_fixed_factor *fix;
 
        if (!pclk->is_in_low_power || pclk->is_in_low_power())
@@ -48,7 +56,7 @@ static struct clk_ops cken_rate_ops = {
 
 static u8 cken_get_parent(struct clk_hw *hw)
 {
-       struct pxa_clk_cken *pclk = to_pxa_clk(hw);
+       struct pxa_clk *pclk = to_pxa_clk(hw);
 
        if (!pclk->is_in_low_power)
                return 0;
@@ -69,29 +77,32 @@ void __init clkdev_pxa_register(int ckid, const char *con_id,
                clk_register_clkdev(clk, con_id, dev_id);
 }
 
-int __init clk_pxa_cken_init(struct pxa_clk_cken *clks, int nb_clks)
+int __init clk_pxa_cken_init(const struct desc_clk_cken *clks, int nb_clks)
 {
        int i;
-       struct pxa_clk_cken *pclk;
+       struct pxa_clk *pxa_clk;
        struct clk *clk;
 
        for (i = 0; i < nb_clks; i++) {
-               pclk = clks + i;
-               pclk->gate.lock = &lock;
-               clk = clk_register_composite(NULL, pclk->name,
-                                            pclk->parent_names, 2,
-                                            &pclk->hw, &cken_mux_ops,
-                                            &pclk->hw, &cken_rate_ops,
-                                            &pclk->gate.hw, &clk_gate_ops,
-                                            pclk->flags);
-               clkdev_pxa_register(pclk->ckid, pclk->con_id, pclk->dev_id,
-                                   clk);
+               pxa_clk = kzalloc(sizeof(*pxa_clk), GFP_KERNEL);
+               pxa_clk->is_in_low_power = clks[i].is_in_low_power;
+               pxa_clk->lp = clks[i].lp;
+               pxa_clk->hp = clks[i].hp;
+               pxa_clk->gate = clks[i].gate;
+               pxa_clk->gate.lock = &lock;
+               clk = clk_register_composite(NULL, clks[i].name,
+                                            clks[i].parent_names, 2,
+                                            &pxa_clk->hw, &cken_mux_ops,
+                                            &pxa_clk->hw, &cken_rate_ops,
+                                            &pxa_clk->gate.hw, &clk_gate_ops,
+                                            clks[i].flags);
+               clkdev_pxa_register(clks[i].ckid, clks[i].con_id,
+                                   clks[i].dev_id, clk);
        }
        return 0;
 }
 
-static void __init pxa_dt_clocks_init(struct device_node *np)
+void __init clk_pxa_dt_common_init(struct device_node *np)
 {
        of_clk_add_provider(np, of_clk_src_onecell_get, &onecell_data);
 }
-CLK_OF_DECLARE(pxa_clks, "marvell,pxa-clocks", pxa_dt_clocks_init);
index 5fe219d06b490c49a7203dd547fe65b537089c73..323965430111943b33dad32b3e8d5a889c7dead2 100644 (file)
@@ -25,7 +25,7 @@
        static struct clk_ops name ## _rate_ops = {             \
                .recalc_rate = name ## _get_rate,               \
        };                                                      \
-       static struct clk *clk_register_ ## name(void)          \
+       static struct clk * __init clk_register_ ## name(void)  \
        {                                                       \
                return clk_register_composite(NULL, clk_name,   \
                        name ## _parents,                       \
@@ -40,7 +40,7 @@
        static struct clk_ops name ## _rate_ops = {             \
                .recalc_rate = name ## _get_rate,               \
        };                                                      \
-       static struct clk *clk_register_ ## name(void)          \
+       static struct clk * __init clk_register_ ## name(void)  \
        {                                                       \
                return clk_register_composite(NULL, clk_name,   \
                        name ## _parents,                       \
@@ -66,7 +66,7 @@
  *  |    Clock   | --- | / div_hp  |
  *  +------------+     +-----------+
  */
-struct pxa_clk_cken {
+struct desc_clk_cken {
        struct clk_hw hw;
        int ckid;
        const char *name;
@@ -102,6 +102,7 @@ static int dummy_clk_set_parent(struct clk_hw *hw, u8 index)
 
 extern void clkdev_pxa_register(int ckid, const char *con_id,
                                const char *dev_id, struct clk *clk);
-extern int clk_pxa_cken_init(struct pxa_clk_cken *clks, int nb_clks);
+extern int clk_pxa_cken_init(const struct desc_clk_cken *clks, int nb_clks);
+void clk_pxa_dt_common_init(struct device_node *np);
 
 #endif
diff --git a/drivers/clk/pxa/clk-pxa25x.c b/drivers/clk/pxa/clk-pxa25x.c
new file mode 100644 (file)
index 0000000..6cd88d9
--- /dev/null
@@ -0,0 +1,273 @@
+/*
+ * Marvell PXA25x family clocks
+ *
+ * Copyright (C) 2014 Robert Jarzmik
+ *
+ * Heavily inspired from former arch/arm/mach-pxa/pxa25x.c.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * For non-devicetree platforms. Once pxa is fully converted to devicetree, this
+ * should go away.
+ */
+#include <linux/clk-provider.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <mach/pxa25x.h>
+#include <mach/pxa2xx-regs.h>
+
+#include <dt-bindings/clock/pxa-clock.h>
+#include "clk-pxa.h"
+
+#define KHz 1000
+#define MHz (1000 * 1000)
+
+enum {
+       PXA_CORE_RUN = 0,
+       PXA_CORE_TURBO,
+};
+
+/*
+ * Various clock factors driven by the CCCR register.
+ */
+
+/* Crystal Frequency to Memory Frequency Multiplier (L) */
+static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
+
+/* Memory Frequency to Run Mode Frequency Multiplier (M) */
+static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
+
+/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
+/* Note: we store the value N * 2 here. */
+static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
+
+static const char * const get_freq_khz[] = {
+       "core", "run", "cpll", "memory"
+};
+
+/*
+ * Get the clock frequency as reflected by CCCR and the turbo flag.
+ * We assume these values have been applied via a fcs.
+ * If info is not 0 we also display the current settings.
+ */
+unsigned int pxa25x_get_clk_frequency_khz(int info)
+{
+       struct clk *clk;
+       unsigned long clks[5];
+       int i;
+
+       for (i = 0; i < ARRAY_SIZE(get_freq_khz); i++) {
+               clk = clk_get(NULL, get_freq_khz[i]);
+               if (IS_ERR(clk)) {
+                       clks[i] = 0;
+               } else {
+                       clks[i] = clk_get_rate(clk);
+                       clk_put(clk);
+               }
+       }
+
+       if (info) {
+               pr_info("Run Mode clock: %ld.%02ldMHz\n",
+                       clks[1] / 1000000, (clks[1] % 1000000) / 10000);
+               pr_info("Turbo Mode clock: %ld.%02ldMHz\n",
+                       clks[2] / 1000000, (clks[2] % 1000000) / 10000);
+               pr_info("Memory clock: %ld.%02ldMHz\n",
+                       clks[3] / 1000000, (clks[3] % 1000000) / 10000);
+       }
+
+       return (unsigned int)clks[0];
+}
+
+static unsigned long clk_pxa25x_memory_get_rate(struct clk_hw *hw,
+                                               unsigned long parent_rate)
+{
+       unsigned long cccr = CCCR;
+       unsigned int m = M_clk_mult[(cccr >> 5) & 0x03];
+
+       return parent_rate / m;
+}
+PARENTS(clk_pxa25x_memory) = { "run" };
+RATE_RO_OPS(clk_pxa25x_memory, "memory");
+
+PARENTS(pxa25x_pbus95) = { "ppll_95_85mhz", "ppll_95_85mhz" };
+PARENTS(pxa25x_pbus147) = { "ppll_147_46mhz", "ppll_147_46mhz" };
+PARENTS(pxa25x_osc3) = { "osc_3_6864mhz", "osc_3_6864mhz" };
+
+#define PXA25X_CKEN(dev_id, con_id, parents, mult, div,                        \
+                   bit, is_lp, flags)                                  \
+       PXA_CKEN(dev_id, con_id, bit, parents, mult, div, mult, div,    \
+                is_lp,  &CKEN, CKEN_ ## bit, flags)
+#define PXA25X_PBUS95_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay)        \
+       PXA25X_CKEN(dev_id, con_id, pxa25x_pbus95_parents, mult_hp,     \
+                   div_hp, bit, NULL, 0)
+#define PXA25X_PBUS147_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay)\
+       PXA25X_CKEN(dev_id, con_id, pxa25x_pbus147_parents, mult_hp,    \
+                   div_hp, bit, NULL, 0)
+#define PXA25X_OSC3_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay)  \
+       PXA25X_CKEN(dev_id, con_id, pxa25x_osc3_parents, mult_hp,       \
+                   div_hp, bit, NULL, 0)
+
+#define PXA25X_CKEN_1RATE(dev_id, con_id, bit, parents, delay)         \
+       PXA_CKEN_1RATE(dev_id, con_id, bit, parents,                    \
+                      &CKEN, CKEN_ ## bit, 0)
+#define PXA25X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay)      \
+       PXA_CKEN_1RATE(dev_id, con_id, bit, parents,                    \
+                      &CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED)
+
+static struct desc_clk_cken pxa25x_clocks[] __initdata = {
+       PXA25X_PBUS95_CKEN("pxa2xx-mci.0", NULL, MMC, 1, 5, 0),
+       PXA25X_PBUS95_CKEN("pxa2xx-i2c.0", NULL, I2C, 1, 3, 0),
+       PXA25X_PBUS95_CKEN("pxa2xx-ir", "FICPCLK", FICP, 1, 2, 0),
+       PXA25X_PBUS95_CKEN("pxa25x-udc", NULL, USB, 1, 2, 5),
+       PXA25X_PBUS147_CKEN("pxa2xx-uart.0", NULL, FFUART, 1, 10, 1),
+       PXA25X_PBUS147_CKEN("pxa2xx-uart.1", NULL, BTUART, 1, 10, 1),
+       PXA25X_PBUS147_CKEN("pxa2xx-uart.2", NULL, STUART, 1, 10, 1),
+       PXA25X_PBUS147_CKEN("pxa2xx-uart.3", NULL, HWUART, 1, 10, 1),
+       PXA25X_PBUS147_CKEN("pxa2xx-i2s", NULL, I2S, 1, 10, 0),
+       PXA25X_PBUS147_CKEN(NULL, "AC97CLK", AC97, 1, 12, 0),
+       PXA25X_OSC3_CKEN("pxa25x-ssp.0", NULL, SSP, 1, 1, 0),
+       PXA25X_OSC3_CKEN("pxa25x-nssp.1", NULL, NSSP, 1, 1, 0),
+       PXA25X_OSC3_CKEN("pxa25x-nssp.2", NULL, ASSP, 1, 1, 0),
+       PXA25X_OSC3_CKEN("pxa25x-pwm.0", NULL, PWM0, 1, 1, 0),
+       PXA25X_OSC3_CKEN("pxa25x-pwm.1", NULL, PWM1, 1, 1, 0),
+
+       PXA25X_CKEN_1RATE("pxa2xx-fb", NULL, LCD, clk_pxa25x_memory_parents, 0),
+       PXA25X_CKEN_1RATE_AO("pxa2xx-pcmcia", NULL, MEMC,
+                            clk_pxa25x_memory_parents, 0),
+};
+
+static u8 clk_pxa25x_core_get_parent(struct clk_hw *hw)
+{
+       unsigned long clkcfg;
+       unsigned int t;
+
+       asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
+       t  = clkcfg & (1 << 0);
+       if (t)
+               return PXA_CORE_TURBO;
+       return PXA_CORE_RUN;
+}
+
+static unsigned long clk_pxa25x_core_get_rate(struct clk_hw *hw,
+                                             unsigned long parent_rate)
+{
+       return parent_rate;
+}
+PARENTS(clk_pxa25x_core) = { "run", "cpll" };
+MUX_RO_RATE_RO_OPS(clk_pxa25x_core, "core");
+
+static unsigned long clk_pxa25x_run_get_rate(struct clk_hw *hw,
+                                            unsigned long parent_rate)
+{
+       unsigned long cccr = CCCR;
+       unsigned int n2 = N2_clk_mult[(cccr >> 7) & 0x07];
+
+       return (parent_rate / n2) * 2;
+}
+PARENTS(clk_pxa25x_run) = { "cpll" };
+RATE_RO_OPS(clk_pxa25x_run, "run");
+
+static unsigned long clk_pxa25x_cpll_get_rate(struct clk_hw *hw,
+       unsigned long parent_rate)
+{
+       unsigned long clkcfg, cccr = CCCR;
+       unsigned int l, m, n2, t;
+
+       asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
+       t = clkcfg & (1 << 0);
+       l  =  L_clk_mult[(cccr >> 0) & 0x1f];
+       m = M_clk_mult[(cccr >> 5) & 0x03];
+       n2 = N2_clk_mult[(cccr >> 7) & 0x07];
+
+       if (t)
+               return m * l * n2 * parent_rate / 2;
+       return m * l * parent_rate;
+}
+PARENTS(clk_pxa25x_cpll) = { "osc_3_6864mhz" };
+RATE_RO_OPS(clk_pxa25x_cpll, "cpll");
+
+static void __init pxa25x_register_core(void)
+{
+       clk_register_clk_pxa25x_cpll();
+       clk_register_clk_pxa25x_run();
+       clkdev_pxa_register(CLK_CORE, "core", NULL,
+                           clk_register_clk_pxa25x_core());
+}
+
+static void __init pxa25x_register_plls(void)
+{
+       clk_register_fixed_rate(NULL, "osc_3_6864mhz", NULL,
+                               CLK_GET_RATE_NOCACHE | CLK_IS_ROOT,
+                               3686400);
+       clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
+                               CLK_GET_RATE_NOCACHE | CLK_IS_ROOT,
+                               32768);
+       clk_register_fixed_rate(NULL, "clk_dummy", NULL, CLK_IS_ROOT, 0);
+       clk_register_fixed_factor(NULL, "ppll_95_85mhz", "osc_3_6864mhz",
+                                 0, 26, 1);
+       clk_register_fixed_factor(NULL, "ppll_147_46mhz", "osc_3_6864mhz",
+                                 0, 40, 1);
+}
+
+static void __init pxa25x_base_clocks_init(void)
+{
+       pxa25x_register_plls();
+       pxa25x_register_core();
+       clk_register_clk_pxa25x_memory();
+}
+
+#define DUMMY_CLK(_con_id, _dev_id, _parent) \
+       { .con_id = _con_id, .dev_id = _dev_id, .parent = _parent }
+struct dummy_clk {
+       const char *con_id;
+       const char *dev_id;
+       const char *parent;
+};
+static struct dummy_clk dummy_clks[] __initdata = {
+       DUMMY_CLK(NULL, "pxa25x-gpio", "osc_32_768khz"),
+       DUMMY_CLK(NULL, "pxa26x-gpio", "osc_32_768khz"),
+       DUMMY_CLK("GPIO11_CLK", NULL, "osc_3_6864mhz"),
+       DUMMY_CLK("GPIO12_CLK", NULL, "osc_32_768khz"),
+       DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
+       DUMMY_CLK("OSTIMER0", NULL, "osc_32_768khz"),
+       DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
+};
+
+static void __init pxa25x_dummy_clocks_init(void)
+{
+       struct clk *clk;
+       struct dummy_clk *d;
+       const char *name;
+       int i;
+
+       /*
+        * All pinctrl logic has been wiped out of the clock driver, especially
+        * for gpio11 and gpio12 outputs. Machine code should ensure proper pin
+        * control (ie. pxa2xx_mfp_config() invocation).
+        */
+       for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) {
+               d = &dummy_clks[i];
+               name = d->dev_id ? d->dev_id : d->con_id;
+               clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
+               clk_register_clkdev(clk, d->con_id, d->dev_id);
+       }
+}
+
+int __init pxa25x_clocks_init(void)
+{
+       pxa25x_base_clocks_init();
+       pxa25x_dummy_clocks_init();
+       return clk_pxa_cken_init(pxa25x_clocks, ARRAY_SIZE(pxa25x_clocks));
+}
+
+static void __init pxa25x_dt_clocks_init(struct device_node *np)
+{
+       pxa25x_clocks_init();
+       clk_pxa_dt_common_init(np);
+}
+CLK_OF_DECLARE(pxa25x_clks, "marvell,pxa250-core-clocks",
+              pxa25x_dt_clocks_init);
index 88b9fe13fa444b2a81a3bd8a2588b035357d0048..5f9b54b024b9e1607b724c8ceb5dcfba7b58c992 100644 (file)
@@ -111,7 +111,7 @@ PARENTS(pxa27x_membus) = { "lcd_base", "lcd_base" };
        PXA_CKEN_1RATE(dev_id, con_id, bit, parents,                    \
                       &CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED)
 
-static struct pxa_clk_cken pxa27x_clocks[] = {
+static struct desc_clk_cken pxa27x_clocks[] __initdata = {
        PXA27X_PBUS_CKEN("pxa2xx-uart.0", NULL, FFUART, 2, 42, 1),
        PXA27X_PBUS_CKEN("pxa2xx-uart.1", NULL, BTUART, 2, 42, 1),
        PXA27X_PBUS_CKEN("pxa2xx-uart.2", NULL, STUART, 2, 42, 1),
@@ -368,3 +368,10 @@ static int __init pxa27x_clocks_init(void)
        return clk_pxa_cken_init(pxa27x_clocks, ARRAY_SIZE(pxa27x_clocks));
 }
 postcore_initcall(pxa27x_clocks_init);
+
+static void __init pxa27x_dt_clocks_init(struct device_node *np)
+{
+       pxa27x_clocks_init();
+       clk_pxa_dt_common_init(np);
+}
+CLK_OF_DECLARE(pxa_clks, "marvell,pxa270-clocks", pxa27x_dt_clocks_init);
index b823bc3b625067c3b64b32b79a0b8b3e17541096..60873a7f45d94b3687bb342b86dd7bbfb9db67df 100644 (file)
@@ -141,7 +141,7 @@ struct pll_freq_tbl *find_freq(const struct pll_freq_tbl *f, unsigned long rate)
 
 static long
 clk_pll_determine_rate(struct clk_hw *hw, unsigned long rate,
-                      unsigned long *p_rate, struct clk **p)
+                      unsigned long *p_rate, struct clk_hw **p)
 {
        struct clk_pll *pll = to_clk_pll(hw);
        const struct pll_freq_tbl *f;
index b6e6959e89aafed9248ba6ddd882e0ece7a4deb1..0b93972c8807f11ef5e27bf6eb9f14e85b9f1055 100644 (file)
@@ -368,16 +368,17 @@ clk_dyn_rcg_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 
 static long _freq_tbl_determine_rate(struct clk_hw *hw,
                const struct freq_tbl *f, unsigned long rate,
-               unsigned long *p_rate, struct clk **p)
+               unsigned long *p_rate, struct clk_hw **p_hw)
 {
        unsigned long clk_flags;
+       struct clk *p;
 
        f = qcom_find_freq(f, rate);
        if (!f)
                return -EINVAL;
 
        clk_flags = __clk_get_flags(hw->clk);
-       *p = clk_get_parent_by_index(hw->clk, f->src);
+       p = clk_get_parent_by_index(hw->clk, f->src);
        if (clk_flags & CLK_SET_RATE_PARENT) {
                rate = rate * f->pre_div;
                if (f->n) {
@@ -387,15 +388,16 @@ static long _freq_tbl_determine_rate(struct clk_hw *hw,
                        rate = tmp;
                }
        } else {
-               rate =  __clk_get_rate(*p);
+               rate =  __clk_get_rate(p);
        }
+       *p_hw = __clk_get_hw(p);
        *p_rate = rate;
 
        return f->freq;
 }
 
 static long clk_rcg_determine_rate(struct clk_hw *hw, unsigned long rate,
-               unsigned long *p_rate, struct clk **p)
+               unsigned long *p_rate, struct clk_hw **p)
 {
        struct clk_rcg *rcg = to_clk_rcg(hw);
 
@@ -403,7 +405,7 @@ static long clk_rcg_determine_rate(struct clk_hw *hw, unsigned long rate,
 }
 
 static long clk_dyn_rcg_determine_rate(struct clk_hw *hw, unsigned long rate,
-               unsigned long *p_rate, struct clk **p)
+               unsigned long *p_rate, struct clk_hw **p)
 {
        struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
 
@@ -411,13 +413,15 @@ static long clk_dyn_rcg_determine_rate(struct clk_hw *hw, unsigned long rate,
 }
 
 static long clk_rcg_bypass_determine_rate(struct clk_hw *hw, unsigned long rate,
-               unsigned long *p_rate, struct clk **p)
+               unsigned long *p_rate, struct clk_hw **p_hw)
 {
        struct clk_rcg *rcg = to_clk_rcg(hw);
        const struct freq_tbl *f = rcg->freq_tbl;
+       struct clk *p;
 
-       *p = clk_get_parent_by_index(hw->clk, f->src);
-       *p_rate = __clk_round_rate(*p, rate);
+       p = clk_get_parent_by_index(hw->clk, f->src);
+       *p_hw = __clk_get_hw(p);
+       *p_rate = __clk_round_rate(p, rate);
 
        return *p_rate;
 }
index cfa9eb4fe9ca60c1420e7821f7d927e1fc82fb10..08b8b3729f539ee769f15d1f474e8c3718d1e640 100644 (file)
@@ -175,16 +175,17 @@ clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 
 static long _freq_tbl_determine_rate(struct clk_hw *hw,
                const struct freq_tbl *f, unsigned long rate,
-               unsigned long *p_rate, struct clk **p)
+               unsigned long *p_rate, struct clk_hw **p_hw)
 {
        unsigned long clk_flags;
+       struct clk *p;
 
        f = qcom_find_freq(f, rate);
        if (!f)
                return -EINVAL;
 
        clk_flags = __clk_get_flags(hw->clk);
-       *p = clk_get_parent_by_index(hw->clk, f->src);
+       p = clk_get_parent_by_index(hw->clk, f->src);
        if (clk_flags & CLK_SET_RATE_PARENT) {
                if (f->pre_div) {
                        rate /= 2;
@@ -198,15 +199,16 @@ static long _freq_tbl_determine_rate(struct clk_hw *hw,
                        rate = tmp;
                }
        } else {
-               rate =  __clk_get_rate(*p);
+               rate =  __clk_get_rate(p);
        }
+       *p_hw = __clk_get_hw(p);
        *p_rate = rate;
 
        return f->freq;
 }
 
 static long clk_rcg2_determine_rate(struct clk_hw *hw, unsigned long rate,
-               unsigned long *p_rate, struct clk **p)
+               unsigned long *p_rate, struct clk_hw **p)
 {
        struct clk_rcg2 *rcg = to_clk_rcg2(hw);
 
@@ -359,7 +361,7 @@ static int clk_edp_pixel_set_rate_and_parent(struct clk_hw *hw,
 }
 
 static long clk_edp_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
-                                unsigned long *p_rate, struct clk **p)
+                                unsigned long *p_rate, struct clk_hw **p)
 {
        struct clk_rcg2 *rcg = to_clk_rcg2(hw);
        const struct freq_tbl *f = rcg->freq_tbl;
@@ -371,7 +373,7 @@ static long clk_edp_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
        u32 hid_div;
 
        /* Force the correct parent */
-       *p = clk_get_parent_by_index(hw->clk, f->src);
+       *p = __clk_get_hw(clk_get_parent_by_index(hw->clk, f->src));
 
        if (src_rate == 810000000)
                frac = frac_table_810m;
@@ -410,18 +412,20 @@ const struct clk_ops clk_edp_pixel_ops = {
 EXPORT_SYMBOL_GPL(clk_edp_pixel_ops);
 
 static long clk_byte_determine_rate(struct clk_hw *hw, unsigned long rate,
-                        unsigned long *p_rate, struct clk **p)
+                        unsigned long *p_rate, struct clk_hw **p_hw)
 {
        struct clk_rcg2 *rcg = to_clk_rcg2(hw);
        const struct freq_tbl *f = rcg->freq_tbl;
        unsigned long parent_rate, div;
        u32 mask = BIT(rcg->hid_width) - 1;
+       struct clk *p;
 
        if (rate == 0)
                return -EINVAL;
 
-       *p = clk_get_parent_by_index(hw->clk, f->src);
-       *p_rate = parent_rate = __clk_round_rate(*p, rate);
+       p = clk_get_parent_by_index(hw->clk, f->src);
+       *p_hw = __clk_get_hw(p);
+       *p_rate = parent_rate = __clk_round_rate(p, rate);
 
        div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
        div = min_t(u32, div, mask);
@@ -472,14 +476,16 @@ static const struct frac_entry frac_table_pixel[] = {
 };
 
 static long clk_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
-                                unsigned long *p_rate, struct clk **p)
+                                unsigned long *p_rate, struct clk_hw **p)
 {
        struct clk_rcg2 *rcg = to_clk_rcg2(hw);
        unsigned long request, src_rate;
        int delta = 100000;
        const struct freq_tbl *f = rcg->freq_tbl;
        const struct frac_entry *frac = frac_table_pixel;
-       struct clk *parent = *p = clk_get_parent_by_index(hw->clk, f->src);
+       struct clk *parent = clk_get_parent_by_index(hw->clk, f->src);
+
+       *p = __clk_get_hw(parent);
 
        for (; frac->num; frac++) {
                request = (rate * frac->den) / frac->num;
index bd8514d63634bdb78ae0e75f801be478265f5f91..2714097f90db1138b1f71771461b15932b826cce 100644 (file)
@@ -6,6 +6,7 @@ obj-y   += clk-rockchip.o
 obj-y  += clk.o
 obj-y  += clk-pll.o
 obj-y  += clk-cpu.o
+obj-y  += clk-mmc-phase.o
 obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
 
 obj-y  += clk-rk3188.o
diff --git a/drivers/clk/rockchip/clk-mmc-phase.c b/drivers/clk/rockchip/clk-mmc-phase.c
new file mode 100644 (file)
index 0000000..c842e3b
--- /dev/null
@@ -0,0 +1,154 @@
+/*
+ * Copyright 2014 Google, Inc
+ * Author: Alexandru M Stan <amstan@chromium.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/slab.h>
+#include <linux/clk-provider.h>
+#include "clk.h"
+
+struct rockchip_mmc_clock {
+       struct clk_hw   hw;
+       void __iomem    *reg;
+       int             id;
+       int             shift;
+};
+
+#define to_mmc_clock(_hw) container_of(_hw, struct rockchip_mmc_clock, hw)
+
+#define RK3288_MMC_CLKGEN_DIV 2
+
+static unsigned long rockchip_mmc_recalc(struct clk_hw *hw,
+                                        unsigned long parent_rate)
+{
+       return parent_rate / RK3288_MMC_CLKGEN_DIV;
+}
+
+#define ROCKCHIP_MMC_DELAY_SEL BIT(10)
+#define ROCKCHIP_MMC_DEGREE_MASK 0x3
+#define ROCKCHIP_MMC_DELAYNUM_OFFSET 2
+#define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET)
+
+#define PSECS_PER_SEC 1000000000000LL
+
+/*
+ * Each fine delay is between 40ps-80ps. Assume each fine delay is 60ps to
+ * simplify calculations. So 45degs could be anywhere between 33deg and 66deg.
+ */
+#define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60
+
+static int rockchip_mmc_get_phase(struct clk_hw *hw)
+{
+       struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);
+       unsigned long rate = clk_get_rate(hw->clk);
+       u32 raw_value;
+       u16 degrees;
+       u32 delay_num = 0;
+
+       raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);
+
+       degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90;
+
+       if (raw_value & ROCKCHIP_MMC_DELAY_SEL) {
+               /* degrees/delaynum * 10000 */
+               unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) *
+                                       36 * (rate / 1000000);
+
+               delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK);
+               delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET;
+               degrees += delay_num * factor / 10000;
+       }
+
+       return degrees % 360;
+}
+
+static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees)
+{
+       struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);
+       unsigned long rate = clk_get_rate(hw->clk);
+       u8 nineties, remainder;
+       u8 delay_num;
+       u32 raw_value;
+       u64 delay;
+
+       /* allow 22 to be 22.5 */
+       degrees++;
+       /* floor to 22.5 increment */
+       degrees -= ((degrees) * 10 % 225) / 10;
+
+       nineties = degrees / 90;
+       /* 22.5 multiples */
+       remainder = (degrees % 90) / 22;
+
+       delay = PSECS_PER_SEC;
+       do_div(delay, rate);
+       /* / 360 / 22.5 */
+       do_div(delay, 16);
+       do_div(delay, ROCKCHIP_MMC_DELAY_ELEMENT_PSEC);
+
+       delay *= remainder;
+       delay_num = (u8) min(delay, 255ULL);
+
+       raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0;
+       raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET;
+       raw_value |= nineties;
+       writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift), mmc_clock->reg);
+
+       pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x actual_degrees=%d\n",
+               __clk_get_name(hw->clk), degrees, delay_num,
+               mmc_clock->reg, raw_value>>(mmc_clock->shift),
+               rockchip_mmc_get_phase(hw)
+       );
+
+       return 0;
+}
+
+static const struct clk_ops rockchip_mmc_clk_ops = {
+       .recalc_rate    = rockchip_mmc_recalc,
+       .get_phase      = rockchip_mmc_get_phase,
+       .set_phase      = rockchip_mmc_set_phase,
+};
+
+struct clk *rockchip_clk_register_mmc(const char *name,
+                               const char **parent_names, u8 num_parents,
+                               void __iomem *reg, int shift)
+{
+       struct clk_init_data init;
+       struct rockchip_mmc_clock *mmc_clock;
+       struct clk *clk;
+
+       mmc_clock = kmalloc(sizeof(*mmc_clock), GFP_KERNEL);
+       if (!mmc_clock)
+               return NULL;
+
+       init.num_parents = num_parents;
+       init.parent_names = parent_names;
+       init.ops = &rockchip_mmc_clk_ops;
+
+       mmc_clock->hw.init = &init;
+       mmc_clock->reg = reg;
+       mmc_clock->shift = shift;
+
+       if (name)
+               init.name = name;
+
+       clk = clk_register(NULL, &mmc_clock->hw);
+       if (IS_ERR(clk))
+               goto err_free;
+
+       return clk;
+
+err_free:
+       kfree(mmc_clock);
+       return NULL;
+}
index a3e886a38480a75060d310bc128944e54169c80d..f8d3baf275b211623efd553d7b7fdf23c609d7f0 100644 (file)
@@ -39,6 +39,7 @@ struct rockchip_clk_pll {
        int                     lock_offset;
        unsigned int            lock_shift;
        enum rockchip_pll_type  type;
+       u8                      flags;
        const struct rockchip_pll_rate_table *rate_table;
        unsigned int            rate_count;
        spinlock_t              *lock;
@@ -257,6 +258,55 @@ static int rockchip_rk3066_pll_is_enabled(struct clk_hw *hw)
        return !(pllcon & RK3066_PLLCON3_PWRDOWN);
 }
 
+static void rockchip_rk3066_pll_init(struct clk_hw *hw)
+{
+       struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
+       const struct rockchip_pll_rate_table *rate;
+       unsigned int nf, nr, no, bwadj;
+       unsigned long drate;
+       u32 pllcon;
+
+       if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
+               return;
+
+       drate = __clk_get_rate(hw->clk);
+       rate = rockchip_get_pll_settings(pll, drate);
+
+       /* when no rate setting for the current rate, rely on clk_set_rate */
+       if (!rate)
+               return;
+
+       pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));
+       nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT) & RK3066_PLLCON0_NR_MASK) + 1;
+       no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT) & RK3066_PLLCON0_OD_MASK) + 1;
+
+       pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));
+       nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT) & RK3066_PLLCON1_NF_MASK) + 1;
+
+       pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2));
+       bwadj = (pllcon >> RK3066_PLLCON2_BWADJ_SHIFT) & RK3066_PLLCON2_BWADJ_MASK;
+
+       pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), bwadj(%d:%d)\n",
+                __func__, __clk_get_name(hw->clk), drate, rate->nr, nr,
+               rate->no, no, rate->nf, nf, rate->bwadj, bwadj);
+       if (rate->nr != nr || rate->no != no || rate->nf != nf
+                                            || rate->bwadj != bwadj) {
+               struct clk *parent = __clk_get_parent(hw->clk);
+               unsigned long prate;
+
+               if (!parent) {
+                       pr_warn("%s: parent of %s not available\n",
+                               __func__, __clk_get_name(hw->clk));
+                       return;
+               }
+
+               pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
+                        __func__, __clk_get_name(hw->clk));
+               prate = __clk_get_rate(parent);
+               rockchip_rk3066_pll_set_rate(hw, drate, prate);
+       }
+}
+
 static const struct clk_ops rockchip_rk3066_pll_clk_norate_ops = {
        .recalc_rate = rockchip_rk3066_pll_recalc_rate,
        .enable = rockchip_rk3066_pll_enable,
@@ -271,6 +321,7 @@ static const struct clk_ops rockchip_rk3066_pll_clk_ops = {
        .enable = rockchip_rk3066_pll_enable,
        .disable = rockchip_rk3066_pll_disable,
        .is_enabled = rockchip_rk3066_pll_is_enabled,
+       .init = rockchip_rk3066_pll_init,
 };
 
 /*
@@ -282,7 +333,7 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
                void __iomem *base, int con_offset, int grf_lock_offset,
                int lock_shift, int mode_offset, int mode_shift,
                struct rockchip_pll_rate_table *rate_table,
-               spinlock_t *lock)
+               u8 clk_pll_flags, spinlock_t *lock)
 {
        const char *pll_parents[3];
        struct clk_init_data init;
@@ -345,8 +396,22 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
        pll->reg_base = base + con_offset;
        pll->lock_offset = grf_lock_offset;
        pll->lock_shift = lock_shift;
+       pll->flags = clk_pll_flags;
        pll->lock = lock;
 
+       /* create the mux on top of the real pll */
+       pll->pll_mux_ops = &clk_mux_ops;
+       pll_mux = &pll->pll_mux;
+       pll_mux->reg = base + mode_offset;
+       pll_mux->shift = mode_shift;
+       pll_mux->mask = PLL_MODE_MASK;
+       pll_mux->flags = 0;
+       pll_mux->lock = lock;
+       pll_mux->hw.init = &init;
+
+       if (pll_type == pll_rk3066)
+               pll_mux->flags |= CLK_MUX_HIWORD_MASK;
+
        pll_clk = clk_register(NULL, &pll->hw);
        if (IS_ERR(pll_clk)) {
                pr_err("%s: failed to register pll clock %s : %ld\n",
@@ -355,10 +420,6 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
                goto err_pll;
        }
 
-       /* create the mux on top of the real pll */
-       pll->pll_mux_ops = &clk_mux_ops;
-       pll_mux = &pll->pll_mux;
-
        /* the actual muxing is xin24m, pll-output, xin32k */
        pll_parents[0] = parent_names[0];
        pll_parents[1] = pll_name;
@@ -370,16 +431,6 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
        init.parent_names = pll_parents;
        init.num_parents = ARRAY_SIZE(pll_parents);
 
-       pll_mux->reg = base + mode_offset;
-       pll_mux->shift = mode_shift;
-       pll_mux->mask = PLL_MODE_MASK;
-       pll_mux->flags = 0;
-       pll_mux->lock = lock;
-       pll_mux->hw.init = &init;
-
-       if (pll_type == pll_rk3066)
-               pll_mux->flags |= CLK_MUX_HIWORD_MASK;
-
        mux_clk = clk_register(NULL, &pll_mux->hw);
        if (IS_ERR(mux_clk))
                goto err_mux;
index beed49c79126bb1412cf7b217586aa8c0b6e532d..c54078960847c91f6f499ecb8f26924338bb2ab4 100644 (file)
@@ -212,13 +212,13 @@ PNAME(mux_sclk_macref_p)  = { "mac_src", "ext_rmii" };
 
 static struct rockchip_pll_clock rk3188_pll_clks[] __initdata = {
        [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
-                    RK2928_MODE_CON, 0, 6, rk3188_pll_rates),
+                    RK2928_MODE_CON, 0, 6, 0, rk3188_pll_rates),
        [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
-                    RK2928_MODE_CON, 4, 5, NULL),
+                    RK2928_MODE_CON, 4, 5, 0, NULL),
        [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
-                    RK2928_MODE_CON, 8, 7, rk3188_pll_rates),
+                    RK2928_MODE_CON, 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
        [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
-                    RK2928_MODE_CON, 12, 8, rk3188_pll_rates),
+                    RK2928_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
 };
 
 #define MFLAGS CLK_MUX_HIWORD_MASK
@@ -257,9 +257,9 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
        GATE(0, "hclk_vdpu", "aclk_vdpu", 0,
                        RK2928_CLKGATE_CON(3), 12, GFLAGS),
 
-       GATE(0, "gpll_ddr", "gpll", 0,
+       GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
                        RK2928_CLKGATE_CON(1), 7, GFLAGS),
-       COMPOSITE(0, "ddrphy", mux_ddrphy_p, 0,
+       COMPOSITE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
                        RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
                        RK2928_CLKGATE_CON(0), 2, GFLAGS),
 
@@ -270,10 +270,10 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
                        RK2928_CLKGATE_CON(0), 6, GFLAGS),
        GATE(0, "pclk_cpu", "pclk_cpu_pre", 0,
                        RK2928_CLKGATE_CON(0), 5, GFLAGS),
-       GATE(0, "hclk_cpu", "hclk_cpu_pre", 0,
+       GATE(0, "hclk_cpu", "hclk_cpu_pre", CLK_IGNORE_UNUSED,
                        RK2928_CLKGATE_CON(0), 4, GFLAGS),
 
-       COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, 0,
+       COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
                        RK2928_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 5, DFLAGS,
                        RK2928_CLKGATE_CON(3), 0, GFLAGS),
        COMPOSITE(0, "aclk_lcdc1_pre", mux_pll_src_cpll_gpll_p, 0,
@@ -304,9 +304,9 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
         * the 480m are generated inside the usb block from these clocks,
         * but they are also a source for the hsicphy clock.
         */
-       GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", 0,
+       GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", CLK_IGNORE_UNUSED,
                        RK2928_CLKGATE_CON(1), 5, GFLAGS),
-       GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", 0,
+       GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", CLK_IGNORE_UNUSED,
                        RK2928_CLKGATE_CON(1), 6, GFLAGS),
 
        COMPOSITE(0, "mac_src", mux_mac_p, 0,
@@ -320,9 +320,9 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
        COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0,
                        RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
                        RK2928_CLKGATE_CON(2), 6, GFLAGS),
-       COMPOSITE_FRAC(0, "hsadc_frac", "hsadc_src",
+       COMPOSITE_FRAC(0, "hsadc_frac", "hsadc_src", 0,
                        RK2928_CLKSEL_CON(23), 0,
-                       RK2928_CLKGATE_CON(2), 7, 0, GFLAGS),
+                       RK2928_CLKGATE_CON(2), 7, GFLAGS),
        MUX(SCLK_HSADC, "sclk_hsadc", mux_sclk_hsadc_p, 0,
                        RK2928_CLKSEL_CON(22), 4, 2, MFLAGS),
 
@@ -330,6 +330,15 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
                        RK2928_CLKSEL_CON(24), 8, 8, DFLAGS,
                        RK2928_CLKGATE_CON(2), 8, GFLAGS),
 
+       COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0,
+                       RK2928_CLKSEL_CON(5), 0, 7, DFLAGS,
+                       RK2928_CLKGATE_CON(0), 13, GFLAGS),
+       COMPOSITE_FRAC(0, "spdif_frac", "spdif_pll", 0,
+                       RK2928_CLKSEL_CON(9), 0,
+                       RK2928_CLKGATE_CON(0), 14, GFLAGS),
+       MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0,
+                       RK2928_CLKSEL_CON(5), 8, 2, MFLAGS),
+
        /*
         * Clock-Architecture Diagram 4
         */
@@ -399,8 +408,8 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
 
        /* aclk_cpu gates */
        GATE(ACLK_DMA1, "aclk_dma1", "aclk_cpu", 0, RK2928_CLKGATE_CON(5), 0, GFLAGS),
-       GATE(0, "aclk_intmem", "aclk_cpu", 0, RK2928_CLKGATE_CON(4), 12, GFLAGS),
-       GATE(0, "aclk_strc_sys", "aclk_cpu", 0, RK2928_CLKGATE_CON(4), 10, GFLAGS),
+       GATE(0, "aclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 12, GFLAGS),
+       GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 10, GFLAGS),
 
        /* hclk_cpu gates */
        GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(5), 6, GFLAGS),
@@ -410,14 +419,14 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
        /* hclk_ahb2apb is part of a clk branch */
        GATE(0, "hclk_vio_bus", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 12, GFLAGS),
        GATE(HCLK_LCDC0, "hclk_lcdc0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 1, GFLAGS),
-       GATE(HCLK_LCDC1, "hclk_lcdc1", "aclk_cpu", 0, RK2928_CLKGATE_CON(6), 2, GFLAGS),
+       GATE(HCLK_LCDC1, "hclk_lcdc1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 2, GFLAGS),
        GATE(HCLK_CIF0, "hclk_cif0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 4, GFLAGS),
        GATE(HCLK_IPP, "hclk_ipp", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 9, GFLAGS),
        GATE(HCLK_RGA, "hclk_rga", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 10, GFLAGS),
 
        /* hclk_peri gates */
-       GATE(0, "hclk_peri_axi_matrix", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 0, GFLAGS),
-       GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 6, GFLAGS),
+       GATE(0, "hclk_peri_axi_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS),
+       GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 6, GFLAGS),
        GATE(0, "hclk_emem_peri", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 7, GFLAGS),
        GATE(HCLK_EMAC, "hclk_emac", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS),
        GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
@@ -457,18 +466,18 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
        GATE(0, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS),
        GATE(0, "pclk_ddrpubl", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
        GATE(0, "pclk_dbg", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),
-       GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 4, GFLAGS),
-       GATE(PCLK_PMU, "pclk_pmu", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 5, GFLAGS),
+       GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),
+       GATE(PCLK_PMU, "pclk_pmu", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 5, GFLAGS),
 
        /* aclk_peri */
        GATE(ACLK_DMA2, "aclk_dma2", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS),
        GATE(ACLK_SMC, "aclk_smc", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 8, GFLAGS),
-       GATE(0, "aclk_peri_niu", "aclk_peri", 0, RK2928_CLKGATE_CON(4), 4, GFLAGS),
-       GATE(0, "aclk_cpu_peri", "aclk_peri", 0, RK2928_CLKGATE_CON(4), 2, GFLAGS),
-       GATE(0, "aclk_peri_axi_matrix", "aclk_peri", 0, RK2928_CLKGATE_CON(4), 3, GFLAGS),
+       GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 4, GFLAGS),
+       GATE(0, "aclk_cpu_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS),
+       GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 3, GFLAGS),
 
        /* pclk_peri gates */
-       GATE(0, "pclk_peri_axi_matrix", "pclk_peri", 0, RK2928_CLKGATE_CON(4), 1, GFLAGS),
+       GATE(0, "pclk_peri_axi_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS),
        GATE(PCLK_PWM23, "pclk_pwm23", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 11, GFLAGS),
        GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
        GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS),
@@ -511,7 +520,7 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
                                                            | CLK_DIVIDER_READ_ONLY,
                        RK2928_CLKGATE_CON(4), 9, GFLAGS),
 
-       GATE(CORE_L2C, "core_l2c", "aclk_cpu", 0,
+       GATE(CORE_L2C, "core_l2c", "aclk_cpu", CLK_IGNORE_UNUSED,
                        RK2928_CLKGATE_CON(9), 4, GFLAGS),
 
        COMPOSITE(0, "aclk_peri_pre", mux_pll_src_gpll_cpll_p, 0,
@@ -577,14 +586,6 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
                        RK2928_CLKGATE_CON(0), 12, GFLAGS),
        MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, 0,
                        RK2928_CLKSEL_CON(4), 8, 2, MFLAGS),
-       COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0,
-                       RK2928_CLKSEL_CON(5), 0, 7, DFLAGS,
-                       RK2928_CLKGATE_CON(0), 13, GFLAGS),
-       COMPOSITE_FRAC(0, "spdif_frac", "spdif_pll", 0,
-                       RK2928_CLKSEL_CON(9), 0,
-                       RK2928_CLKGATE_CON(0), 14, GFLAGS),
-       MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0,
-                       RK2928_CLKSEL_CON(5), 8, 2, MFLAGS),
 
        GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
        GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
@@ -618,7 +619,7 @@ PNAME(mux_hsicphy_p)                = { "sclk_otgphy0", "sclk_otgphy1",
                                    "gpll", "cpll" };
 
 static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
-       COMPOSITE_NOMUX_DIVTBL(0, "aclk_core", "armclk", 0,
+       COMPOSITE_NOMUX_DIVTBL(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
                        RK2928_CLKSEL_CON(1), 3, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
                        div_rk3188_aclk_core_t, RK2928_CLKGATE_CON(0), 7, GFLAGS),
 
@@ -633,7 +634,7 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
                        RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
                        RK2928_CLKGATE_CON(4), 9, GFLAGS),
 
-       GATE(CORE_L2C, "core_l2c", "armclk", 0,
+       GATE(CORE_L2C, "core_l2c", "armclk", CLK_IGNORE_UNUSED,
                        RK2928_CLKGATE_CON(9), 4, GFLAGS),
 
        COMPOSITE(0, "aclk_peri_pre", mux_pll_src_cpll_gpll_p, 0,
@@ -663,7 +664,7 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
                        RK2928_CLKSEL_CON(30), 0, 2, DFLAGS,
                        RK2928_CLKGATE_CON(3), 6, GFLAGS),
        DIV(0, "sclk_hsicphy_12m", "sclk_hsicphy_480m", 0,
-                       RK2928_CLKGATE_CON(11), 8, 6, DFLAGS),
+                       RK2928_CLKSEL_CON(11), 8, 6, DFLAGS),
 
        MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0,
                        RK2928_CLKSEL_CON(2), 15, 1, MFLAGS),
@@ -675,14 +676,6 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
                        RK2928_CLKGATE_CON(0), 10, GFLAGS),
        MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0,
                        RK2928_CLKSEL_CON(3), 8, 2, MFLAGS),
-       COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0,
-                       RK2928_CLKSEL_CON(5), 0, 7, DFLAGS,
-                       RK2928_CLKGATE_CON(13), 13, GFLAGS),
-       COMPOSITE_FRAC(0, "spdif_frac", "spdif_pll", 0,
-                       RK2928_CLKSEL_CON(9), 0,
-                       RK2928_CLKGATE_CON(0), 14, GFLAGS),
-       MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0,
-                       RK2928_CLKSEL_CON(5), 8, 2, MFLAGS),
 
        GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
        GATE(0, "hclk_imem1", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 15, GFLAGS),
index 23278291da448de806a9a8929fe300c6952aafec..ac6be7c0132d1e27cfad2f95169212b70f3d31d2 100644 (file)
@@ -16,6 +16,7 @@
 #include <linux/clk-provider.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/syscore_ops.h>
 #include <dt-bindings/clock/rk3288-cru.h>
 #include "clk.h"
 
@@ -83,11 +84,13 @@ struct rockchip_pll_rate_table rk3288_pll_rates[] = {
        RK3066_PLL_RATE( 742500000, 8, 495, 2),
        RK3066_PLL_RATE( 696000000, 1, 58, 2),
        RK3066_PLL_RATE( 600000000, 1, 50, 2),
-       RK3066_PLL_RATE( 594000000, 2, 198, 4),
+       RK3066_PLL_RATE_BWADJ(594000000, 1, 198, 8, 1),
        RK3066_PLL_RATE( 552000000, 1, 46, 2),
        RK3066_PLL_RATE( 504000000, 1, 84, 4),
+       RK3066_PLL_RATE( 500000000, 3, 125, 2),
        RK3066_PLL_RATE( 456000000, 1, 76, 4),
        RK3066_PLL_RATE( 408000000, 1, 68, 4),
+       RK3066_PLL_RATE( 400000000, 3, 100, 2),
        RK3066_PLL_RATE( 384000000, 2, 128, 4),
        RK3066_PLL_RATE( 360000000, 1, 60, 4),
        RK3066_PLL_RATE( 312000000, 1, 52, 4),
@@ -173,14 +176,14 @@ PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu" };
 PNAME(mux_pll_src_cpll_gpll_p)         = { "cpll", "gpll" };
 PNAME(mux_pll_src_npll_cpll_gpll_p)    = { "npll", "cpll", "gpll" };
 PNAME(mux_pll_src_cpll_gpll_npll_p)    = { "cpll", "gpll", "npll" };
-PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usb480m" };
+PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usbphy480m_src" };
+PNAME(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "usbphy480m_src", "npll" };
 
 PNAME(mux_mmc_src_p)   = { "cpll", "gpll", "xin24m", "xin24m" };
 PNAME(mux_i2s_pre_p)   = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
 PNAME(mux_i2s_clkout_p)        = { "i2s_pre", "xin12m" };
 PNAME(mux_spdif_p)     = { "spdif_pre", "spdif_frac", "xin12m" };
 PNAME(mux_spdif_8ch_p) = { "spdif_8ch_pre", "spdif_8ch_frac", "xin12m" };
-PNAME(mux_uart0_pll_p) = { "cpll", "gpll", "usbphy_480m_src", "npll" };
 PNAME(mux_uart0_p)     = { "uart0_src", "uart0_frac", "xin24m" };
 PNAME(mux_uart1_p)     = { "uart1_src", "uart1_frac", "xin24m" };
 PNAME(mux_uart2_p)     = { "uart2_src", "uart2_frac", "xin24m" };
@@ -192,22 +195,22 @@ PNAME(mux_hsadcout_p)     = { "hsadc_src", "ext_hsadc" };
 PNAME(mux_edp_24m_p)   = { "ext_edp_24m", "xin24m" };
 PNAME(mux_tspout_p)    = { "cpll", "gpll", "npll", "xin27m" };
 
-PNAME(mux_usbphy480m_p)                = { "sclk_otgphy0", "sclk_otgphy1",
-                                   "sclk_otgphy2" };
+PNAME(mux_usbphy480m_p)                = { "sclk_otgphy1", "sclk_otgphy2",
+                                   "sclk_otgphy0" };
 PNAME(mux_hsicphy480m_p)       = { "cpll", "gpll", "usbphy480m_src" };
 PNAME(mux_hsicphy12m_p)                = { "hsicphy12m_xin12m", "hsicphy12m_usbphy" };
 
 static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {
        [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK3288_PLL_CON(0),
-                    RK3288_MODE_CON, 0, 6, rk3288_pll_rates),
+                    RK3288_MODE_CON, 0, 6, 0, rk3288_pll_rates),
        [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3288_PLL_CON(4),
-                    RK3288_MODE_CON, 4, 5, NULL),
+                    RK3288_MODE_CON, 4, 5, 0, NULL),
        [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8),
-                    RK3288_MODE_CON, 8, 7, rk3288_pll_rates),
+                    RK3288_MODE_CON, 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
        [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
-                    RK3288_MODE_CON, 12, 8, rk3288_pll_rates),
+                    RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
        [npll] = PLL(pll_rk3066, PLL_NPLL, "npll",  mux_pll_p, 0, RK3288_PLL_CON(16),
-                    RK3288_MODE_CON, 14, 9, rk3288_pll_rates),
+                    RK3288_MODE_CON, 14, 9, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
 };
 
 static struct clk_div_table div_hclk_cpu_t[] = {
@@ -226,67 +229,67 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
         * Clock-Architecture Diagram 1
         */
 
-       GATE(0, "apll_core", "apll", 0,
+       GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
                        RK3288_CLKGATE_CON(0), 1, GFLAGS),
-       GATE(0, "gpll_core", "gpll", 0,
+       GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
                        RK3288_CLKGATE_CON(0), 2, GFLAGS),
 
-       COMPOSITE_NOMUX(0, "armcore0", "armclk", 0,
+       COMPOSITE_NOMUX(0, "armcore0", "armclk", CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(36), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
                        RK3288_CLKGATE_CON(12), 0, GFLAGS),
-       COMPOSITE_NOMUX(0, "armcore1", "armclk", 0,
+       COMPOSITE_NOMUX(0, "armcore1", "armclk", CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(36), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
                        RK3288_CLKGATE_CON(12), 1, GFLAGS),
-       COMPOSITE_NOMUX(0, "armcore2", "armclk", 0,
+       COMPOSITE_NOMUX(0, "armcore2", "armclk", CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(36), 8, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
                        RK3288_CLKGATE_CON(12), 2, GFLAGS),
-       COMPOSITE_NOMUX(0, "armcore3", "armclk", 0,
+       COMPOSITE_NOMUX(0, "armcore3", "armclk", CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(36), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
                        RK3288_CLKGATE_CON(12), 3, GFLAGS),
-       COMPOSITE_NOMUX(0, "l2ram", "armclk", 0,
+       COMPOSITE_NOMUX(0, "l2ram", "armclk", CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(37), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
                        RK3288_CLKGATE_CON(12), 4, GFLAGS),
-       COMPOSITE_NOMUX(0, "aclk_core_m0", "armclk", 0,
+       COMPOSITE_NOMUX(0, "aclk_core_m0", "armclk", CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(0), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
                        RK3288_CLKGATE_CON(12), 5, GFLAGS),
-       COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", 0,
+       COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(0), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
                        RK3288_CLKGATE_CON(12), 6, GFLAGS),
        COMPOSITE_NOMUX(0, "atclk", "armclk", 0,
                        RK3288_CLKSEL_CON(37), 4, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
                        RK3288_CLKGATE_CON(12), 7, GFLAGS),
-       COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", 0,
+       COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(37), 9, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
                        RK3288_CLKGATE_CON(12), 8, GFLAGS),
        GATE(0, "pclk_dbg", "pclk_dbg_pre", 0,
                        RK3288_CLKGATE_CON(12), 9, GFLAGS),
-       GATE(0, "cs_dbg", "pclk_dbg_pre", 0,
+       GATE(0, "cs_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
                        RK3288_CLKGATE_CON(12), 10, GFLAGS),
        GATE(0, "pclk_core_niu", "pclk_dbg_pre", 0,
                        RK3288_CLKGATE_CON(12), 11, GFLAGS),
 
-       GATE(0, "dpll_ddr", "dpll", 0,
+       GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
                        RK3288_CLKGATE_CON(0), 8, GFLAGS),
        GATE(0, "gpll_ddr", "gpll", 0,
                        RK3288_CLKGATE_CON(0), 9, GFLAGS),
-       COMPOSITE_NOGATE(0, "ddrphy", mux_ddrphy_p, 0,
+       COMPOSITE_NOGATE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(26), 2, 1, MFLAGS, 0, 2,
                                        DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
 
-       GATE(0, "gpll_aclk_cpu", "gpll", 0,
+       GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED,
                        RK3288_CLKGATE_CON(0), 10, GFLAGS),
-       GATE(0, "cpll_aclk_cpu", "cpll", 0,
+       GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED,
                        RK3288_CLKGATE_CON(0), 11, GFLAGS),
-       COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0,
+       COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(1), 15, 1, MFLAGS, 3, 5, DFLAGS),
-       DIV(0, "aclk_cpu_pre", "aclk_cpu_src", 0,
+       DIV(0, "aclk_cpu_pre", "aclk_cpu_src", CLK_SET_RATE_PARENT,
                        RK3288_CLKSEL_CON(1), 0, 3, DFLAGS),
-       GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0,
+       GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
                        RK3288_CLKGATE_CON(0), 3, GFLAGS),
-       COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_pre", 0,
+       COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(1), 12, 3, DFLAGS,
                        RK3288_CLKGATE_CON(0), 5, GFLAGS),
-       COMPOSITE_NOMUX_DIVTBL(HCLK_CPU, "hclk_cpu", "aclk_cpu_pre", 0,
+       COMPOSITE_NOMUX_DIVTBL(HCLK_CPU, "hclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(1), 8, 2, DFLAGS, div_hclk_cpu_t,
                        RK3288_CLKGATE_CON(0), 4, GFLAGS),
        GATE(0, "c2c_host", "aclk_cpu_src", 0,
@@ -294,7 +297,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
        COMPOSITE_NOMUX(0, "crypto", "aclk_cpu_pre", 0,
                        RK3288_CLKSEL_CON(26), 6, 2, DFLAGS,
                        RK3288_CLKGATE_CON(5), 4, GFLAGS),
-       GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", 0,
+       GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
                        RK3288_CLKGATE_CON(0), 7, GFLAGS),
 
        COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0,
@@ -305,7 +308,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
                        RK3288_CLKGATE_CON(4), 2, GFLAGS),
        MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
                        RK3288_CLKSEL_CON(4), 8, 2, MFLAGS),
-       COMPOSITE_NODIV(0, "i2s0_clkout", mux_i2s_clkout_p, CLK_SET_RATE_PARENT,
+       COMPOSITE_NODIV(SCLK_I2S0_OUT, "i2s0_clkout", mux_i2s_clkout_p, 0,
                        RK3288_CLKSEL_CON(4), 12, 1, MFLAGS,
                        RK3288_CLKGATE_CON(4), 0, GFLAGS),
        GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT,
@@ -325,7 +328,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
        COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", 0,
                        RK3288_CLKSEL_CON(40), 0, 7, DFLAGS,
                        RK3288_CLKGATE_CON(4), 7, GFLAGS),
-       COMPOSITE_FRAC(0, "spdif_8ch_frac", "spdif_8ch_src", 0,
+       COMPOSITE_FRAC(0, "spdif_8ch_frac", "spdif_8ch_pre", 0,
                        RK3288_CLKSEL_CON(41), 0,
                        RK3288_CLKGATE_CON(4), 8, GFLAGS),
        COMPOSITE_NODIV(SCLK_SPDIF8CH, "sclk_spdif_8ch", mux_spdif_8ch_p, 0,
@@ -373,12 +376,12 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
        GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
                RK3288_CLKGATE_CON(9), 1, GFLAGS),
 
-       COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, 0,
+       COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
                        RK3288_CLKGATE_CON(3), 0, GFLAGS),
        DIV(0, "hclk_vio", "aclk_vio0", 0,
                        RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
-       COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, 0,
+       COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
                        RK3288_CLKGATE_CON(3), 2, GFLAGS),
 
@@ -436,24 +439,24 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
 
        DIV(0, "pclk_pd_alive", "gpll", 0,
                        RK3288_CLKSEL_CON(33), 8, 5, DFLAGS),
-       COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", 0,
+       COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(33), 0, 5, DFLAGS,
                        RK3288_CLKGATE_CON(5), 8, GFLAGS),
 
-       COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_cpll_gpll_usb480m_p, 0,
+       COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_cpll_gll_usb_npll_p, 0,
                        RK3288_CLKSEL_CON(34), 6, 2, MFLAGS, 0, 5, DFLAGS,
                        RK3288_CLKGATE_CON(5), 7, GFLAGS),
 
-       COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, 0,
+       COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
                        RK3288_CLKGATE_CON(2), 0, GFLAGS),
        COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
                        RK3288_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
                        RK3288_CLKGATE_CON(2), 3, GFLAGS),
-       COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0,
+       COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
                        RK3288_CLKGATE_CON(2), 2, GFLAGS),
-       GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
+       GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
                        RK3288_CLKGATE_CON(2), 1, GFLAGS),
 
        /*
@@ -483,6 +486,18 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
                        RK3288_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 6, DFLAGS,
                        RK3288_CLKGATE_CON(13), 3, GFLAGS),
 
+       MMC(SCLK_SDMMC_DRV,    "sdmmc_drv",    "sclk_sdmmc", RK3288_SDMMC_CON0, 1),
+       MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3288_SDMMC_CON1, 0),
+
+       MMC(SCLK_SDIO0_DRV,    "sdio0_drv",    "sclk_sdio0", RK3288_SDIO0_CON0, 1),
+       MMC(SCLK_SDIO0_SAMPLE, "sdio0_sample", "sclk_sdio0", RK3288_SDIO0_CON1, 0),
+
+       MMC(SCLK_SDIO1_DRV,    "sdio1_drv",    "sclk_sdio1", RK3288_SDIO1_CON0, 1),
+       MMC(SCLK_SDIO1_SAMPLE, "sdio1_sample", "sclk_sdio1", RK3288_SDIO1_CON1, 0),
+
+       MMC(SCLK_EMMC_DRV,     "emmc_drv",     "sclk_emmc",  RK3288_EMMC_CON0,  1),
+       MMC(SCLK_EMMC_SAMPLE,  "emmc_sample",  "sclk_emmc",  RK3288_EMMC_CON1,  0),
+
        COMPOSITE(0, "sclk_tspout", mux_tspout_p, 0,
                        RK3288_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS,
                        RK3288_CLKGATE_CON(4), 11, GFLAGS),
@@ -490,13 +505,13 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
                        RK3288_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
                        RK3288_CLKGATE_CON(4), 10, GFLAGS),
 
-       GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", 0,
+       GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", CLK_IGNORE_UNUSED,
                        RK3288_CLKGATE_CON(13), 4, GFLAGS),
-       GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", 0,
+       GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", CLK_IGNORE_UNUSED,
                        RK3288_CLKGATE_CON(13), 5, GFLAGS),
-       GATE(SCLK_OTGPHY2, "sclk_otgphy2", "usb480m", 0,
+       GATE(SCLK_OTGPHY2, "sclk_otgphy2", "usb480m", CLK_IGNORE_UNUSED,
                        RK3288_CLKGATE_CON(13), 6, GFLAGS),
-       GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", 0,
+       GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", CLK_IGNORE_UNUSED,
                        RK3288_CLKGATE_CON(13), 7, GFLAGS),
 
        COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin32k", 0,
@@ -517,7 +532,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
                        RK3288_CLKSEL_CON(38), 15, 1, MFLAGS, 8, 5, DFLAGS,
                        RK3288_CLKGATE_CON(5), 6, GFLAGS),
 
-       COMPOSITE(0, "uart0_src", mux_uart0_pll_p, 0,
+       COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gll_usb_npll_p, 0,
                        RK3288_CLKSEL_CON(13), 13, 2, MFLAGS, 0, 7, DFLAGS,
                        RK3288_CLKGATE_CON(1), 8, GFLAGS),
        COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", 0,
@@ -585,7 +600,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
 
        COMPOSITE_NODIV(0, "usbphy480m_src", mux_usbphy480m_p, 0,
                        RK3288_CLKSEL_CON(13), 11, 2, MFLAGS,
-                       RK3288_CLKGATE_CON(5), 15, GFLAGS),
+                       RK3288_CLKGATE_CON(5), 14, GFLAGS),
        COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
                        RK3288_CLKSEL_CON(29), 0, 2, MFLAGS,
                        RK3288_CLKGATE_CON(3), 6, GFLAGS),
@@ -601,19 +616,19 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
         */
 
        /* aclk_cpu gates */
-       GATE(0, "sclk_intmem0", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 5, GFLAGS),
-       GATE(0, "sclk_intmem1", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 6, GFLAGS),
-       GATE(0, "sclk_intmem2", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 7, GFLAGS),
+       GATE(0, "sclk_intmem0", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 5, GFLAGS),
+       GATE(0, "sclk_intmem1", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 6, GFLAGS),
+       GATE(0, "sclk_intmem2", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 7, GFLAGS),
        GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 12, GFLAGS),
-       GATE(0, "aclk_strc_sys", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 13, GFLAGS),
-       GATE(0, "aclk_intmem", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 4, GFLAGS),
+       GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 13, GFLAGS),
+       GATE(0, "aclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 4, GFLAGS),
        GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 6, GFLAGS),
        GATE(0, "aclk_ccp", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 8, GFLAGS),
 
        /* hclk_cpu gates */
        GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 0, RK3288_CLKGATE_CON(11), 7, GFLAGS),
        GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 8, GFLAGS),
-       GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 9, GFLAGS),
+       GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 9, GFLAGS),
        GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 10, GFLAGS),
        GATE(HCLK_SPDIF8CH, "hclk_spdif_8ch", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 11, GFLAGS),
 
@@ -622,42 +637,42 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
        GATE(PCLK_TIMER, "pclk_timer", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 1, GFLAGS),
        GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 2, GFLAGS),
        GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 3, GFLAGS),
-       GATE(0, "pclk_ddrupctl0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 14, GFLAGS),
-       GATE(0, "pclk_publ0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 15, GFLAGS),
-       GATE(0, "pclk_ddrupctl1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 0, GFLAGS),
-       GATE(0, "pclk_publ1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 1, GFLAGS),
+       GATE(PCLK_DDRUPCTL0, "pclk_ddrupctl0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 14, GFLAGS),
+       GATE(PCLK_PUBL0, "pclk_publ0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 15, GFLAGS),
+       GATE(PCLK_DDRUPCTL1, "pclk_ddrupctl1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 0, GFLAGS),
+       GATE(PCLK_PUBL1, "pclk_publ1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 1, GFLAGS),
        GATE(0, "pclk_efuse_1024", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 2, GFLAGS),
        GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS),
        GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS),
        GATE(0, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS),
-       GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 11, GFLAGS),
+       GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 11, GFLAGS),
 
        /* ddrctrl [DDR Controller PHY clock] gates */
-       GATE(0, "nclk_ddrupctl0", "ddrphy", 0, RK3288_CLKGATE_CON(11), 4, GFLAGS),
-       GATE(0, "nclk_ddrupctl1", "ddrphy", 0, RK3288_CLKGATE_CON(11), 5, GFLAGS),
+       GATE(0, "nclk_ddrupctl0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 4, GFLAGS),
+       GATE(0, "nclk_ddrupctl1", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 5, GFLAGS),
 
        /* ddrphy gates */
-       GATE(0, "sclk_ddrphy0", "ddrphy", 0, RK3288_CLKGATE_CON(4), 12, GFLAGS),
-       GATE(0, "sclk_ddrphy1", "ddrphy", 0, RK3288_CLKGATE_CON(4), 13, GFLAGS),
+       GATE(0, "sclk_ddrphy0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(4), 12, GFLAGS),
+       GATE(0, "sclk_ddrphy1", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(4), 13, GFLAGS),
 
        /* aclk_peri gates */
-       GATE(0, "aclk_peri_axi_matrix", "aclk_peri", 0, RK3288_CLKGATE_CON(6), 2, GFLAGS),
+       GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 2, GFLAGS),
        GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 0, RK3288_CLKGATE_CON(6), 3, GFLAGS),
-       GATE(0, "aclk_peri_niu", "aclk_peri", 0, RK3288_CLKGATE_CON(7), 11, GFLAGS),
-       GATE(ACLK_MMU, "aclk_mmu", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 12, GFLAGS),
+       GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 11, GFLAGS),
+       GATE(ACLK_MMU, "aclk_mmu", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(8), 12, GFLAGS),
        GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 0, GFLAGS),
        GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 2, GFLAGS),
 
        /* hclk_peri gates */
-       GATE(0, "hclk_peri_matrix", "hclk_peri", 0, RK3288_CLKGATE_CON(6), 0, GFLAGS),
-       GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 4, GFLAGS),
+       GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 0, GFLAGS),
+       GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 4, GFLAGS),
        GATE(HCLK_USBHOST0, "hclk_host0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 6, GFLAGS),
-       GATE(HCLK_USBHOST1, "hclk_host1", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 7, GFLAGS),
+       GATE(HCLK_USBHOST1, "hclk_host1", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 7, GFLAGS),
        GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 8, GFLAGS),
-       GATE(0, "hclk_usb_peri", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 9, GFLAGS),
-       GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 10, GFLAGS),
-       GATE(0, "hclk_emem", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 12, GFLAGS),
-       GATE(0, "hclk_mem", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 13, GFLAGS),
+       GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 9, GFLAGS),
+       GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 10, GFLAGS),
+       GATE(0, "hclk_emem", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 12, GFLAGS),
+       GATE(0, "hclk_mem", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 13, GFLAGS),
        GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 14, GFLAGS),
        GATE(HCLK_NANDC1, "hclk_nandc1", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 15, GFLAGS),
        GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 8, GFLAGS),
@@ -669,7 +684,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
        GATE(0, "pmu_hclk_otg0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 5, GFLAGS),
 
        /* pclk_peri gates */
-       GATE(0, "pclk_peri_matrix", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 1, GFLAGS),
+       GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 1, GFLAGS),
        GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 4, GFLAGS),
        GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 5, GFLAGS),
        GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 6, GFLAGS),
@@ -705,48 +720,48 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
        GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 4, GFLAGS),
        GATE(PCLK_GPIO5, "pclk_gpio5", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 5, GFLAGS),
        GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 6, GFLAGS),
-       GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 11, GFLAGS),
-       GATE(0, "pclk_alive_niu", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 12, GFLAGS),
+       GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14), 11, GFLAGS),
+       GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14), 12, GFLAGS),
 
        /* pclk_pd_pmu gates */
-       GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 0, GFLAGS),
-       GATE(0, "pclk_intmem1", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 1, GFLAGS),
-       GATE(0, "pclk_pmu_niu", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 2, GFLAGS),
-       GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 3, GFLAGS),
+       GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 0, GFLAGS),
+       GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 1, GFLAGS),
+       GATE(0, "pclk_pmu_niu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 2, GFLAGS),
+       GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 3, GFLAGS),
        GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 4, GFLAGS),
 
        /* hclk_vio gates */
        GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 1, GFLAGS),
        GATE(HCLK_VOP0, "hclk_vop0", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 6, GFLAGS),
        GATE(HCLK_VOP1, "hclk_vop1", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 8, GFLAGS),
-       GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 9, GFLAGS),
-       GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 10, GFLAGS),
+       GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 9, GFLAGS),
+       GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 10, GFLAGS),
        GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS),
        GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 3, GFLAGS),
        GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 1, GFLAGS),
-       GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 10, GFLAGS),
+       GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 10, GFLAGS),
        GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 4, GFLAGS),
        GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS),
        GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 6, GFLAGS),
        GATE(PCLK_LVDS_PHY, "pclk_lvds_phy", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 7, GFLAGS),
-       GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 8, GFLAGS),
+       GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 8, GFLAGS),
        GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 9, GFLAGS),
-       GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 11, GFLAGS),
+       GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 11, GFLAGS),
 
        /* aclk_vio0 gates */
        GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 5, GFLAGS),
        GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS),
-       GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 11, GFLAGS),
+       GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 11, GFLAGS),
        GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS),
 
        /* aclk_vio1 gates */
        GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 7, GFLAGS),
        GATE(ACLK_ISP, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS),
-       GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 12, GFLAGS),
+       GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 12, GFLAGS),
 
        /* aclk_rga_pre gates */
        GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 0, GFLAGS),
-       GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 13, GFLAGS),
+       GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 13, GFLAGS),
 
        /*
         * Other ungrouped clocks.
@@ -762,6 +777,64 @@ static const char *rk3288_critical_clocks[] __initconst = {
        "hclk_peri",
 };
 
+#ifdef CONFIG_PM_SLEEP
+static void __iomem *rk3288_cru_base;
+
+/* Some CRU registers will be reset in maskrom when the system
+ * wakes up from fastboot.
+ * So save them before suspend, restore them after resume.
+ */
+static const int rk3288_saved_cru_reg_ids[] = {
+       RK3288_MODE_CON,
+       RK3288_CLKSEL_CON(0),
+       RK3288_CLKSEL_CON(1),
+       RK3288_CLKSEL_CON(10),
+       RK3288_CLKSEL_CON(33),
+       RK3288_CLKSEL_CON(37),
+};
+
+static u32 rk3288_saved_cru_regs[ARRAY_SIZE(rk3288_saved_cru_reg_ids)];
+
+static int rk3288_clk_suspend(void)
+{
+       int i, reg_id;
+
+       for (i = 0; i < ARRAY_SIZE(rk3288_saved_cru_reg_ids); i++) {
+               reg_id = rk3288_saved_cru_reg_ids[i];
+
+               rk3288_saved_cru_regs[i] =
+                               readl_relaxed(rk3288_cru_base + reg_id);
+       }
+       return 0;
+}
+
+static void rk3288_clk_resume(void)
+{
+       int i, reg_id;
+
+       for (i = ARRAY_SIZE(rk3288_saved_cru_reg_ids) - 1; i >= 0; i--) {
+               reg_id = rk3288_saved_cru_reg_ids[i];
+
+               writel_relaxed(rk3288_saved_cru_regs[i] | 0xffff0000,
+                              rk3288_cru_base + reg_id);
+       }
+}
+
+static struct syscore_ops rk3288_clk_syscore_ops = {
+       .suspend = rk3288_clk_suspend,
+       .resume = rk3288_clk_resume,
+};
+
+static void rk3288_clk_sleep_init(void __iomem *reg_base)
+{
+       rk3288_cru_base = reg_base;
+       register_syscore_ops(&rk3288_clk_syscore_ops);
+}
+
+#else /* CONFIG_PM_SLEEP */
+static void rk3288_clk_sleep_init(void __iomem *reg_base) {}
+#endif
+
 static void __init rk3288_clk_init(struct device_node *np)
 {
        void __iomem *reg_base;
@@ -810,5 +883,6 @@ static void __init rk3288_clk_init(struct device_node *np)
                                  ROCKCHIP_SOFTRST_HIWORD_MASK);
 
        rockchip_register_restart_notifier(RK3288_GLB_SRST_FST);
+       rk3288_clk_sleep_init(reg_base);
 }
 CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);
index 880a266f01431b3b9e7040565d3a3e81f0716a8b..20e05bbb3a6766bd8c630c9ce9cd16d16d81c6f8 100644 (file)
@@ -197,7 +197,8 @@ void __init rockchip_clk_register_plls(struct rockchip_pll_clock *list,
                                list->parent_names, list->num_parents,
                                reg_base, list->con_offset, grf_lock_offset,
                                list->lock_shift, list->mode_offset,
-                               list->mode_shift, list->rate_table, &clk_lock);
+                               list->mode_shift, list->rate_table,
+                               list->pll_flags, &clk_lock);
                if (IS_ERR(clk)) {
                        pr_err("%s: failed to register clock %s\n", __func__,
                                list->name);
@@ -244,9 +245,6 @@ void __init rockchip_clk_register_branches(
                                        list->div_flags, &clk_lock);
                        break;
                case branch_fraction_divider:
-                       /* keep all gates untouched for now */
-                       flags |= CLK_IGNORE_UNUSED;
-
                        clk = rockchip_clk_register_frac_branch(list->name,
                                list->parent_names, list->num_parents,
                                reg_base, list->muxdiv_offset, list->div_flags,
@@ -256,18 +254,12 @@ void __init rockchip_clk_register_branches(
                case branch_gate:
                        flags |= CLK_SET_RATE_PARENT;
 
-                       /* keep all gates untouched for now */
-                       flags |= CLK_IGNORE_UNUSED;
-
                        clk = clk_register_gate(NULL, list->name,
                                list->parent_names[0], flags,
                                reg_base + list->gate_offset,
                                list->gate_shift, list->gate_flags, &clk_lock);
                        break;
                case branch_composite:
-                       /* keep all gates untouched for now */
-                       flags |= CLK_IGNORE_UNUSED;
-
                        clk = rockchip_clk_register_branch(list->name,
                                list->parent_names, list->num_parents,
                                reg_base, list->muxdiv_offset, list->mux_shift,
@@ -277,6 +269,14 @@ void __init rockchip_clk_register_branches(
                                list->gate_offset, list->gate_shift,
                                list->gate_flags, flags, &clk_lock);
                        break;
+               case branch_mmc:
+                       clk = rockchip_clk_register_mmc(
+                               list->name,
+                               list->parent_names, list->num_parents,
+                               reg_base + list->muxdiv_offset,
+                               list->div_shift
+                       );
+                       break;
                }
 
                /* none of the cases above matched */
index ca009ab0a33a28ad507d83cf9cf0de183b33a09e..58d2e3bdf22fed499f8b4893eaf48690433d0298 100644 (file)
 #define RK3288_GLB_SRST_SND            0x1b4
 #define RK3288_SOFTRST_CON(x)          (x * 0x4 + 0x1b8)
 #define RK3288_MISC_CON                        0x1e8
+#define RK3288_SDMMC_CON0              0x200
+#define RK3288_SDMMC_CON1              0x204
+#define RK3288_SDIO0_CON0              0x208
+#define RK3288_SDIO0_CON1              0x20c
+#define RK3288_SDIO1_CON0              0x210
+#define RK3288_SDIO1_CON1              0x214
+#define RK3288_EMMC_CON0               0x218
+#define RK3288_EMMC_CON1               0x21c
 
 enum rockchip_pll_type {
        pll_rk3066,
@@ -62,6 +70,15 @@ enum rockchip_pll_type {
        .bwadj = (_nf >> 1),                    \
 }
 
+#define RK3066_PLL_RATE_BWADJ(_rate, _nr, _nf, _no, _bw)       \
+{                                                              \
+       .rate   = _rate##U,                                     \
+       .nr = _nr,                                              \
+       .nf = _nf,                                              \
+       .no = _no,                                              \
+       .bwadj = _bw,                                           \
+}
+
 struct rockchip_pll_rate_table {
        unsigned long rate;
        unsigned int nr;
@@ -81,7 +98,12 @@ struct rockchip_pll_rate_table {
  * @mode_shift: offset inside the mode-register for the mode of this pll.
  * @lock_shift: offset inside the lock register for the lock status.
  * @type: Type of PLL to be registered.
+ * @pll_flags: hardware-specific flags
  * @rate_table: Table of usable pll rates
+ *
+ * Flags:
+ * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
+ *     rate_table parameters and ajust them if necessary.
  */
 struct rockchip_pll_clock {
        unsigned int            id;
@@ -94,11 +116,14 @@ struct rockchip_pll_clock {
        int                     mode_shift;
        int                     lock_shift;
        enum rockchip_pll_type  type;
+       u8                      pll_flags;
        struct rockchip_pll_rate_table *rate_table;
 };
 
+#define ROCKCHIP_PLL_SYNC_RATE         BIT(0)
+
 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift,  \
-               _lshift, _rtable)                                       \
+               _lshift, _pflags, _rtable)                              \
        {                                                               \
                .id             = _id,                                  \
                .type           = _type,                                \
@@ -110,6 +135,7 @@ struct rockchip_pll_clock {
                .mode_offset    = _mode,                                \
                .mode_shift     = _mshift,                              \
                .lock_shift     = _lshift,                              \
+               .pll_flags      = _pflags,                              \
                .rate_table     = _rtable,                              \
        }
 
@@ -118,7 +144,7 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
                void __iomem *base, int con_offset, int grf_lock_offset,
                int lock_shift, int reg_mode, int mode_shift,
                struct rockchip_pll_rate_table *rate_table,
-               spinlock_t *lock);
+               u8 clk_pll_flags, spinlock_t *lock);
 
 struct rockchip_cpuclk_clksel {
        int reg;
@@ -152,6 +178,10 @@ struct clk *rockchip_clk_register_cpuclk(const char *name,
                        const struct rockchip_cpuclk_rate_table *rates,
                        int nrates, void __iomem *reg_base, spinlock_t *lock);
 
+struct clk *rockchip_clk_register_mmc(const char *name,
+                               const char **parent_names, u8 num_parents,
+                               void __iomem *reg, int shift);
+
 #define PNAME(x) static const char *x[] __initconst
 
 enum rockchip_clk_branch_type {
@@ -160,6 +190,7 @@ enum rockchip_clk_branch_type {
        branch_divider,
        branch_fraction_divider,
        branch_gate,
+       branch_mmc,
 };
 
 struct rockchip_clk_branch {
@@ -352,6 +383,16 @@ struct rockchip_clk_branch {
                .gate_flags     = gf,                           \
        }
 
+#define MMC(_id, cname, pname, offset, shift)                  \
+       {                                                       \
+               .id             = _id,                          \
+               .branch_type    = branch_mmc,                   \
+               .name           = cname,                        \
+               .parent_names   = (const char *[]){ pname },    \
+               .num_parents    = 1,                            \
+               .muxdiv_offset  = offset,                       \
+               .div_shift      = shift,                        \
+       }
 
 void rockchip_clk_init(struct device_node *np, void __iomem *base,
                       unsigned long nr_clks);
index 6fb4bc602e8ac467d4489e51f30b642e5771dda7..006c6f294310d51e804bfda91b76e3eeb211b7e7 100644 (file)
@@ -5,6 +5,7 @@
 obj-$(CONFIG_COMMON_CLK)       += clk.o clk-pll.o
 obj-$(CONFIG_SOC_EXYNOS3250)   += clk-exynos3250.o
 obj-$(CONFIG_ARCH_EXYNOS4)     += clk-exynos4.o
+obj-$(CONFIG_SOC_EXYNOS4415)   += clk-exynos4415.o
 obj-$(CONFIG_SOC_EXYNOS5250)   += clk-exynos5250.o
 obj-$(CONFIG_SOC_EXYNOS5260)   += clk-exynos5260.o
 obj-$(CONFIG_SOC_EXYNOS5410)   += clk-exynos5410.o
@@ -12,6 +13,7 @@ obj-$(CONFIG_SOC_EXYNOS5420)  += clk-exynos5420.o
 obj-$(CONFIG_SOC_EXYNOS5440)   += clk-exynos5440.o
 obj-$(CONFIG_ARCH_EXYNOS)      += clk-exynos-audss.o
 obj-$(CONFIG_ARCH_EXYNOS)      += clk-exynos-clkout.o
+obj-$(CONFIG_ARCH_EXYNOS7)     += clk-exynos7.o
 obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
 obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
 obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
index acce708ace18e02997a004aebd6b2b0fee17ef20..f2c2ccce49bb1ad00f7502e9d4e4236fc6bcbe54 100644 (file)
@@ -29,6 +29,13 @@ static DEFINE_SPINLOCK(lock);
 static struct clk **clk_table;
 static void __iomem *reg_base;
 static struct clk_onecell_data clk_data;
+/*
+ * On Exynos5420 this will be a clock which has to be enabled before any
+ * access to audss registers. Typically a child of EPLL.
+ *
+ * On other platforms this will be -ENODEV.
+ */
+static struct clk *epll;
 
 #define ASS_CLK_SRC 0x0
 #define ASS_CLK_DIV 0x4
@@ -98,6 +105,8 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
                dev_err(&pdev->dev, "failed to map audss registers\n");
                return PTR_ERR(reg_base);
        }
+       /* EPLL don't have to be enabled for boards other than Exynos5420 */
+       epll = ERR_PTR(-ENODEV);
 
        clk_table = devm_kzalloc(&pdev->dev,
                                sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
@@ -115,8 +124,20 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
        pll_in = devm_clk_get(&pdev->dev, "pll_in");
        if (!IS_ERR(pll_ref))
                mout_audss_p[0] = __clk_get_name(pll_ref);
-       if (!IS_ERR(pll_in))
+       if (!IS_ERR(pll_in)) {
                mout_audss_p[1] = __clk_get_name(pll_in);
+
+               if (variant == TYPE_EXYNOS5420) {
+                       epll = pll_in;
+
+                       ret = clk_prepare_enable(epll);
+                       if (ret) {
+                               dev_err(&pdev->dev,
+                                               "failed to prepare the epll clock\n");
+                               return ret;
+                       }
+               }
+       }
        clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
                                mout_audss_p, ARRAY_SIZE(mout_audss_p),
                                CLK_SET_RATE_NO_REPARENT,
@@ -203,6 +224,9 @@ unregister:
                        clk_unregister(clk_table[i]);
        }
 
+       if (!IS_ERR(epll))
+               clk_disable_unprepare(epll);
+
        return ret;
 }
 
@@ -210,6 +234,10 @@ static int exynos_audss_clk_remove(struct platform_device *pdev)
 {
        int i;
 
+#ifdef CONFIG_PM_SLEEP
+       unregister_syscore_ops(&exynos_audss_clk_syscore_ops);
+#endif
+
        of_clk_del_provider(pdev->dev.of_node);
 
        for (i = 0; i < clk_data.clk_num; i++) {
@@ -217,6 +245,9 @@ static int exynos_audss_clk_remove(struct platform_device *pdev)
                        clk_unregister(clk_table[i]);
        }
 
+       if (!IS_ERR(epll))
+               clk_disable_unprepare(epll);
+
        return 0;
 }
 
index 940f02837b824869932d3e6b63462942577a708c..88e8c6bbd77ff8ea6919bc6c1ef7bd3fdc1324ae 100644 (file)
@@ -505,7 +505,7 @@ static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata
 /* fixed rate clocks generated inside the soc */
 static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
        FRATE(0, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),
-       FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
+       FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", "hdmi", 0, 27000000),
        FRATE(0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
 };
 
diff --git a/drivers/clk/samsung/clk-exynos4415.c b/drivers/clk/samsung/clk-exynos4415.c
new file mode 100644 (file)
index 0000000..2123fc2
--- /dev/null
@@ -0,0 +1,1144 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Chanwoo Choi <cw00.choi@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos4415 SoC.
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/syscore_ops.h>
+
+#include <dt-bindings/clock/exynos4415.h>
+
+#include "clk.h"
+#include "clk-pll.h"
+
+#define SRC_LEFTBUS            0x4200
+#define DIV_LEFTBUS            0x4500
+#define GATE_IP_LEFTBUS                0x4800
+#define GATE_IP_IMAGE          0x4930
+#define SRC_RIGHTBUS           0x8200
+#define DIV_RIGHTBUS           0x8500
+#define GATE_IP_RIGHTBUS       0x8800
+#define GATE_IP_PERIR          0x8960
+#define EPLL_LOCK              0xc010
+#define G3D_PLL_LOCK           0xc020
+#define DISP_PLL_LOCK          0xc030
+#define ISP_PLL_LOCK           0xc040
+#define EPLL_CON0              0xc110
+#define EPLL_CON1              0xc114
+#define EPLL_CON2              0xc118
+#define G3D_PLL_CON0           0xc120
+#define G3D_PLL_CON1           0xc124
+#define G3D_PLL_CON2           0xc128
+#define ISP_PLL_CON0           0xc130
+#define ISP_PLL_CON1           0xc134
+#define ISP_PLL_CON2           0xc138
+#define DISP_PLL_CON0          0xc140
+#define DISP_PLL_CON1          0xc144
+#define DISP_PLL_CON2          0xc148
+#define SRC_TOP0               0xc210
+#define SRC_TOP1               0xc214
+#define SRC_CAM                        0xc220
+#define SRC_TV                 0xc224
+#define SRC_MFC                        0xc228
+#define SRC_G3D                        0xc22c
+#define SRC_LCD                        0xc234
+#define SRC_ISP                        0xc238
+#define SRC_MAUDIO             0xc23c
+#define SRC_FSYS               0xc240
+#define SRC_PERIL0             0xc250
+#define SRC_PERIL1             0xc254
+#define SRC_CAM1               0xc258
+#define SRC_TOP_ISP0           0xc25c
+#define SRC_TOP_ISP1           0xc260
+#define SRC_MASK_TOP           0xc310
+#define SRC_MASK_CAM           0xc320
+#define SRC_MASK_TV            0xc324
+#define SRC_MASK_LCD           0xc334
+#define SRC_MASK_ISP           0xc338
+#define SRC_MASK_MAUDIO                0xc33c
+#define SRC_MASK_FSYS          0xc340
+#define SRC_MASK_PERIL0                0xc350
+#define SRC_MASK_PERIL1                0xc354
+#define DIV_TOP                        0xc510
+#define DIV_CAM                        0xc520
+#define DIV_TV                 0xc524
+#define DIV_MFC                        0xc528
+#define DIV_G3D                        0xc52c
+#define DIV_LCD                        0xc534
+#define DIV_ISP                        0xc538
+#define DIV_MAUDIO             0xc53c
+#define DIV_FSYS0              0xc540
+#define DIV_FSYS1              0xc544
+#define DIV_FSYS2              0xc548
+#define DIV_PERIL0             0xc550
+#define DIV_PERIL1             0xc554
+#define DIV_PERIL2             0xc558
+#define DIV_PERIL3             0xc55c
+#define DIV_PERIL4             0xc560
+#define DIV_PERIL5             0xc564
+#define DIV_CAM1               0xc568
+#define DIV_TOP_ISP1           0xc56c
+#define DIV_TOP_ISP0           0xc570
+#define CLKDIV2_RATIO          0xc580
+#define GATE_SCLK_CAM          0xc820
+#define GATE_SCLK_TV           0xc824
+#define GATE_SCLK_MFC          0xc828
+#define GATE_SCLK_G3D          0xc82c
+#define GATE_SCLK_LCD          0xc834
+#define GATE_SCLK_MAUDIO       0xc83c
+#define GATE_SCLK_FSYS         0xc840
+#define GATE_SCLK_PERIL                0xc850
+#define GATE_IP_CAM            0xc920
+#define GATE_IP_TV             0xc924
+#define GATE_IP_MFC            0xc928
+#define GATE_IP_G3D            0xc92c
+#define GATE_IP_LCD            0xc934
+#define GATE_IP_FSYS           0xc940
+#define GATE_IP_PERIL          0xc950
+#define GATE_BLOCK             0xc970
+#define APLL_LOCK              0x14000
+#define APLL_CON0              0x14100
+#define SRC_CPU                        0x14200
+#define DIV_CPU0               0x14500
+#define DIV_CPU1               0x14504
+
+enum exynos4415_plls {
+       apll, epll, g3d_pll, isp_pll, disp_pll,
+       nr_plls,
+};
+
+static struct samsung_clk_provider *exynos4415_ctx;
+
+/*
+ * Support for CMU save/restore across system suspends
+ */
+#ifdef CONFIG_PM_SLEEP
+static struct samsung_clk_reg_dump *exynos4415_clk_regs;
+
+static unsigned long exynos4415_cmu_clk_regs[] __initdata = {
+       SRC_LEFTBUS,
+       DIV_LEFTBUS,
+       GATE_IP_LEFTBUS,
+       GATE_IP_IMAGE,
+       SRC_RIGHTBUS,
+       DIV_RIGHTBUS,
+       GATE_IP_RIGHTBUS,
+       GATE_IP_PERIR,
+       EPLL_LOCK,
+       G3D_PLL_LOCK,
+       DISP_PLL_LOCK,
+       ISP_PLL_LOCK,
+       EPLL_CON0,
+       EPLL_CON1,
+       EPLL_CON2,
+       G3D_PLL_CON0,
+       G3D_PLL_CON1,
+       G3D_PLL_CON2,
+       ISP_PLL_CON0,
+       ISP_PLL_CON1,
+       ISP_PLL_CON2,
+       DISP_PLL_CON0,
+       DISP_PLL_CON1,
+       DISP_PLL_CON2,
+       SRC_TOP0,
+       SRC_TOP1,
+       SRC_CAM,
+       SRC_TV,
+       SRC_MFC,
+       SRC_G3D,
+       SRC_LCD,
+       SRC_ISP,
+       SRC_MAUDIO,
+       SRC_FSYS,
+       SRC_PERIL0,
+       SRC_PERIL1,
+       SRC_CAM1,
+       SRC_TOP_ISP0,
+       SRC_TOP_ISP1,
+       SRC_MASK_TOP,
+       SRC_MASK_CAM,
+       SRC_MASK_TV,
+       SRC_MASK_LCD,
+       SRC_MASK_ISP,
+       SRC_MASK_MAUDIO,
+       SRC_MASK_FSYS,
+       SRC_MASK_PERIL0,
+       SRC_MASK_PERIL1,
+       DIV_TOP,
+       DIV_CAM,
+       DIV_TV,
+       DIV_MFC,
+       DIV_G3D,
+       DIV_LCD,
+       DIV_ISP,
+       DIV_MAUDIO,
+       DIV_FSYS0,
+       DIV_FSYS1,
+       DIV_FSYS2,
+       DIV_PERIL0,
+       DIV_PERIL1,
+       DIV_PERIL2,
+       DIV_PERIL3,
+       DIV_PERIL4,
+       DIV_PERIL5,
+       DIV_CAM1,
+       DIV_TOP_ISP1,
+       DIV_TOP_ISP0,
+       CLKDIV2_RATIO,
+       GATE_SCLK_CAM,
+       GATE_SCLK_TV,
+       GATE_SCLK_MFC,
+       GATE_SCLK_G3D,
+       GATE_SCLK_LCD,
+       GATE_SCLK_MAUDIO,
+       GATE_SCLK_FSYS,
+       GATE_SCLK_PERIL,
+       GATE_IP_CAM,
+       GATE_IP_TV,
+       GATE_IP_MFC,
+       GATE_IP_G3D,
+       GATE_IP_LCD,
+       GATE_IP_FSYS,
+       GATE_IP_PERIL,
+       GATE_BLOCK,
+       APLL_LOCK,
+       APLL_CON0,
+       SRC_CPU,
+       DIV_CPU0,
+       DIV_CPU1,
+};
+
+static int exynos4415_clk_suspend(void)
+{
+       samsung_clk_save(exynos4415_ctx->reg_base, exynos4415_clk_regs,
+                               ARRAY_SIZE(exynos4415_cmu_clk_regs));
+
+       return 0;
+}
+
+static void exynos4415_clk_resume(void)
+{
+       samsung_clk_restore(exynos4415_ctx->reg_base, exynos4415_clk_regs,
+                               ARRAY_SIZE(exynos4415_cmu_clk_regs));
+}
+
+static struct syscore_ops exynos4415_clk_syscore_ops = {
+       .suspend = exynos4415_clk_suspend,
+       .resume = exynos4415_clk_resume,
+};
+
+static void exynos4415_clk_sleep_init(void)
+{
+       exynos4415_clk_regs =
+               samsung_clk_alloc_reg_dump(exynos4415_cmu_clk_regs,
+                                       ARRAY_SIZE(exynos4415_cmu_clk_regs));
+       if (!exynos4415_clk_regs) {
+               pr_warn("%s: Failed to allocate sleep save data\n", __func__);
+               return;
+       }
+
+       register_syscore_ops(&exynos4415_clk_syscore_ops);
+}
+#else
+static inline void exynos4415_clk_sleep_init(void) { }
+#endif
+
+/* list of all parent clock list */
+PNAME(mout_g3d_pllsrc_p)       = { "fin_pll", };
+
+PNAME(mout_apll_p)             = { "fin_pll", "fout_apll", };
+PNAME(mout_g3d_pll_p)          = { "fin_pll", "fout_g3d_pll", };
+PNAME(mout_isp_pll_p)          = { "fin_pll", "fout_isp_pll", };
+PNAME(mout_disp_pll_p)         = { "fin_pll", "fout_disp_pll", };
+
+PNAME(mout_mpll_user_p)                = { "fin_pll", "div_mpll_pre", };
+PNAME(mout_epll_p)             = { "fin_pll", "fout_epll", };
+PNAME(mout_core_p)             = { "mout_apll", "mout_mpll_user_c", };
+PNAME(mout_hpm_p)              = { "mout_apll", "mout_mpll_user_c", };
+
+PNAME(mout_ebi_p)              = { "div_aclk_200", "div_aclk_160", };
+PNAME(mout_ebi_1_p)            = { "mout_ebi", "mout_g3d_pll", };
+
+PNAME(mout_gdl_p)              = { "mout_mpll_user_l", };
+PNAME(mout_gdr_p)              = { "mout_mpll_user_r", };
+
+PNAME(mout_aclk_266_p)         = { "mout_mpll_user_t", "mout_g3d_pll", };
+
+PNAME(group_epll_g3dpll_p)     = { "mout_epll", "mout_g3d_pll" };
+PNAME(group_sclk_p)            = { "xxti", "xusbxti",
+                                   "none", "mout_isp_pll",
+                                   "none", "none", "div_mpll_pre",
+                                   "mout_epll", "mout_g3d_pll", };
+PNAME(group_spdif_p)           = { "mout_audio0", "mout_audio1",
+                                   "mout_audio2", "spdif_extclk", };
+PNAME(group_sclk_audio2_p)     = { "audiocdclk2", "none",
+                                   "none", "mout_isp_pll",
+                                   "mout_disp_pll", "xusbxti",
+                                   "div_mpll_pre", "mout_epll",
+                                   "mout_g3d_pll", };
+PNAME(group_sclk_audio1_p)     = { "audiocdclk1", "none",
+                                   "none", "mout_isp_pll",
+                                   "mout_disp_pll", "xusbxti",
+                                   "div_mpll_pre", "mout_epll",
+                                   "mout_g3d_pll", };
+PNAME(group_sclk_audio0_p)     = { "audiocdclk0", "none",
+                                   "none", "mout_isp_pll",
+                                   "mout_disp_pll", "xusbxti",
+                                   "div_mpll_pre", "mout_epll",
+                                   "mout_g3d_pll", };
+PNAME(group_fimc_lclk_p)       = { "xxti", "xusbxti",
+                                   "none", "mout_isp_pll",
+                                   "none", "mout_disp_pll",
+                                   "mout_mpll_user_t", "mout_epll",
+                                   "mout_g3d_pll", };
+PNAME(group_sclk_fimd0_p)      = { "xxti", "xusbxti",
+                                   "m_bitclkhsdiv4_4l", "mout_isp_pll",
+                                   "mout_disp_pll", "sclk_hdmiphy",
+                                   "div_mpll_pre", "mout_epll",
+                                   "mout_g3d_pll", };
+PNAME(mout_hdmi_p)             = { "sclk_pixel", "sclk_hdmiphy" };
+PNAME(mout_mfc_p)              = { "mout_mfc_0", "mout_mfc_1" };
+PNAME(mout_g3d_p)              = { "mout_g3d_0", "mout_g3d_1" };
+PNAME(mout_jpeg_p)             = { "mout_jpeg_0", "mout_jpeg_1" };
+PNAME(mout_jpeg1_p)            = { "mout_epll", "mout_g3d_pll" };
+PNAME(group_aclk_isp0_300_p)   = { "mout_isp_pll", "div_mpll_pre" };
+PNAME(group_aclk_isp0_400_user_p) = { "fin_pll", "div_aclk_400_mcuisp" };
+PNAME(group_aclk_isp0_300_user_p) = { "fin_pll", "mout_aclk_isp0_300" };
+PNAME(group_aclk_isp1_300_user_p) = { "fin_pll", "mout_aclk_isp1_300" };
+PNAME(group_mout_mpll_user_t_p)        = { "mout_mpll_user_t" };
+
+static struct samsung_fixed_factor_clock exynos4415_fixed_factor_clks[] __initdata = {
+       /* HACK: fin_pll hardcoded to xusbxti until detection is implemented. */
+       FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),
+};
+
+static struct samsung_fixed_rate_clock exynos4415_fixed_rate_clks[] __initdata = {
+       FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
+};
+
+static struct samsung_mux_clock exynos4415_mux_clks[] __initdata = {
+       /*
+        * NOTE: Following table is sorted by register address in ascending
+        * order and then bitfield shift in descending order, as it is done
+        * in the User's Manual. When adding new entries, please make sure
+        * that the order is preserved, to avoid merge conflicts and make
+        * further work with defined data easier.
+        */
+
+       /* SRC_LEFTBUS */
+       MUX(CLK_MOUT_MPLL_USER_L, "mout_mpll_user_l", mout_mpll_user_p,
+               SRC_LEFTBUS, 4, 1),
+       MUX(CLK_MOUT_GDL, "mout_gdl", mout_gdl_p, SRC_LEFTBUS, 0, 1),
+
+       /* SRC_RIGHTBUS */
+       MUX(CLK_MOUT_MPLL_USER_R, "mout_mpll_user_r", mout_mpll_user_p,
+               SRC_RIGHTBUS, 4, 1),
+       MUX(CLK_MOUT_GDR, "mout_gdr", mout_gdr_p, SRC_RIGHTBUS, 0, 1),
+
+       /* SRC_TOP0 */
+       MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1),
+       MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_mout_mpll_user_t_p,
+               SRC_TOP0, 24, 1),
+       MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_mout_mpll_user_t_p,
+               SRC_TOP0, 20, 1),
+       MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_mout_mpll_user_t_p,
+               SRC_TOP0, 16, 1),
+       MUX(CLK_MOUT_ACLK_266, "mout_aclk_266", mout_aclk_266_p,
+               SRC_TOP0, 12, 1),
+       MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
+               SRC_TOP0, 8, 1),
+       MUX(CLK_MOUT_EPLL, "mout_epll", mout_epll_p, SRC_TOP0, 4, 1),
+       MUX(CLK_MOUT_EBI_1, "mout_ebi_1", mout_ebi_1_p, SRC_TOP0, 0, 1),
+
+       /* SRC_TOP1 */
+       MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p,
+               SRC_TOP1, 28, 1),
+       MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p,
+               SRC_TOP1, 16, 1),
+       MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t", mout_mpll_user_p,
+               SRC_TOP1, 12, 1),
+       MUX(CLK_MOUT_ACLK_400_MCUISP, "mout_aclk_400_mcuisp",
+               group_mout_mpll_user_t_p, SRC_TOP1, 8, 1),
+       MUX(CLK_MOUT_G3D_PLLSRC, "mout_g3d_pllsrc", mout_g3d_pllsrc_p,
+               SRC_TOP1, 0, 1),
+
+       /* SRC_CAM */
+       MUX(CLK_MOUT_CSIS1, "mout_csis1", group_fimc_lclk_p, SRC_CAM, 28, 4),
+       MUX(CLK_MOUT_CSIS0, "mout_csis0", group_fimc_lclk_p, SRC_CAM, 24, 4),
+       MUX(CLK_MOUT_CAM1, "mout_cam1", group_fimc_lclk_p, SRC_CAM, 20, 4),
+       MUX(CLK_MOUT_FIMC3_LCLK, "mout_fimc3_lclk", group_fimc_lclk_p, SRC_CAM,
+               12, 4),
+       MUX(CLK_MOUT_FIMC2_LCLK, "mout_fimc2_lclk", group_fimc_lclk_p, SRC_CAM,
+               8, 4),
+       MUX(CLK_MOUT_FIMC1_LCLK, "mout_fimc1_lclk", group_fimc_lclk_p, SRC_CAM,
+               4, 4),
+       MUX(CLK_MOUT_FIMC0_LCLK, "mout_fimc0_lclk", group_fimc_lclk_p, SRC_CAM,
+               0, 4),
+
+       /* SRC_TV */
+       MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
+
+       /* SRC_MFC */
+       MUX(CLK_MOUT_MFC, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
+       MUX(CLK_MOUT_MFC_1, "mout_mfc_1", group_epll_g3dpll_p, SRC_MFC, 4, 1),
+       MUX(CLK_MOUT_MFC_0, "mout_mfc_0", group_mout_mpll_user_t_p, SRC_MFC, 0,
+               1),
+
+       /* SRC_G3D */
+       MUX(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1),
+       MUX(CLK_MOUT_G3D_1, "mout_g3d_1", group_epll_g3dpll_p, SRC_G3D, 4, 1),
+       MUX(CLK_MOUT_G3D_0, "mout_g3d_0", group_mout_mpll_user_t_p, SRC_G3D, 0,
+               1),
+
+       /* SRC_LCD */
+       MUX(CLK_MOUT_MIPI0, "mout_mipi0", group_fimc_lclk_p, SRC_LCD, 12, 4),
+       MUX(CLK_MOUT_FIMD0, "mout_fimd0", group_sclk_fimd0_p, SRC_LCD, 0, 4),
+
+       /* SRC_ISP */
+       MUX(CLK_MOUT_TSADC_ISP, "mout_tsadc_isp", group_fimc_lclk_p, SRC_ISP,
+               16, 4),
+       MUX(CLK_MOUT_UART_ISP, "mout_uart_isp", group_fimc_lclk_p, SRC_ISP,
+               12, 4),
+       MUX(CLK_MOUT_SPI1_ISP, "mout_spi1_isp", group_fimc_lclk_p, SRC_ISP,
+               8, 4),
+       MUX(CLK_MOUT_SPI0_ISP, "mout_spi0_isp", group_fimc_lclk_p, SRC_ISP,
+               4, 4),
+       MUX(CLK_MOUT_PWM_ISP, "mout_pwm_isp", group_fimc_lclk_p, SRC_ISP,
+               0, 4),
+
+       /* SRC_MAUDIO */
+       MUX(CLK_MOUT_AUDIO0, "mout_audio0", group_sclk_audio0_p, SRC_MAUDIO,
+               0, 4),
+
+       /* SRC_FSYS */
+       MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
+       MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4),
+       MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),
+       MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
+
+       /* SRC_PERIL0 */
+       MUX(CLK_MOUT_UART3, "mout_uart3", group_sclk_p, SRC_PERIL0, 12, 4),
+       MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),
+       MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
+       MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
+
+       /* SRC_PERIL1 */
+       MUX(CLK_MOUT_SPI2, "mout_spi2", group_sclk_p, SRC_PERIL1, 24, 4),
+       MUX(CLK_MOUT_SPI1, "mout_spi1", group_sclk_p, SRC_PERIL1, 20, 4),
+       MUX(CLK_MOUT_SPI0, "mout_spi0", group_sclk_p, SRC_PERIL1, 16, 4),
+       MUX(CLK_MOUT_SPDIF, "mout_spdif", group_spdif_p, SRC_PERIL1, 8, 4),
+       MUX(CLK_MOUT_AUDIO2, "mout_audio2", group_sclk_audio2_p, SRC_PERIL1,
+               4, 4),
+       MUX(CLK_MOUT_AUDIO1, "mout_audio1", group_sclk_audio1_p, SRC_PERIL1,
+               0, 4),
+
+       /* SRC_CPU */
+       MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p,
+               SRC_CPU, 24, 1),
+       MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1),
+       MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1, 0,
+               CLK_MUX_READ_ONLY),
+       MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
+               CLK_SET_RATE_PARENT, 0),
+
+       /* SRC_CAM1 */
+       MUX(CLK_MOUT_PXLASYNC_CSIS1_FIMC, "mout_pxlasync_csis1",
+               group_fimc_lclk_p, SRC_CAM1, 20, 1),
+       MUX(CLK_MOUT_PXLASYNC_CSIS0_FIMC, "mout_pxlasync_csis0",
+               group_fimc_lclk_p, SRC_CAM1, 16, 1),
+       MUX(CLK_MOUT_JPEG, "mout_jpeg", mout_jpeg_p, SRC_CAM1, 8, 1),
+       MUX(CLK_MOUT_JPEG1, "mout_jpeg_1", mout_jpeg1_p, SRC_CAM1, 4, 1),
+       MUX(CLK_MOUT_JPEG0, "mout_jpeg_0", group_mout_mpll_user_t_p, SRC_CAM1,
+               0, 1),
+
+       /* SRC_TOP_ISP0 */
+       MUX(CLK_MOUT_ACLK_ISP0_300, "mout_aclk_isp0_300",
+               group_aclk_isp0_300_p, SRC_TOP_ISP0, 8, 1),
+       MUX(CLK_MOUT_ACLK_ISP0_400, "mout_aclk_isp0_400_user",
+               group_aclk_isp0_400_user_p, SRC_TOP_ISP0, 4, 1),
+       MUX(CLK_MOUT_ACLK_ISP0_300_USER, "mout_aclk_isp0_300_user",
+               group_aclk_isp0_300_user_p, SRC_TOP_ISP0, 0, 1),
+
+       /* SRC_TOP_ISP1 */
+       MUX(CLK_MOUT_ACLK_ISP1_300, "mout_aclk_isp1_300",
+               group_aclk_isp0_300_p, SRC_TOP_ISP1, 4, 1),
+       MUX(CLK_MOUT_ACLK_ISP1_300_USER, "mout_aclk_isp1_300_user",
+               group_aclk_isp1_300_user_p, SRC_TOP_ISP1, 0, 1),
+};
+
+static struct samsung_div_clock exynos4415_div_clks[] __initdata = {
+       /*
+        * NOTE: Following table is sorted by register address in ascending
+        * order and then bitfield shift in descending order, as it is done
+        * in the User's Manual. When adding new entries, please make sure
+        * that the order is preserved, to avoid merge conflicts and make
+        * further work with defined data easier.
+        */
+
+       /* DIV_LEFTBUS */
+       DIV(CLK_DIV_GPL, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
+       DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 4),
+
+       /* DIV_RIGHTBUS */
+       DIV(CLK_DIV_GPR, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
+       DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 4),
+
+       /* DIV_TOP */
+       DIV(CLK_DIV_ACLK_400_MCUISP, "div_aclk_400_mcuisp",
+               "mout_aclk_400_mcuisp", DIV_TOP, 24, 3),
+       DIV(CLK_DIV_EBI, "div_ebi", "mout_ebi_1", DIV_TOP, 16, 3),
+       DIV(CLK_DIV_ACLK_200, "div_aclk_200", "mout_aclk_200", DIV_TOP, 12, 3),
+       DIV(CLK_DIV_ACLK_160, "div_aclk_160", "mout_aclk_160", DIV_TOP, 8, 3),
+       DIV(CLK_DIV_ACLK_100, "div_aclk_100", "mout_aclk_100", DIV_TOP, 4, 4),
+       DIV(CLK_DIV_ACLK_266, "div_aclk_266", "mout_aclk_266", DIV_TOP, 0, 3),
+
+       /* DIV_CAM */
+       DIV(CLK_DIV_CSIS1, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
+       DIV(CLK_DIV_CSIS0, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
+       DIV(CLK_DIV_CAM1, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
+       DIV(CLK_DIV_FIMC3_LCLK, "div_fimc3_lclk", "mout_fimc3_lclk", DIV_CAM,
+               12, 4),
+       DIV(CLK_DIV_FIMC2_LCLK, "div_fimc2_lclk", "mout_fimc2_lclk", DIV_CAM,
+               8, 4),
+       DIV(CLK_DIV_FIMC1_LCLK, "div_fimc1_lclk", "mout_fimc1_lclk", DIV_CAM,
+               4, 4),
+       DIV(CLK_DIV_FIMC0_LCLK, "div_fimc0_lclk", "mout_fimc0_lclk", DIV_CAM,
+               0, 4),
+
+       /* DIV_TV */
+       DIV(CLK_DIV_TV_BLK, "div_tv_blk", "mout_g3d_pll", DIV_TV, 0, 4),
+
+       /* DIV_MFC */
+       DIV(CLK_DIV_MFC, "div_mfc", "mout_mfc", DIV_MFC, 0, 4),
+
+       /* DIV_G3D */
+       DIV(CLK_DIV_G3D, "div_g3d", "mout_g3d", DIV_G3D, 0, 4),
+
+       /* DIV_LCD */
+       DIV_F(CLK_DIV_MIPI0_PRE, "div_mipi0_pre", "div_mipi0", DIV_LCD, 20, 4,
+               CLK_SET_RATE_PARENT, 0),
+       DIV(CLK_DIV_MIPI0, "div_mipi0", "mout_mipi0", DIV_LCD, 16, 4),
+       DIV(CLK_DIV_FIMD0, "div_fimd0", "mout_fimd0", DIV_LCD, 0, 4),
+
+       /* DIV_ISP */
+       DIV(CLK_DIV_UART_ISP, "div_uart_isp", "mout_uart_isp", DIV_ISP, 28, 4),
+       DIV_F(CLK_DIV_SPI1_ISP_PRE, "div_spi1_isp_pre", "div_spi1_isp",
+               DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0),
+       DIV(CLK_DIV_SPI1_ISP, "div_spi1_isp", "mout_spi1_isp", DIV_ISP, 16, 4),
+       DIV_F(CLK_DIV_SPI0_ISP_PRE, "div_spi0_isp_pre", "div_spi0_isp",
+               DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0),
+       DIV(CLK_DIV_SPI0_ISP, "div_spi0_isp", "mout_spi0_isp", DIV_ISP, 4, 4),
+       DIV(CLK_DIV_PWM_ISP, "div_pwm_isp", "mout_pwm_isp", DIV_ISP, 0, 4),
+
+       /* DIV_MAUDIO */
+       DIV(CLK_DIV_PCM0, "div_pcm0", "div_audio0", DIV_MAUDIO, 4, 8),
+       DIV(CLK_DIV_AUDIO0, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
+
+       /* DIV_FSYS0 */
+       DIV_F(CLK_DIV_TSADC_PRE, "div_tsadc_pre", "div_tsadc", DIV_FSYS0, 8, 8,
+               CLK_SET_RATE_PARENT, 0),
+       DIV(CLK_DIV_TSADC, "div_tsadc", "mout_tsadc", DIV_FSYS0, 0, 4),
+
+       /* DIV_FSYS1 */
+       DIV_F(CLK_DIV_MMC1_PRE, "div_mmc1_pre", "div_mmc1", DIV_FSYS1, 24, 8,
+               CLK_SET_RATE_PARENT, 0),
+       DIV(CLK_DIV_MMC1, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
+       DIV_F(CLK_DIV_MMC0_PRE, "div_mmc0_pre", "div_mmc0", DIV_FSYS1, 8, 8,
+               CLK_SET_RATE_PARENT, 0),
+       DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
+
+       /* DIV_FSYS2 */
+       DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8,
+               CLK_SET_RATE_PARENT, 0),
+       DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4,
+               CLK_SET_RATE_PARENT, 0),
+
+       /* DIV_PERIL0 */
+       DIV(CLK_DIV_UART3, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
+       DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
+       DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
+       DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
+
+       /* DIV_PERIL1 */
+       DIV_F(CLK_DIV_SPI1_PRE, "div_spi1_pre", "div_spi1", DIV_PERIL1, 24, 8,
+               CLK_SET_RATE_PARENT, 0),
+       DIV(CLK_DIV_SPI1, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
+       DIV_F(CLK_DIV_SPI0_PRE, "div_spi0_pre", "div_spi0", DIV_PERIL1, 8, 8,
+               CLK_SET_RATE_PARENT, 0),
+       DIV(CLK_DIV_SPI0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
+
+       /* DIV_PERIL2 */
+       DIV_F(CLK_DIV_SPI2_PRE, "div_spi2_pre", "div_spi2", DIV_PERIL2, 8, 8,
+               CLK_SET_RATE_PARENT, 0),
+       DIV(CLK_DIV_SPI2, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4),
+
+       /* DIV_PERIL4 */
+       DIV(CLK_DIV_PCM2, "div_pcm2", "div_audio2", DIV_PERIL4, 20, 8),
+       DIV(CLK_DIV_AUDIO2, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
+       DIV(CLK_DIV_PCM1, "div_pcm1", "div_audio1", DIV_PERIL4, 20, 8),
+       DIV(CLK_DIV_AUDIO1, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
+
+       /* DIV_PERIL5 */
+       DIV(CLK_DIV_I2S1, "div_i2s1", "div_audio1", DIV_PERIL5, 0, 6),
+
+       /* DIV_CAM1 */
+       DIV(CLK_DIV_PXLASYNC_CSIS1_FIMC, "div_pxlasync_csis1_fimc",
+               "mout_pxlasync_csis1", DIV_CAM1, 24, 4),
+       DIV(CLK_DIV_PXLASYNC_CSIS0_FIMC, "div_pxlasync_csis0_fimc",
+               "mout_pxlasync_csis0", DIV_CAM1, 20, 4),
+       DIV(CLK_DIV_JPEG, "div_jpeg", "mout_jpeg", DIV_CAM1, 0, 4),
+
+       /* DIV_CPU0 */
+       DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),
+       DIV_F(CLK_DIV_APLL, "div_apll", "mout_apll", DIV_CPU0, 24, 3,
+                       CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+       DIV(CLK_DIV_PCLK_DBG, "div_pclk_dbg", "div_core2", DIV_CPU0, 20, 3),
+       DIV(CLK_DIV_ATB, "div_atb", "div_core2", DIV_CPU0, 16, 3),
+       DIV(CLK_DIV_PERIPH, "div_periph", "div_core2", DIV_CPU0, 12, 3),
+       DIV(CLK_DIV_COREM1, "div_corem1", "div_core2", DIV_CPU0, 8, 3),
+       DIV(CLK_DIV_COREM0, "div_corem0", "div_core2", DIV_CPU0, 4, 3),
+       DIV_F(CLK_DIV_CORE, "div_core", "mout_core", DIV_CPU0, 0, 3,
+               CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+
+       /* DIV_CPU1 */
+       DIV(CLK_DIV_HPM, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
+       DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
+};
+
+static struct samsung_gate_clock exynos4415_gate_clks[] __initdata = {
+       /*
+        * NOTE: Following table is sorted by register address in ascending
+        * order and then bitfield shift in descending order, as it is done
+        * in the User's Manual. When adding new entries, please make sure
+        * that the order is preserved, to avoid merge conflicts and make
+        * further work with defined data easier.
+        */
+
+       /* GATE_IP_LEFTBUS */
+       GATE(CLK_ASYNC_G3D, "async_g3d", "div_aclk_100", GATE_IP_LEFTBUS, 6,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_ASYNC_MFCL, "async_mfcl", "div_aclk_100", GATE_IP_LEFTBUS, 4,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_ASYNC_TVX, "async_tvx", "div_aclk_100", GATE_IP_LEFTBUS, 3,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_GPIO_LEFT, "gpio_left", "div_aclk_100", GATE_IP_LEFTBUS, 0,
+               CLK_IGNORE_UNUSED, 0),
+
+       /* GATE_IP_IMAGE */
+       GATE(CLK_PPMUIMAGE, "ppmuimage", "div_aclk_100", GATE_IP_IMAGE,
+               9, 0, 0),
+       GATE(CLK_QEMDMA2, "qe_mdma2", "div_aclk_100", GATE_IP_IMAGE,
+               8, 0, 0),
+       GATE(CLK_QEROTATOR, "qe_rotator", "div_aclk_100", GATE_IP_IMAGE,
+               7, 0, 0),
+       GATE(CLK_SMMUMDMA2, "smmu_mdam2", "div_aclk_100", GATE_IP_IMAGE,
+               5, 0, 0),
+       GATE(CLK_SMMUROTATOR, "smmu_rotator", "div_aclk_100", GATE_IP_IMAGE,
+               4, 0, 0),
+       GATE(CLK_MDMA2, "mdma2", "div_aclk_100", GATE_IP_IMAGE, 2, 0, 0),
+       GATE(CLK_ROTATOR, "rotator", "div_aclk_100", GATE_IP_IMAGE, 1, 0, 0),
+
+       /* GATE_IP_RIGHTBUS */
+       GATE(CLK_ASYNC_ISPMX, "async_ispmx", "div_aclk_100",
+               GATE_IP_RIGHTBUS, 9, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_ASYNC_MAUDIOX, "async_maudiox", "div_aclk_100",
+               GATE_IP_RIGHTBUS, 7, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_ASYNC_MFCR, "async_mfcr", "div_aclk_100",
+               GATE_IP_RIGHTBUS, 6, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_ASYNC_FSYSD, "async_fsysd", "div_aclk_100",
+               GATE_IP_RIGHTBUS, 5, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_ASYNC_LCD0X, "async_lcd0x", "div_aclk_100",
+               GATE_IP_RIGHTBUS, 3, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100",
+               GATE_IP_RIGHTBUS, 2, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100",
+               GATE_IP_RIGHTBUS, 1, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_GPIO_RIGHT, "gpio_right", "div_aclk_100",
+               GATE_IP_RIGHTBUS, 0, CLK_IGNORE_UNUSED, 0),
+
+       /* GATE_IP_PERIR */
+       GATE(CLK_ANTIRBK_APBIF, "antirbk_apbif", "div_aclk_100",
+               GATE_IP_PERIR, 24, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_EFUSE_WRITER_APBIF, "efuse_writer_apbif", "div_aclk_100",
+               GATE_IP_PERIR, 23, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_MONOCNT, "monocnt", "div_aclk_100", GATE_IP_PERIR, 22,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_TZPC6, "tzpc6", "div_aclk_100", GATE_IP_PERIR, 21,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_PROVISIONKEY1, "provisionkey1", "div_aclk_100",
+               GATE_IP_PERIR, 20, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_PROVISIONKEY0, "provisionkey0", "div_aclk_100",
+               GATE_IP_PERIR, 19, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_CMU_ISPPART, "cmu_isppart", "div_aclk_100", GATE_IP_PERIR, 18,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_TMU_APBIF, "tmu_apbif", "div_aclk_100",
+               GATE_IP_PERIR, 17, 0, 0),
+       GATE(CLK_KEYIF, "keyif", "div_aclk_100", GATE_IP_PERIR, 16, 0, 0),
+       GATE(CLK_RTC, "rtc", "div_aclk_100", GATE_IP_PERIR, 15, 0, 0),
+       GATE(CLK_WDT, "wdt", "div_aclk_100", GATE_IP_PERIR, 14, 0, 0),
+       GATE(CLK_MCT, "mct", "div_aclk_100", GATE_IP_PERIR, 13, 0, 0),
+       GATE(CLK_SECKEY, "seckey", "div_aclk_100", GATE_IP_PERIR, 12,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_HDMI_CEC, "hdmi_cec", "div_aclk_100", GATE_IP_PERIR, 11,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_TZPC5, "tzpc5", "div_aclk_100", GATE_IP_PERIR, 10,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_TZPC4, "tzpc4", "div_aclk_100", GATE_IP_PERIR, 9,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_TZPC3, "tzpc3", "div_aclk_100", GATE_IP_PERIR, 8,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_TZPC2, "tzpc2", "div_aclk_100", GATE_IP_PERIR, 7,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_TZPC1, "tzpc1", "div_aclk_100", GATE_IP_PERIR, 6,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_TZPC0, "tzpc0", "div_aclk_100", GATE_IP_PERIR, 5,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_CMU_COREPART, "cmu_corepart", "div_aclk_100", GATE_IP_PERIR, 4,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_CMU_TOPPART, "cmu_toppart", "div_aclk_100", GATE_IP_PERIR, 3,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_PMU_APBIF, "pmu_apbif", "div_aclk_100", GATE_IP_PERIR, 2,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_SYSREG, "sysreg", "div_aclk_100", GATE_IP_PERIR, 1,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_CHIP_ID, "chip_id", "div_aclk_100", GATE_IP_PERIR, 0,
+               CLK_IGNORE_UNUSED, 0),
+
+       /* GATE_SCLK_CAM - non-completed */
+       GATE(CLK_SCLK_PXLAYSNC_CSIS1_FIMC, "sclk_pxlasync_csis1_fimc",
+               "div_pxlasync_csis1_fimc", GATE_SCLK_CAM, 11,
+               CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_PXLAYSNC_CSIS0_FIMC, "sclk_pxlasync_csis0_fimc",
+               "div_pxlasync_csis0_fimc", GATE_SCLK_CAM,
+               10, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_jpeg",
+               GATE_SCLK_CAM, 8, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_CSIS1, "sclk_csis1", "div_csis1",
+               GATE_SCLK_CAM, 7, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_CSIS0, "sclk_csis0", "div_csis0",
+               GATE_SCLK_CAM, 6, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
+               GATE_SCLK_CAM, 5, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_FIMC3_LCLK, "sclk_fimc3_lclk", "div_fimc3_lclk",
+               GATE_SCLK_CAM, 3, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_FIMC2_LCLK, "sclk_fimc2_lclk", "div_fimc2_lclk",
+               GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_FIMC1_LCLK, "sclk_fimc1_lclk", "div_fimc1_lclk",
+               GATE_SCLK_CAM, 1, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_FIMC0_LCLK, "sclk_fimc0_lclk", "div_fimc0_lclk",
+               GATE_SCLK_CAM, 0, CLK_SET_RATE_PARENT, 0),
+
+       /* GATE_SCLK_TV */
+       GATE(CLK_SCLK_PIXEL, "sclk_pixel", "div_tv_blk",
+               GATE_SCLK_TV, 3, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
+               GATE_SCLK_TV, 2, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_MIXER, "sclk_mixer", "div_tv_blk",
+               GATE_SCLK_TV, 0, CLK_SET_RATE_PARENT, 0),
+
+       /* GATE_SCLK_MFC */
+       GATE(CLK_SCLK_MFC, "sclk_mfc", "div_mfc",
+               GATE_SCLK_MFC, 0, CLK_SET_RATE_PARENT, 0),
+
+       /* GATE_SCLK_G3D */
+       GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d",
+               GATE_SCLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
+
+       /* GATE_SCLK_LCD */
+       GATE(CLK_SCLK_MIPIDPHY4L, "sclk_mipidphy4l", "div_mipi0",
+               GATE_SCLK_LCD, 4, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi0_pre",
+               GATE_SCLK_LCD, 3, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_MDNIE0, "sclk_mdnie0", "div_fimd0",
+               GATE_SCLK_LCD, 1, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0",
+               GATE_SCLK_LCD, 0, CLK_SET_RATE_PARENT, 0),
+
+       /* GATE_SCLK_MAUDIO */
+       GATE(CLK_SCLK_PCM0, "sclk_pcm0", "div_pcm0",
+               GATE_SCLK_MAUDIO, 1, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0",
+               GATE_SCLK_MAUDIO, 0, CLK_SET_RATE_PARENT, 0),
+
+       /* GATE_SCLK_FSYS */
+       GATE(CLK_SCLK_TSADC, "sclk_tsadc", "div_tsadc_pre",
+               GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
+               GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre",
+               GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
+               GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
+               GATE_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
+
+       /* GATE_SCLK_PERIL */
+       GATE(CLK_SCLK_I2S, "sclk_i2s1", "div_i2s1",
+               GATE_SCLK_PERIL, 18, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_PCM2, "sclk_pcm2", "div_pcm2",
+               GATE_SCLK_PERIL, 16, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_PCM1, "sclk_pcm1", "div_pcm1",
+               GATE_SCLK_PERIL, 15, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2",
+               GATE_SCLK_PERIL, 14, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1",
+               GATE_SCLK_PERIL, 13, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
+               GATE_SCLK_PERIL, 10, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi2_pre",
+               GATE_SCLK_PERIL, 8, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi1_pre",
+               GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
+               GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
+               GATE_SCLK_PERIL, 3, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
+               GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
+               GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
+               GATE_SCLK_PERIL, 0, CLK_SET_RATE_PARENT, 0),
+
+       /* GATE_IP_CAM */
+       GATE(CLK_SMMUFIMC_LITE2, "smmufimc_lite2", "div_aclk_160", GATE_IP_CAM,
+               22, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_FIMC_LITE2, "fimc_lite2", "div_aclk_160", GATE_IP_CAM,
+               20, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_PIXELASYNCM1, "pixelasyncm1", "div_aclk_160", GATE_IP_CAM,
+               18, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_PIXELASYNCM0, "pixelasyncm0", "div_aclk_160", GATE_IP_CAM,
+               17, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_PPMUCAMIF, "ppmucamif", "div_aclk_160", GATE_IP_CAM,
+               16, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_SMMUJPEG, "smmujpeg", "div_aclk_160", GATE_IP_CAM, 11, 0, 0),
+       GATE(CLK_SMMUFIMC3, "smmufimc3", "div_aclk_160", GATE_IP_CAM, 10, 0, 0),
+       GATE(CLK_SMMUFIMC2, "smmufimc2", "div_aclk_160", GATE_IP_CAM, 9, 0, 0),
+       GATE(CLK_SMMUFIMC1, "smmufimc1", "div_aclk_160", GATE_IP_CAM, 8, 0, 0),
+       GATE(CLK_SMMUFIMC0, "smmufimc0", "div_aclk_160", GATE_IP_CAM, 7, 0, 0),
+       GATE(CLK_JPEG, "jpeg", "div_aclk_160", GATE_IP_CAM, 6, 0, 0),
+       GATE(CLK_CSIS1, "csis1", "div_aclk_160", GATE_IP_CAM, 5, 0, 0),
+       GATE(CLK_CSIS0, "csis0", "div_aclk_160", GATE_IP_CAM, 4, 0, 0),
+       GATE(CLK_FIMC3, "fimc3", "div_aclk_160", GATE_IP_CAM, 3, 0, 0),
+       GATE(CLK_FIMC2, "fimc2", "div_aclk_160", GATE_IP_CAM, 2, 0, 0),
+       GATE(CLK_FIMC1, "fimc1", "div_aclk_160", GATE_IP_CAM, 1, 0, 0),
+       GATE(CLK_FIMC0, "fimc0", "div_aclk_160", GATE_IP_CAM, 0, 0, 0),
+
+       /* GATE_IP_TV */
+       GATE(CLK_PPMUTV, "ppmutv", "div_aclk_100", GATE_IP_TV, 5, 0, 0),
+       GATE(CLK_SMMUTV, "smmutv", "div_aclk_100", GATE_IP_TV, 4, 0, 0),
+       GATE(CLK_HDMI, "hdmi", "div_aclk_100", GATE_IP_TV, 3, 0, 0),
+       GATE(CLK_MIXER, "mixer", "div_aclk_100", GATE_IP_TV, 1, 0, 0),
+       GATE(CLK_VP, "vp", "div_aclk_100", GATE_IP_TV, 0, 0, 0),
+
+       /* GATE_IP_MFC */
+       GATE(CLK_PPMUMFC_R, "ppmumfc_r", "div_aclk_200", GATE_IP_MFC, 4,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_PPMUMFC_L, "ppmumfc_l", "div_aclk_200", GATE_IP_MFC, 3,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_SMMUMFC_R, "smmumfc_r", "div_aclk_200", GATE_IP_MFC, 2, 0, 0),
+       GATE(CLK_SMMUMFC_L, "smmumfc_l", "div_aclk_200", GATE_IP_MFC, 1, 0, 0),
+       GATE(CLK_MFC, "mfc", "div_aclk_200", GATE_IP_MFC, 0, 0, 0),
+
+       /* GATE_IP_G3D */
+       GATE(CLK_PPMUG3D, "ppmug3d", "div_aclk_200", GATE_IP_G3D, 1,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_G3D, "g3d", "div_aclk_200", GATE_IP_G3D, 0, 0, 0),
+
+       /* GATE_IP_LCD */
+       GATE(CLK_PPMULCD0, "ppmulcd0", "div_aclk_160", GATE_IP_LCD, 5,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_SMMUFIMD0, "smmufimd0", "div_aclk_160", GATE_IP_LCD, 4, 0, 0),
+       GATE(CLK_DSIM0, "dsim0", "div_aclk_160", GATE_IP_LCD, 3, 0, 0),
+       GATE(CLK_SMIES, "smies", "div_aclk_160", GATE_IP_LCD, 2, 0, 0),
+       GATE(CLK_MIE0, "mie0", "div_aclk_160", GATE_IP_LCD, 1, 0, 0),
+       GATE(CLK_FIMD0, "fimd0", "div_aclk_160", GATE_IP_LCD, 0, 0, 0),
+
+       /* GATE_IP_FSYS */
+       GATE(CLK_TSADC, "tsadc", "div_aclk_200", GATE_IP_FSYS, 20, 0, 0),
+       GATE(CLK_PPMUFILE, "ppmufile", "div_aclk_200", GATE_IP_FSYS, 17,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_NFCON, "nfcon", "div_aclk_200", GATE_IP_FSYS, 16, 0, 0),
+       GATE(CLK_USBDEVICE, "usbdevice", "div_aclk_200", GATE_IP_FSYS, 13,
+               0, 0),
+       GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
+       GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
+       GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
+       GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
+       GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
+       GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
+       GATE(CLK_PDMA0, "pdma0", "div_aclk_200", GATE_IP_FSYS, 0, 0, 0),
+
+       /* GATE_IP_PERIL */
+       GATE(CLK_SPDIF, "spdif", "div_aclk_100", GATE_IP_PERIL, 26, 0, 0),
+       GATE(CLK_PWM, "pwm", "div_aclk_100", GATE_IP_PERIL, 24, 0, 0),
+       GATE(CLK_PCM2, "pcm2", "div_aclk_100", GATE_IP_PERIL, 23, 0, 0),
+       GATE(CLK_PCM1, "pcm1", "div_aclk_100", GATE_IP_PERIL, 22, 0, 0),
+       GATE(CLK_I2S1, "i2s1", "div_aclk_100", GATE_IP_PERIL, 20, 0, 0),
+       GATE(CLK_SPI2, "spi2", "div_aclk_100", GATE_IP_PERIL, 18, 0, 0),
+       GATE(CLK_SPI1, "spi1", "div_aclk_100", GATE_IP_PERIL, 17, 0, 0),
+       GATE(CLK_SPI0, "spi0", "div_aclk_100", GATE_IP_PERIL, 16, 0, 0),
+       GATE(CLK_I2CHDMI, "i2chdmi", "div_aclk_100", GATE_IP_PERIL, 14, 0, 0),
+       GATE(CLK_I2C7, "i2c7", "div_aclk_100", GATE_IP_PERIL, 13, 0, 0),
+       GATE(CLK_I2C6, "i2c6", "div_aclk_100", GATE_IP_PERIL, 12, 0, 0),
+       GATE(CLK_I2C5, "i2c5", "div_aclk_100", GATE_IP_PERIL, 11, 0, 0),
+       GATE(CLK_I2C4, "i2c4", "div_aclk_100", GATE_IP_PERIL, 10, 0, 0),
+       GATE(CLK_I2C3, "i2c3", "div_aclk_100", GATE_IP_PERIL, 9, 0, 0),
+       GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
+       GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
+       GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
+       GATE(CLK_UART3, "uart3", "div_aclk_100", GATE_IP_PERIL, 3, 0, 0),
+       GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
+       GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
+       GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
+};
+
+/*
+ * APLL & MPLL & BPLL & ISP_PLL & DISP_PLL & G3D_PLL
+ */
+static struct samsung_pll_rate_table exynos4415_pll_rates[] = {
+       PLL_35XX_RATE(1600000000, 400, 3,  1),
+       PLL_35XX_RATE(1500000000, 250, 2,  1),
+       PLL_35XX_RATE(1400000000, 175, 3,  0),
+       PLL_35XX_RATE(1300000000, 325, 3,  1),
+       PLL_35XX_RATE(1200000000, 400, 4,  1),
+       PLL_35XX_RATE(1100000000, 275, 3,  1),
+       PLL_35XX_RATE(1066000000, 533, 6,  1),
+       PLL_35XX_RATE(1000000000, 250, 3,  1),
+       PLL_35XX_RATE(960000000,  320, 4,  1),
+       PLL_35XX_RATE(900000000,  300, 4,  1),
+       PLL_35XX_RATE(850000000,  425, 6,  1),
+       PLL_35XX_RATE(800000000,  200, 3,  1),
+       PLL_35XX_RATE(700000000,  175, 3,  1),
+       PLL_35XX_RATE(667000000,  667, 12, 1),
+       PLL_35XX_RATE(600000000,  400, 4,  2),
+       PLL_35XX_RATE(550000000,  275, 3,  2),
+       PLL_35XX_RATE(533000000,  533, 6,  2),
+       PLL_35XX_RATE(520000000,  260, 3,  2),
+       PLL_35XX_RATE(500000000,  250, 3,  2),
+       PLL_35XX_RATE(440000000,  220, 3,  2),
+       PLL_35XX_RATE(400000000,  200, 3,  2),
+       PLL_35XX_RATE(350000000,  175, 3,  2),
+       PLL_35XX_RATE(300000000,  300, 3,  3),
+       PLL_35XX_RATE(266000000,  266, 3,  3),
+       PLL_35XX_RATE(200000000,  200, 3,  3),
+       PLL_35XX_RATE(160000000,  160, 3,  3),
+       PLL_35XX_RATE(100000000,  200, 3,  4),
+       { /* sentinel */ }
+};
+
+/* EPLL */
+static struct samsung_pll_rate_table exynos4415_epll_rates[] = {
+       PLL_36XX_RATE(800000000, 200, 3, 1,     0),
+       PLL_36XX_RATE(288000000,  96, 2, 2,     0),
+       PLL_36XX_RATE(192000000, 128, 2, 3,     0),
+       PLL_36XX_RATE(144000000,  96, 2, 3,     0),
+       PLL_36XX_RATE(96000000,  128, 2, 4,     0),
+       PLL_36XX_RATE(84000000,  112, 2, 4,     0),
+       PLL_36XX_RATE(80750011,  107, 2, 4, 43691),
+       PLL_36XX_RATE(73728004,   98, 2, 4, 19923),
+       PLL_36XX_RATE(67987602,  271, 3, 5, 62285),
+       PLL_36XX_RATE(65911004,  175, 2, 5, 49982),
+       PLL_36XX_RATE(50000000,  200, 3, 5,     0),
+       PLL_36XX_RATE(49152003,  131, 2, 5,  4719),
+       PLL_36XX_RATE(48000000,  128, 2, 5,     0),
+       PLL_36XX_RATE(45250000,  181, 3, 5,     0),
+       { /* sentinel */ }
+};
+
+static struct samsung_pll_clock exynos4415_plls[nr_plls] __initdata = {
+       [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
+                       APLL_LOCK, APLL_CON0, NULL),
+       [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
+                       EPLL_LOCK, EPLL_CON0, NULL),
+       [g3d_pll] = PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll",
+                       "mout_g3d_pllsrc", G3D_PLL_LOCK, G3D_PLL_CON0, NULL),
+       [isp_pll] = PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "fin_pll",
+                       ISP_PLL_LOCK, ISP_PLL_CON0, NULL),
+       [disp_pll] = PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll",
+                       "fin_pll", DISP_PLL_LOCK, DISP_PLL_CON0, NULL),
+};
+
+static void __init exynos4415_cmu_init(struct device_node *np)
+{
+       void __iomem *reg_base;
+
+       reg_base = of_iomap(np, 0);
+       if (!reg_base)
+               panic("%s: failed to map registers\n", __func__);
+
+       exynos4415_ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
+       if (!exynos4415_ctx)
+               panic("%s: unable to allocate context.\n", __func__);
+
+       exynos4415_plls[apll].rate_table = exynos4415_pll_rates;
+       exynos4415_plls[epll].rate_table = exynos4415_epll_rates;
+       exynos4415_plls[g3d_pll].rate_table = exynos4415_pll_rates;
+       exynos4415_plls[isp_pll].rate_table = exynos4415_pll_rates;
+       exynos4415_plls[disp_pll].rate_table = exynos4415_pll_rates;
+
+       samsung_clk_register_fixed_factor(exynos4415_ctx,
+                               exynos4415_fixed_factor_clks,
+                               ARRAY_SIZE(exynos4415_fixed_factor_clks));
+       samsung_clk_register_fixed_rate(exynos4415_ctx,
+                               exynos4415_fixed_rate_clks,
+                               ARRAY_SIZE(exynos4415_fixed_rate_clks));
+
+       samsung_clk_register_pll(exynos4415_ctx, exynos4415_plls,
+                               ARRAY_SIZE(exynos4415_plls), reg_base);
+       samsung_clk_register_mux(exynos4415_ctx, exynos4415_mux_clks,
+                               ARRAY_SIZE(exynos4415_mux_clks));
+       samsung_clk_register_div(exynos4415_ctx, exynos4415_div_clks,
+                               ARRAY_SIZE(exynos4415_div_clks));
+       samsung_clk_register_gate(exynos4415_ctx, exynos4415_gate_clks,
+                               ARRAY_SIZE(exynos4415_gate_clks));
+
+       exynos4415_clk_sleep_init();
+
+       samsung_clk_of_add_provider(np, exynos4415_ctx);
+}
+CLK_OF_DECLARE(exynos4415_cmu, "samsung,exynos4415-cmu", exynos4415_cmu_init);
+
+/*
+ * CMU DMC
+ */
+
+#define MPLL_LOCK              0x008
+#define MPLL_CON0              0x108
+#define MPLL_CON1              0x10c
+#define MPLL_CON2              0x110
+#define BPLL_LOCK              0x118
+#define BPLL_CON0              0x218
+#define BPLL_CON1              0x21c
+#define BPLL_CON2              0x220
+#define SRC_DMC                        0x300
+#define DIV_DMC1               0x504
+
+enum exynos4415_dmc_plls {
+       mpll, bpll,
+       nr_dmc_plls,
+};
+
+static struct samsung_clk_provider *exynos4415_dmc_ctx;
+
+#ifdef CONFIG_PM_SLEEP
+static struct samsung_clk_reg_dump *exynos4415_dmc_clk_regs;
+
+static unsigned long exynos4415_cmu_dmc_clk_regs[] __initdata = {
+       MPLL_LOCK,
+       MPLL_CON0,
+       MPLL_CON1,
+       MPLL_CON2,
+       BPLL_LOCK,
+       BPLL_CON0,
+       BPLL_CON1,
+       BPLL_CON2,
+       SRC_DMC,
+       DIV_DMC1,
+};
+
+static int exynos4415_dmc_clk_suspend(void)
+{
+       samsung_clk_save(exynos4415_dmc_ctx->reg_base,
+                               exynos4415_dmc_clk_regs,
+                               ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs));
+       return 0;
+}
+
+static void exynos4415_dmc_clk_resume(void)
+{
+       samsung_clk_restore(exynos4415_dmc_ctx->reg_base,
+                               exynos4415_dmc_clk_regs,
+                               ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs));
+}
+
+static struct syscore_ops exynos4415_dmc_clk_syscore_ops = {
+       .suspend = exynos4415_dmc_clk_suspend,
+       .resume = exynos4415_dmc_clk_resume,
+};
+
+static void exynos4415_dmc_clk_sleep_init(void)
+{
+       exynos4415_dmc_clk_regs =
+               samsung_clk_alloc_reg_dump(exynos4415_cmu_dmc_clk_regs,
+                               ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs));
+       if (!exynos4415_dmc_clk_regs) {
+               pr_warn("%s: Failed to allocate sleep save data\n", __func__);
+               return;
+       }
+
+       register_syscore_ops(&exynos4415_dmc_clk_syscore_ops);
+}
+#else
+static inline void exynos4415_dmc_clk_sleep_init(void) { }
+#endif /* CONFIG_PM_SLEEP */
+
+PNAME(mout_mpll_p)             = { "fin_pll", "fout_mpll", };
+PNAME(mout_bpll_p)             = { "fin_pll", "fout_bpll", };
+PNAME(mbpll_p)                 = { "mout_mpll", "mout_bpll", };
+
+static struct samsung_mux_clock exynos4415_dmc_mux_clks[] __initdata = {
+       MUX(CLK_DMC_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_DMC, 12, 1),
+       MUX(CLK_DMC_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_DMC, 10, 1),
+       MUX(CLK_DMC_MOUT_DPHY, "mout_dphy", mbpll_p, SRC_DMC, 8, 1),
+       MUX(CLK_DMC_MOUT_DMC_BUS, "mout_dmc_bus", mbpll_p, SRC_DMC, 4, 1),
+};
+
+static struct samsung_div_clock exynos4415_dmc_div_clks[] __initdata = {
+       DIV(CLK_DMC_DIV_DMC, "div_dmc", "div_dmc_pre", DIV_DMC1, 27, 3),
+       DIV(CLK_DMC_DIV_DPHY, "div_dphy", "mout_dphy", DIV_DMC1, 23, 3),
+       DIV(CLK_DMC_DIV_DMC_PRE, "div_dmc_pre", "mout_dmc_bus",
+               DIV_DMC1, 19, 2),
+       DIV(CLK_DMC_DIV_DMCP, "div_dmcp", "div_dmcd", DIV_DMC1, 15, 3),
+       DIV(CLK_DMC_DIV_DMCD, "div_dmcd", "div_dmc", DIV_DMC1, 11, 3),
+       DIV(CLK_DMC_DIV_MPLL_PRE, "div_mpll_pre", "mout_mpll", DIV_DMC1, 8, 2),
+};
+
+static struct samsung_pll_clock exynos4415_dmc_plls[nr_dmc_plls] __initdata = {
+       [mpll] = PLL(pll_35xx, CLK_DMC_FOUT_MPLL, "fout_mpll", "fin_pll",
+               MPLL_LOCK, MPLL_CON0, NULL),
+       [bpll] = PLL(pll_35xx, CLK_DMC_FOUT_BPLL, "fout_bpll", "fin_pll",
+               BPLL_LOCK, BPLL_CON0, NULL),
+};
+
+static void __init exynos4415_cmu_dmc_init(struct device_node *np)
+{
+       void __iomem *reg_base;
+
+       reg_base = of_iomap(np, 0);
+       if (!reg_base)
+               panic("%s: failed to map registers\n", __func__);
+
+       exynos4415_dmc_ctx = samsung_clk_init(np, reg_base, NR_CLKS_DMC);
+       if (!exynos4415_dmc_ctx)
+               panic("%s: unable to allocate context.\n", __func__);
+
+       exynos4415_dmc_plls[mpll].rate_table = exynos4415_pll_rates;
+       exynos4415_dmc_plls[bpll].rate_table = exynos4415_pll_rates;
+
+       samsung_clk_register_pll(exynos4415_dmc_ctx, exynos4415_dmc_plls,
+                               ARRAY_SIZE(exynos4415_dmc_plls), reg_base);
+       samsung_clk_register_mux(exynos4415_dmc_ctx, exynos4415_dmc_mux_clks,
+                               ARRAY_SIZE(exynos4415_dmc_mux_clks));
+       samsung_clk_register_div(exynos4415_dmc_ctx, exynos4415_dmc_div_clks,
+                               ARRAY_SIZE(exynos4415_dmc_div_clks));
+
+       exynos4415_dmc_clk_sleep_init();
+
+       samsung_clk_of_add_provider(np, exynos4415_dmc_ctx);
+}
+CLK_OF_DECLARE(exynos4415_cmu_dmc, "samsung,exynos4415-cmu-dmc",
+               exynos4415_cmu_dmc_init);
index 2527e39aadcfbfafab2a0b5c97d4aab2e4809458..e2e5193d10490b0295805023c448c1c0b685d02d 100644 (file)
 
 #include <linux/clk.h>
 #include <linux/clkdev.h>
-#include <linux/clk-provider.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
-#include <linux/syscore_ops.h>
 
 #include "clk-exynos5260.h"
 #include "clk.h"
 
 #include <dt-bindings/clock/exynos5260-clk.h>
 
-static LIST_HEAD(clock_reg_cache_list);
-
-struct exynos5260_clock_reg_cache {
-       struct list_head node;
-       void __iomem *reg_base;
-       struct samsung_clk_reg_dump *rdump;
-       unsigned int rd_num;
-};
-
-struct exynos5260_cmu_info {
-       /* list of pll clocks and respective count */
-       struct samsung_pll_clock *pll_clks;
-       unsigned int nr_pll_clks;
-       /* list of mux clocks and respective count */
-       struct samsung_mux_clock *mux_clks;
-       unsigned int nr_mux_clks;
-       /* list of div clocks and respective count */
-       struct samsung_div_clock *div_clks;
-       unsigned int nr_div_clks;
-       /* list of gate clocks and respective count */
-       struct samsung_gate_clock *gate_clks;
-       unsigned int nr_gate_clks;
-       /* list of fixed clocks and respective count */
-       struct samsung_fixed_rate_clock *fixed_clks;
-       unsigned int nr_fixed_clks;
-       /* total number of clocks with IDs assigned*/
-       unsigned int nr_clk_ids;
-
-       /* list and number of clocks registers */
-       unsigned long *clk_regs;
-       unsigned int nr_clk_regs;
-};
-
 /*
  * Applicable for all 2550 Type PLLS for Exynos5260, listed below
  * DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL.
@@ -113,104 +78,6 @@ static struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initdata = {
        PLL_36XX_RATE(66000000, 176, 2, 5, 0),
 };
 
-#ifdef CONFIG_PM_SLEEP
-
-static int exynos5260_clk_suspend(void)
-{
-       struct exynos5260_clock_reg_cache *cache;
-
-       list_for_each_entry(cache, &clock_reg_cache_list, node)
-               samsung_clk_save(cache->reg_base, cache->rdump,
-                               cache->rd_num);
-
-       return 0;
-}
-
-static void exynos5260_clk_resume(void)
-{
-       struct exynos5260_clock_reg_cache *cache;
-
-       list_for_each_entry(cache, &clock_reg_cache_list, node)
-               samsung_clk_restore(cache->reg_base, cache->rdump,
-                               cache->rd_num);
-}
-
-static struct syscore_ops exynos5260_clk_syscore_ops = {
-       .suspend = exynos5260_clk_suspend,
-       .resume = exynos5260_clk_resume,
-};
-
-static void exynos5260_clk_sleep_init(void __iomem *reg_base,
-                       unsigned long *rdump,
-                       unsigned long nr_rdump)
-{
-       struct exynos5260_clock_reg_cache *reg_cache;
-
-       reg_cache = kzalloc(sizeof(struct exynos5260_clock_reg_cache),
-                       GFP_KERNEL);
-       if (!reg_cache)
-               panic("could not allocate register cache.\n");
-
-       reg_cache->rdump = samsung_clk_alloc_reg_dump(rdump, nr_rdump);
-
-       if (!reg_cache->rdump)
-               panic("could not allocate register dump storage.\n");
-
-       if (list_empty(&clock_reg_cache_list))
-               register_syscore_ops(&exynos5260_clk_syscore_ops);
-
-       reg_cache->rd_num = nr_rdump;
-       reg_cache->reg_base = reg_base;
-       list_add_tail(&reg_cache->node, &clock_reg_cache_list);
-}
-
-#else
-static void exynos5260_clk_sleep_init(void __iomem *reg_base,
-                       unsigned long *rdump,
-                       unsigned long nr_rdump){}
-#endif
-
-/*
- * Common function which registers plls, muxes, dividers and gates
- * for each CMU. It also add CMU register list to register cache.
- */
-
-void __init exynos5260_cmu_register_one(struct device_node *np,
-                       struct exynos5260_cmu_info *cmu)
-{
-       void __iomem *reg_base;
-       struct samsung_clk_provider *ctx;
-
-       reg_base = of_iomap(np, 0);
-       if (!reg_base)
-               panic("%s: failed to map registers\n", __func__);
-
-       ctx = samsung_clk_init(np, reg_base, cmu->nr_clk_ids);
-       if (!ctx)
-               panic("%s: unable to alllocate ctx\n", __func__);
-
-       if (cmu->pll_clks)
-               samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks,
-                       reg_base);
-       if (cmu->mux_clks)
-               samsung_clk_register_mux(ctx,  cmu->mux_clks,
-                       cmu->nr_mux_clks);
-       if (cmu->div_clks)
-               samsung_clk_register_div(ctx, cmu->div_clks, cmu->nr_div_clks);
-       if (cmu->gate_clks)
-               samsung_clk_register_gate(ctx, cmu->gate_clks,
-                       cmu->nr_gate_clks);
-       if (cmu->fixed_clks)
-               samsung_clk_register_fixed_rate(ctx, cmu->fixed_clks,
-                       cmu->nr_fixed_clks);
-       if (cmu->clk_regs)
-               exynos5260_clk_sleep_init(reg_base, cmu->clk_regs,
-                       cmu->nr_clk_regs);
-
-       samsung_clk_of_add_provider(np, ctx);
-}
-
-
 /* CMU_AUD */
 
 static unsigned long aud_clk_regs[] __initdata = {
@@ -268,7 +135,7 @@ struct samsung_gate_clock aud_gate_clks[] __initdata = {
 
 static void __init exynos5260_clk_aud_init(struct device_node *np)
 {
-       struct exynos5260_cmu_info cmu = {0};
+       struct samsung_cmu_info cmu = {0};
 
        cmu.mux_clks = aud_mux_clks;
        cmu.nr_mux_clks = ARRAY_SIZE(aud_mux_clks);
@@ -280,7 +147,7 @@ static void __init exynos5260_clk_aud_init(struct device_node *np)
        cmu.clk_regs = aud_clk_regs;
        cmu.nr_clk_regs = ARRAY_SIZE(aud_clk_regs);
 
-       exynos5260_cmu_register_one(np, &cmu);
+       samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_aud, "samsung,exynos5260-clock-aud",
@@ -458,7 +325,7 @@ struct samsung_gate_clock disp_gate_clks[] __initdata = {
 
 static void __init exynos5260_clk_disp_init(struct device_node *np)
 {
-       struct exynos5260_cmu_info cmu = {0};
+       struct samsung_cmu_info cmu = {0};
 
        cmu.mux_clks = disp_mux_clks;
        cmu.nr_mux_clks = ARRAY_SIZE(disp_mux_clks);
@@ -470,7 +337,7 @@ static void __init exynos5260_clk_disp_init(struct device_node *np)
        cmu.clk_regs = disp_clk_regs;
        cmu.nr_clk_regs = ARRAY_SIZE(disp_clk_regs);
 
-       exynos5260_cmu_register_one(np, &cmu);
+       samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_disp, "samsung,exynos5260-clock-disp",
@@ -522,7 +389,7 @@ static struct samsung_pll_clock egl_pll_clks[] __initdata = {
 
 static void __init exynos5260_clk_egl_init(struct device_node *np)
 {
-       struct exynos5260_cmu_info cmu = {0};
+       struct samsung_cmu_info cmu = {0};
 
        cmu.pll_clks = egl_pll_clks;
        cmu.nr_pll_clks =  ARRAY_SIZE(egl_pll_clks);
@@ -534,7 +401,7 @@ static void __init exynos5260_clk_egl_init(struct device_node *np)
        cmu.clk_regs = egl_clk_regs;
        cmu.nr_clk_regs = ARRAY_SIZE(egl_clk_regs);
 
-       exynos5260_cmu_register_one(np, &cmu);
+       samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_egl, "samsung,exynos5260-clock-egl",
@@ -624,7 +491,7 @@ struct samsung_gate_clock fsys_gate_clks[] __initdata = {
 
 static void __init exynos5260_clk_fsys_init(struct device_node *np)
 {
-       struct exynos5260_cmu_info cmu = {0};
+       struct samsung_cmu_info cmu = {0};
 
        cmu.mux_clks = fsys_mux_clks;
        cmu.nr_mux_clks = ARRAY_SIZE(fsys_mux_clks);
@@ -634,7 +501,7 @@ static void __init exynos5260_clk_fsys_init(struct device_node *np)
        cmu.clk_regs = fsys_clk_regs;
        cmu.nr_clk_regs = ARRAY_SIZE(fsys_clk_regs);
 
-       exynos5260_cmu_register_one(np, &cmu);
+       samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_fsys, "samsung,exynos5260-clock-fsys",
@@ -713,7 +580,7 @@ struct samsung_gate_clock g2d_gate_clks[] __initdata = {
 
 static void __init exynos5260_clk_g2d_init(struct device_node *np)
 {
-       struct exynos5260_cmu_info cmu = {0};
+       struct samsung_cmu_info cmu = {0};
 
        cmu.mux_clks = g2d_mux_clks;
        cmu.nr_mux_clks = ARRAY_SIZE(g2d_mux_clks);
@@ -725,7 +592,7 @@ static void __init exynos5260_clk_g2d_init(struct device_node *np)
        cmu.clk_regs = g2d_clk_regs;
        cmu.nr_clk_regs = ARRAY_SIZE(g2d_clk_regs);
 
-       exynos5260_cmu_register_one(np, &cmu);
+       samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_g2d, "samsung,exynos5260-clock-g2d",
@@ -774,7 +641,7 @@ static struct samsung_pll_clock g3d_pll_clks[] __initdata = {
 
 static void __init exynos5260_clk_g3d_init(struct device_node *np)
 {
-       struct exynos5260_cmu_info cmu = {0};
+       struct samsung_cmu_info cmu = {0};
 
        cmu.pll_clks = g3d_pll_clks;
        cmu.nr_pll_clks =  ARRAY_SIZE(g3d_pll_clks);
@@ -788,7 +655,7 @@ static void __init exynos5260_clk_g3d_init(struct device_node *np)
        cmu.clk_regs = g3d_clk_regs;
        cmu.nr_clk_regs = ARRAY_SIZE(g3d_clk_regs);
 
-       exynos5260_cmu_register_one(np, &cmu);
+       samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_g3d, "samsung,exynos5260-clock-g3d",
@@ -909,7 +776,7 @@ struct samsung_gate_clock gscl_gate_clks[] __initdata = {
 
 static void __init exynos5260_clk_gscl_init(struct device_node *np)
 {
-       struct exynos5260_cmu_info cmu = {0};
+       struct samsung_cmu_info cmu = {0};
 
        cmu.mux_clks = gscl_mux_clks;
        cmu.nr_mux_clks = ARRAY_SIZE(gscl_mux_clks);
@@ -921,7 +788,7 @@ static void __init exynos5260_clk_gscl_init(struct device_node *np)
        cmu.clk_regs = gscl_clk_regs;
        cmu.nr_clk_regs = ARRAY_SIZE(gscl_clk_regs);
 
-       exynos5260_cmu_register_one(np, &cmu);
+       samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_gscl, "samsung,exynos5260-clock-gscl",
@@ -1028,7 +895,7 @@ struct samsung_gate_clock isp_gate_clks[] __initdata = {
 
 static void __init exynos5260_clk_isp_init(struct device_node *np)
 {
-       struct exynos5260_cmu_info cmu = {0};
+       struct samsung_cmu_info cmu = {0};
 
        cmu.mux_clks = isp_mux_clks;
        cmu.nr_mux_clks = ARRAY_SIZE(isp_mux_clks);
@@ -1040,7 +907,7 @@ static void __init exynos5260_clk_isp_init(struct device_node *np)
        cmu.clk_regs = isp_clk_regs;
        cmu.nr_clk_regs = ARRAY_SIZE(isp_clk_regs);
 
-       exynos5260_cmu_register_one(np, &cmu);
+       samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_isp, "samsung,exynos5260-clock-isp",
@@ -1092,7 +959,7 @@ static struct samsung_pll_clock kfc_pll_clks[] __initdata = {
 
 static void __init exynos5260_clk_kfc_init(struct device_node *np)
 {
-       struct exynos5260_cmu_info cmu = {0};
+       struct samsung_cmu_info cmu = {0};
 
        cmu.pll_clks = kfc_pll_clks;
        cmu.nr_pll_clks =  ARRAY_SIZE(kfc_pll_clks);
@@ -1104,7 +971,7 @@ static void __init exynos5260_clk_kfc_init(struct device_node *np)
        cmu.clk_regs = kfc_clk_regs;
        cmu.nr_clk_regs = ARRAY_SIZE(kfc_clk_regs);
 
-       exynos5260_cmu_register_one(np, &cmu);
+       samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_kfc, "samsung,exynos5260-clock-kfc",
@@ -1148,7 +1015,7 @@ struct samsung_gate_clock mfc_gate_clks[] __initdata = {
 
 static void __init exynos5260_clk_mfc_init(struct device_node *np)
 {
-       struct exynos5260_cmu_info cmu = {0};
+       struct samsung_cmu_info cmu = {0};
 
        cmu.mux_clks = mfc_mux_clks;
        cmu.nr_mux_clks = ARRAY_SIZE(mfc_mux_clks);
@@ -1160,7 +1027,7 @@ static void __init exynos5260_clk_mfc_init(struct device_node *np)
        cmu.clk_regs = mfc_clk_regs;
        cmu.nr_clk_regs = ARRAY_SIZE(mfc_clk_regs);
 
-       exynos5260_cmu_register_one(np, &cmu);
+       samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_mfc, "samsung,exynos5260-clock-mfc",
@@ -1295,7 +1162,7 @@ static struct samsung_pll_clock mif_pll_clks[] __initdata = {
 
 static void __init exynos5260_clk_mif_init(struct device_node *np)
 {
-       struct exynos5260_cmu_info cmu = {0};
+       struct samsung_cmu_info cmu = {0};
 
        cmu.pll_clks = mif_pll_clks;
        cmu.nr_pll_clks =  ARRAY_SIZE(mif_pll_clks);
@@ -1309,7 +1176,7 @@ static void __init exynos5260_clk_mif_init(struct device_node *np)
        cmu.clk_regs = mif_clk_regs;
        cmu.nr_clk_regs = ARRAY_SIZE(mif_clk_regs);
 
-       exynos5260_cmu_register_one(np, &cmu);
+       samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_mif, "samsung,exynos5260-clock-mif",
@@ -1503,7 +1370,7 @@ struct samsung_gate_clock peri_gate_clks[] __initdata = {
 
 static void __init exynos5260_clk_peri_init(struct device_node *np)
 {
-       struct exynos5260_cmu_info cmu = {0};
+       struct samsung_cmu_info cmu = {0};
 
        cmu.mux_clks = peri_mux_clks;
        cmu.nr_mux_clks = ARRAY_SIZE(peri_mux_clks);
@@ -1515,7 +1382,7 @@ static void __init exynos5260_clk_peri_init(struct device_node *np)
        cmu.clk_regs = peri_clk_regs;
        cmu.nr_clk_regs = ARRAY_SIZE(peri_clk_regs);
 
-       exynos5260_cmu_register_one(np, &cmu);
+       samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_peri, "samsung,exynos5260-clock-peri",
@@ -1959,7 +1826,7 @@ static struct samsung_pll_clock top_pll_clks[] __initdata = {
 
 static void __init exynos5260_clk_top_init(struct device_node *np)
 {
-       struct exynos5260_cmu_info cmu = {0};
+       struct samsung_cmu_info cmu = {0};
 
        cmu.pll_clks = top_pll_clks;
        cmu.nr_pll_clks =  ARRAY_SIZE(top_pll_clks);
@@ -1975,7 +1842,7 @@ static void __init exynos5260_clk_top_init(struct device_node *np)
        cmu.clk_regs = top_clk_regs;
        cmu.nr_clk_regs = ARRAY_SIZE(top_clk_regs);
 
-       exynos5260_cmu_register_one(np, &cmu);
+       samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_top, "samsung,exynos5260-clock-top",
diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
new file mode 100644 (file)
index 0000000..ea4483b
--- /dev/null
@@ -0,0 +1,743 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+
+#include "clk.h"
+#include <dt-bindings/clock/exynos7-clk.h>
+
+/* Register Offset definitions for CMU_TOPC (0x10570000) */
+#define CC_PLL_LOCK            0x0000
+#define BUS0_PLL_LOCK          0x0004
+#define BUS1_DPLL_LOCK         0x0008
+#define MFC_PLL_LOCK           0x000C
+#define AUD_PLL_LOCK           0x0010
+#define CC_PLL_CON0            0x0100
+#define BUS0_PLL_CON0          0x0110
+#define BUS1_DPLL_CON0         0x0120
+#define MFC_PLL_CON0           0x0130
+#define AUD_PLL_CON0           0x0140
+#define MUX_SEL_TOPC0          0x0200
+#define MUX_SEL_TOPC1          0x0204
+#define MUX_SEL_TOPC2          0x0208
+#define MUX_SEL_TOPC3          0x020C
+#define DIV_TOPC0              0x0600
+#define DIV_TOPC1              0x0604
+#define DIV_TOPC3              0x060C
+
+static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = {
+       FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_bus0_pll_ctrl", 1, 2, 0),
+       FFACTOR(0, "ffac_topc_bus0_pll_div4",
+               "ffac_topc_bus0_pll_div2", 1, 2, 0),
+       FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_bus1_pll_ctrl", 1, 2, 0),
+       FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_cc_pll_ctrl", 1, 2, 0),
+       FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_mfc_pll_ctrl", 1, 2, 0),
+};
+
+/* List of parent clocks for Muxes in CMU_TOPC */
+PNAME(mout_bus0_pll_ctrl_p)    = { "fin_pll", "fout_bus0_pll" };
+PNAME(mout_bus1_pll_ctrl_p)    = { "fin_pll", "fout_bus1_pll" };
+PNAME(mout_cc_pll_ctrl_p)      = { "fin_pll", "fout_cc_pll" };
+PNAME(mout_mfc_pll_ctrl_p)     = { "fin_pll", "fout_mfc_pll" };
+
+PNAME(mout_topc_group2) = { "mout_sclk_bus0_pll_cmuc",
+       "mout_sclk_bus1_pll_cmuc", "mout_sclk_cc_pll_cmuc",
+       "mout_sclk_mfc_pll_cmuc" };
+
+PNAME(mout_sclk_bus0_pll_cmuc_p) = { "mout_bus0_pll_ctrl",
+       "ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"};
+PNAME(mout_sclk_bus1_pll_cmuc_p) = { "mout_bus1_pll_ctrl",
+       "ffac_topc_bus1_pll_div2"};
+PNAME(mout_sclk_cc_pll_cmuc_p) = { "mout_cc_pll_ctrl",
+       "ffac_topc_cc_pll_div2"};
+PNAME(mout_sclk_mfc_pll_cmuc_p) = { "mout_mfc_pll_ctrl",
+       "ffac_topc_mfc_pll_div2"};
+
+
+PNAME(mout_sclk_bus0_pll_out_p) = {"mout_bus0_pll_ctrl",
+       "ffac_topc_bus0_pll_div2"};
+
+static unsigned long topc_clk_regs[] __initdata = {
+       CC_PLL_LOCK,
+       BUS0_PLL_LOCK,
+       BUS1_DPLL_LOCK,
+       MFC_PLL_LOCK,
+       AUD_PLL_LOCK,
+       CC_PLL_CON0,
+       BUS0_PLL_CON0,
+       BUS1_DPLL_CON0,
+       MFC_PLL_CON0,
+       AUD_PLL_CON0,
+       MUX_SEL_TOPC0,
+       MUX_SEL_TOPC1,
+       MUX_SEL_TOPC2,
+       MUX_SEL_TOPC3,
+       DIV_TOPC0,
+       DIV_TOPC1,
+       DIV_TOPC3,
+};
+
+static struct samsung_mux_clock topc_mux_clks[] __initdata = {
+       MUX(0, "mout_bus0_pll_ctrl", mout_bus0_pll_ctrl_p, MUX_SEL_TOPC0, 0, 1),
+       MUX(0, "mout_bus1_pll_ctrl", mout_bus1_pll_ctrl_p, MUX_SEL_TOPC0, 4, 1),
+       MUX(0, "mout_cc_pll_ctrl", mout_cc_pll_ctrl_p, MUX_SEL_TOPC0, 8, 1),
+       MUX(0, "mout_mfc_pll_ctrl", mout_mfc_pll_ctrl_p, MUX_SEL_TOPC0, 12, 1),
+
+       MUX(0, "mout_sclk_bus0_pll_cmuc", mout_sclk_bus0_pll_cmuc_p,
+               MUX_SEL_TOPC0, 16, 2),
+       MUX(0, "mout_sclk_bus1_pll_cmuc", mout_sclk_bus1_pll_cmuc_p,
+               MUX_SEL_TOPC0, 20, 1),
+       MUX(0, "mout_sclk_cc_pll_cmuc", mout_sclk_cc_pll_cmuc_p,
+               MUX_SEL_TOPC0, 24, 1),
+       MUX(0, "mout_sclk_mfc_pll_cmuc", mout_sclk_mfc_pll_cmuc_p,
+               MUX_SEL_TOPC0, 28, 1),
+
+       MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p,
+               MUX_SEL_TOPC1, 16, 1),
+
+       MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
+
+       MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2),
+};
+
+static struct samsung_div_clock topc_div_clks[] __initdata = {
+       DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133",
+               DIV_TOPC0, 4, 4),
+
+       DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66",
+               DIV_TOPC1, 24, 4),
+
+       DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_sclk_bus0_pll_out",
+               DIV_TOPC3, 0, 3),
+       DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_bus1_pll_ctrl",
+               DIV_TOPC3, 8, 3),
+       DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_cc_pll_ctrl",
+               DIV_TOPC3, 12, 3),
+       DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_mfc_pll_ctrl",
+               DIV_TOPC3, 16, 3),
+};
+
+static struct samsung_pll_clock topc_pll_clks[] __initdata = {
+       PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK,
+               BUS0_PLL_CON0, NULL),
+       PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK,
+               CC_PLL_CON0, NULL),
+       PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK,
+               BUS1_DPLL_CON0, NULL),
+       PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK,
+               MFC_PLL_CON0, NULL),
+       PLL(pll_1460x, 0, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK,
+               AUD_PLL_CON0, NULL),
+};
+
+static struct samsung_cmu_info topc_cmu_info __initdata = {
+       .pll_clks               = topc_pll_clks,
+       .nr_pll_clks            = ARRAY_SIZE(topc_pll_clks),
+       .mux_clks               = topc_mux_clks,
+       .nr_mux_clks            = ARRAY_SIZE(topc_mux_clks),
+       .div_clks               = topc_div_clks,
+       .nr_div_clks            = ARRAY_SIZE(topc_div_clks),
+       .fixed_factor_clks      = topc_fixed_factor_clks,
+       .nr_fixed_factor_clks   = ARRAY_SIZE(topc_fixed_factor_clks),
+       .nr_clk_ids             = TOPC_NR_CLK,
+       .clk_regs               = topc_clk_regs,
+       .nr_clk_regs            = ARRAY_SIZE(topc_clk_regs),
+};
+
+static void __init exynos7_clk_topc_init(struct device_node *np)
+{
+       samsung_cmu_register_one(np, &topc_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc",
+       exynos7_clk_topc_init);
+
+/* Register Offset definitions for CMU_TOP0 (0x105D0000) */
+#define MUX_SEL_TOP00                  0x0200
+#define MUX_SEL_TOP01                  0x0204
+#define MUX_SEL_TOP03                  0x020C
+#define MUX_SEL_TOP0_PERIC3            0x023C
+#define DIV_TOP03                      0x060C
+#define DIV_TOP0_PERIC3                        0x063C
+#define ENABLE_SCLK_TOP0_PERIC3                0x0A3C
+
+/* List of parent clocks for Muxes in CMU_TOP0 */
+PNAME(mout_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" };
+PNAME(mout_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll" };
+PNAME(mout_cc_pll_p)   = { "fin_pll", "dout_sclk_cc_pll" };
+PNAME(mout_mfc_pll_p)  = { "fin_pll", "dout_sclk_mfc_pll" };
+
+PNAME(mout_top0_half_bus0_pll_p) = {"mout_top0_bus0_pll",
+       "ffac_top0_bus0_pll_div2"};
+PNAME(mout_top0_half_bus1_pll_p) = {"mout_top0_bus1_pll",
+       "ffac_top0_bus1_pll_div2"};
+PNAME(mout_top0_half_cc_pll_p) = {"mout_top0_cc_pll",
+       "ffac_top0_cc_pll_div2"};
+PNAME(mout_top0_half_mfc_pll_p) = {"mout_top0_mfc_pll",
+       "ffac_top0_mfc_pll_div2"};
+
+PNAME(mout_top0_group1) = {"mout_top0_half_bus0_pll",
+       "mout_top0_half_bus1_pll", "mout_top0_half_cc_pll",
+       "mout_top0_half_mfc_pll"};
+
+static unsigned long top0_clk_regs[] __initdata = {
+       MUX_SEL_TOP00,
+       MUX_SEL_TOP01,
+       MUX_SEL_TOP03,
+       MUX_SEL_TOP0_PERIC3,
+       DIV_TOP03,
+       DIV_TOP0_PERIC3,
+       ENABLE_SCLK_TOP0_PERIC3,
+};
+
+static struct samsung_mux_clock top0_mux_clks[] __initdata = {
+       MUX(0, "mout_top0_mfc_pll", mout_mfc_pll_p, MUX_SEL_TOP00, 4, 1),
+       MUX(0, "mout_top0_cc_pll", mout_cc_pll_p, MUX_SEL_TOP00, 8, 1),
+       MUX(0, "mout_top0_bus1_pll", mout_bus1_pll_p, MUX_SEL_TOP00, 12, 1),
+       MUX(0, "mout_top0_bus0_pll", mout_bus0_pll_p, MUX_SEL_TOP00, 16, 1),
+
+       MUX(0, "mout_top0_half_mfc_pll", mout_top0_half_mfc_pll_p,
+               MUX_SEL_TOP01, 4, 1),
+       MUX(0, "mout_top0_half_cc_pll", mout_top0_half_cc_pll_p,
+               MUX_SEL_TOP01, 8, 1),
+       MUX(0, "mout_top0_half_bus1_pll", mout_top0_half_bus1_pll_p,
+               MUX_SEL_TOP01, 12, 1),
+       MUX(0, "mout_top0_half_bus0_pll", mout_top0_half_bus0_pll_p,
+               MUX_SEL_TOP01, 16, 1),
+
+       MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2),
+       MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2),
+
+       MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2),
+       MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2),
+       MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2),
+       MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2),
+};
+
+static struct samsung_div_clock top0_div_clks[] __initdata = {
+       DIV(DOUT_ACLK_PERIC1, "dout_aclk_peric1_66", "mout_aclk_peric1_66",
+               DIV_TOP03, 12, 6),
+       DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66",
+               DIV_TOP03, 20, 6),
+
+       DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4),
+       DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4),
+       DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4),
+       DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4),
+};
+
+static struct samsung_gate_clock top0_gate_clks[] __initdata = {
+       GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3",
+               ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0),
+       GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2",
+               ENABLE_SCLK_TOP0_PERIC3, 8, 0, 0),
+       GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1",
+               ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0),
+       GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0",
+               ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0),
+};
+
+static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = {
+       FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll", 1, 2, 0),
+       FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll", 1, 2, 0),
+       FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll", 1, 2, 0),
+       FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll", 1, 2, 0),
+};
+
+static struct samsung_cmu_info top0_cmu_info __initdata = {
+       .mux_clks               = top0_mux_clks,
+       .nr_mux_clks            = ARRAY_SIZE(top0_mux_clks),
+       .div_clks               = top0_div_clks,
+       .nr_div_clks            = ARRAY_SIZE(top0_div_clks),
+       .gate_clks              = top0_gate_clks,
+       .nr_gate_clks           = ARRAY_SIZE(top0_gate_clks),
+       .fixed_factor_clks      = top0_fixed_factor_clks,
+       .nr_fixed_factor_clks   = ARRAY_SIZE(top0_fixed_factor_clks),
+       .nr_clk_ids             = TOP0_NR_CLK,
+       .clk_regs               = top0_clk_regs,
+       .nr_clk_regs            = ARRAY_SIZE(top0_clk_regs),
+};
+
+static void __init exynos7_clk_top0_init(struct device_node *np)
+{
+       samsung_cmu_register_one(np, &top0_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0",
+       exynos7_clk_top0_init);
+
+/* Register Offset definitions for CMU_TOP1 (0x105E0000) */
+#define MUX_SEL_TOP10                  0x0200
+#define MUX_SEL_TOP11                  0x0204
+#define MUX_SEL_TOP13                  0x020C
+#define MUX_SEL_TOP1_FSYS0             0x0224
+#define MUX_SEL_TOP1_FSYS1             0x0228
+#define DIV_TOP13                      0x060C
+#define DIV_TOP1_FSYS0                 0x0624
+#define DIV_TOP1_FSYS1                 0x0628
+#define ENABLE_ACLK_TOP13              0x080C
+#define ENABLE_SCLK_TOP1_FSYS0         0x0A24
+#define ENABLE_SCLK_TOP1_FSYS1         0x0A28
+
+/* List of parent clocks for Muxes in CMU_TOP1 */
+PNAME(mout_top1_bus0_pll_p)    = { "fin_pll", "dout_sclk_bus0_pll" };
+PNAME(mout_top1_bus1_pll_p)    = { "fin_pll", "dout_sclk_bus1_pll_b" };
+PNAME(mout_top1_cc_pll_p)      = { "fin_pll", "dout_sclk_cc_pll_b" };
+PNAME(mout_top1_mfc_pll_p)     = { "fin_pll", "dout_sclk_mfc_pll_b" };
+
+PNAME(mout_top1_half_bus0_pll_p) = {"mout_top1_bus0_pll",
+       "ffac_top1_bus0_pll_div2"};
+PNAME(mout_top1_half_bus1_pll_p) = {"mout_top1_bus1_pll",
+       "ffac_top1_bus1_pll_div2"};
+PNAME(mout_top1_half_cc_pll_p) = {"mout_top1_cc_pll",
+       "ffac_top1_cc_pll_div2"};
+PNAME(mout_top1_half_mfc_pll_p) = {"mout_top1_mfc_pll",
+       "ffac_top1_mfc_pll_div2"};
+
+PNAME(mout_top1_group1) = {"mout_top1_half_bus0_pll",
+       "mout_top1_half_bus1_pll", "mout_top1_half_cc_pll",
+       "mout_top1_half_mfc_pll"};
+
+static unsigned long top1_clk_regs[] __initdata = {
+       MUX_SEL_TOP10,
+       MUX_SEL_TOP11,
+       MUX_SEL_TOP13,
+       MUX_SEL_TOP1_FSYS0,
+       MUX_SEL_TOP1_FSYS1,
+       DIV_TOP13,
+       DIV_TOP1_FSYS0,
+       DIV_TOP1_FSYS1,
+       ENABLE_ACLK_TOP13,
+       ENABLE_SCLK_TOP1_FSYS0,
+       ENABLE_SCLK_TOP1_FSYS1,
+};
+
+static struct samsung_mux_clock top1_mux_clks[] __initdata = {
+       MUX(0, "mout_top1_mfc_pll", mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1),
+       MUX(0, "mout_top1_cc_pll", mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1),
+       MUX(0, "mout_top1_bus1_pll", mout_top1_bus1_pll_p,
+               MUX_SEL_TOP10, 12, 1),
+       MUX(0, "mout_top1_bus0_pll", mout_top1_bus0_pll_p,
+               MUX_SEL_TOP10, 16, 1),
+
+       MUX(0, "mout_top1_half_mfc_pll", mout_top1_half_mfc_pll_p,
+               MUX_SEL_TOP11, 4, 1),
+       MUX(0, "mout_top1_half_cc_pll", mout_top1_half_cc_pll_p,
+               MUX_SEL_TOP11, 8, 1),
+       MUX(0, "mout_top1_half_bus1_pll", mout_top1_half_bus1_pll_p,
+               MUX_SEL_TOP11, 12, 1),
+       MUX(0, "mout_top1_half_bus0_pll", mout_top1_half_bus0_pll_p,
+               MUX_SEL_TOP11, 16, 1),
+
+       MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
+       MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
+
+       MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2),
+
+       MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2),
+       MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 28, 2),
+};
+
+static struct samsung_div_clock top1_div_clks[] __initdata = {
+       DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200",
+               DIV_TOP13, 24, 4),
+       DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200",
+               DIV_TOP13, 28, 4),
+
+       DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
+               DIV_TOP1_FSYS0, 24, 4),
+
+       DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1",
+               DIV_TOP1_FSYS1, 24, 4),
+       DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0",
+               DIV_TOP1_FSYS1, 28, 4),
+};
+
+static struct samsung_gate_clock top1_gate_clks[] __initdata = {
+       GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
+               ENABLE_SCLK_TOP1_FSYS0, 24, CLK_SET_RATE_PARENT, 0),
+
+       GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
+               ENABLE_SCLK_TOP1_FSYS1, 24, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
+               ENABLE_SCLK_TOP1_FSYS1, 28, CLK_SET_RATE_PARENT, 0),
+};
+
+static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = {
+       FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll", 1, 2, 0),
+       FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll", 1, 2, 0),
+       FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll", 1, 2, 0),
+       FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll", 1, 2, 0),
+};
+
+static struct samsung_cmu_info top1_cmu_info __initdata = {
+       .mux_clks               = top1_mux_clks,
+       .nr_mux_clks            = ARRAY_SIZE(top1_mux_clks),
+       .div_clks               = top1_div_clks,
+       .nr_div_clks            = ARRAY_SIZE(top1_div_clks),
+       .gate_clks              = top1_gate_clks,
+       .nr_gate_clks           = ARRAY_SIZE(top1_gate_clks),
+       .fixed_factor_clks      = top1_fixed_factor_clks,
+       .nr_fixed_factor_clks   = ARRAY_SIZE(top1_fixed_factor_clks),
+       .nr_clk_ids             = TOP1_NR_CLK,
+       .clk_regs               = top1_clk_regs,
+       .nr_clk_regs            = ARRAY_SIZE(top1_clk_regs),
+};
+
+static void __init exynos7_clk_top1_init(struct device_node *np)
+{
+       samsung_cmu_register_one(np, &top1_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
+       exynos7_clk_top1_init);
+
+/* Register Offset definitions for CMU_CCORE (0x105B0000) */
+#define MUX_SEL_CCORE                  0x0200
+#define DIV_CCORE                      0x0600
+#define ENABLE_ACLK_CCORE0             0x0800
+#define ENABLE_ACLK_CCORE1             0x0804
+#define ENABLE_PCLK_CCORE              0x0900
+
+/*
+ * List of parent clocks for Muxes in CMU_CCORE
+ */
+PNAME(mout_aclk_ccore_133_p)   = { "fin_pll", "dout_aclk_ccore_133" };
+
+static unsigned long ccore_clk_regs[] __initdata = {
+       MUX_SEL_CCORE,
+       ENABLE_PCLK_CCORE,
+};
+
+static struct samsung_mux_clock ccore_mux_clks[] __initdata = {
+       MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_p,
+               MUX_SEL_CCORE, 1, 1),
+};
+
+static struct samsung_gate_clock ccore_gate_clks[] __initdata = {
+       GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user",
+               ENABLE_PCLK_CCORE, 8, 0, 0),
+};
+
+static struct samsung_cmu_info ccore_cmu_info __initdata = {
+       .mux_clks               = ccore_mux_clks,
+       .nr_mux_clks            = ARRAY_SIZE(ccore_mux_clks),
+       .gate_clks              = ccore_gate_clks,
+       .nr_gate_clks           = ARRAY_SIZE(ccore_gate_clks),
+       .nr_clk_ids             = CCORE_NR_CLK,
+       .clk_regs               = ccore_clk_regs,
+       .nr_clk_regs            = ARRAY_SIZE(ccore_clk_regs),
+};
+
+static void __init exynos7_clk_ccore_init(struct device_node *np)
+{
+       samsung_cmu_register_one(np, &ccore_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore",
+       exynos7_clk_ccore_init);
+
+/* Register Offset definitions for CMU_PERIC0 (0x13610000) */
+#define MUX_SEL_PERIC0                 0x0200
+#define ENABLE_PCLK_PERIC0             0x0900
+#define ENABLE_SCLK_PERIC0             0x0A00
+
+/* List of parent clocks for Muxes in CMU_PERIC0 */
+PNAME(mout_aclk_peric0_66_p)   = { "fin_pll", "dout_aclk_peric0_66" };
+PNAME(mout_sclk_uart0_p)       = { "fin_pll", "sclk_uart0" };
+
+static unsigned long peric0_clk_regs[] __initdata = {
+       MUX_SEL_PERIC0,
+       ENABLE_PCLK_PERIC0,
+       ENABLE_SCLK_PERIC0,
+};
+
+static struct samsung_mux_clock peric0_mux_clks[] __initdata = {
+       MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_p,
+               MUX_SEL_PERIC0, 0, 1),
+       MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_p,
+               MUX_SEL_PERIC0, 16, 1),
+};
+
+static struct samsung_gate_clock peric0_gate_clks[] __initdata = {
+       GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user",
+               ENABLE_PCLK_PERIC0, 8, 0, 0),
+       GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user",
+               ENABLE_PCLK_PERIC0, 9, 0, 0),
+       GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user",
+               ENABLE_PCLK_PERIC0, 10, 0, 0),
+       GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user",
+               ENABLE_PCLK_PERIC0, 11, 0, 0),
+       GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user",
+               ENABLE_PCLK_PERIC0, 12, 0, 0),
+       GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user",
+               ENABLE_PCLK_PERIC0, 13, 0, 0),
+       GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user",
+               ENABLE_PCLK_PERIC0, 14, 0, 0),
+       GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",
+               ENABLE_PCLK_PERIC0, 16, 0, 0),
+       GATE(PCLK_ADCIF, "pclk_adcif", "mout_aclk_peric0_66_user",
+               ENABLE_PCLK_PERIC0, 20, 0, 0),
+       GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user",
+               ENABLE_PCLK_PERIC0, 21, 0, 0),
+
+       GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user",
+               ENABLE_SCLK_PERIC0, 16, 0, 0),
+       GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0),
+};
+
+static struct samsung_cmu_info peric0_cmu_info __initdata = {
+       .mux_clks               = peric0_mux_clks,
+       .nr_mux_clks            = ARRAY_SIZE(peric0_mux_clks),
+       .gate_clks              = peric0_gate_clks,
+       .nr_gate_clks           = ARRAY_SIZE(peric0_gate_clks),
+       .nr_clk_ids             = PERIC0_NR_CLK,
+       .clk_regs               = peric0_clk_regs,
+       .nr_clk_regs            = ARRAY_SIZE(peric0_clk_regs),
+};
+
+static void __init exynos7_clk_peric0_init(struct device_node *np)
+{
+       samsung_cmu_register_one(np, &peric0_cmu_info);
+}
+
+/* Register Offset definitions for CMU_PERIC1 (0x14C80000) */
+#define MUX_SEL_PERIC10                        0x0200
+#define MUX_SEL_PERIC11                        0x0204
+#define ENABLE_PCLK_PERIC1             0x0900
+#define ENABLE_SCLK_PERIC10            0x0A00
+
+CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0",
+       exynos7_clk_peric0_init);
+
+/* List of parent clocks for Muxes in CMU_PERIC1 */
+PNAME(mout_aclk_peric1_66_p)   = { "fin_pll", "dout_aclk_peric1_66" };
+PNAME(mout_sclk_uart1_p)       = { "fin_pll", "sclk_uart1" };
+PNAME(mout_sclk_uart2_p)       = { "fin_pll", "sclk_uart2" };
+PNAME(mout_sclk_uart3_p)       = { "fin_pll", "sclk_uart3" };
+
+static unsigned long peric1_clk_regs[] __initdata = {
+       MUX_SEL_PERIC10,
+       MUX_SEL_PERIC11,
+       ENABLE_PCLK_PERIC1,
+       ENABLE_SCLK_PERIC10,
+};
+
+static struct samsung_mux_clock peric1_mux_clks[] __initdata = {
+       MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p,
+               MUX_SEL_PERIC10, 0, 1),
+
+       MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p,
+               MUX_SEL_PERIC11, 20, 1),
+       MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p,
+               MUX_SEL_PERIC11, 24, 1),
+       MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_p,
+               MUX_SEL_PERIC11, 28, 1),
+};
+
+static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
+       GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user",
+               ENABLE_PCLK_PERIC1, 4, 0, 0),
+       GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user",
+               ENABLE_PCLK_PERIC1, 5, 0, 0),
+       GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user",
+               ENABLE_PCLK_PERIC1, 6, 0, 0),
+       GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user",
+               ENABLE_PCLK_PERIC1, 7, 0, 0),
+       GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user",
+               ENABLE_PCLK_PERIC1, 8, 0, 0),
+       GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user",
+               ENABLE_PCLK_PERIC1, 9, 0, 0),
+       GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user",
+               ENABLE_PCLK_PERIC1, 10, 0, 0),
+       GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user",
+               ENABLE_PCLK_PERIC1, 11, 0, 0),
+
+       GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user",
+               ENABLE_SCLK_PERIC10, 9, 0, 0),
+       GATE(SCLK_UART2, "sclk_uart2_user", "mout_sclk_uart2_user",
+               ENABLE_SCLK_PERIC10, 10, 0, 0),
+       GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user",
+               ENABLE_SCLK_PERIC10, 11, 0, 0),
+};
+
+static struct samsung_cmu_info peric1_cmu_info __initdata = {
+       .mux_clks               = peric1_mux_clks,
+       .nr_mux_clks            = ARRAY_SIZE(peric1_mux_clks),
+       .gate_clks              = peric1_gate_clks,
+       .nr_gate_clks           = ARRAY_SIZE(peric1_gate_clks),
+       .nr_clk_ids             = PERIC1_NR_CLK,
+       .clk_regs               = peric1_clk_regs,
+       .nr_clk_regs            = ARRAY_SIZE(peric1_clk_regs),
+};
+
+static void __init exynos7_clk_peric1_init(struct device_node *np)
+{
+       samsung_cmu_register_one(np, &peric1_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1",
+       exynos7_clk_peric1_init);
+
+/* Register Offset definitions for CMU_PERIS (0x10040000) */
+#define MUX_SEL_PERIS                  0x0200
+#define ENABLE_PCLK_PERIS              0x0900
+#define ENABLE_PCLK_PERIS_SECURE_CHIPID        0x0910
+#define ENABLE_SCLK_PERIS              0x0A00
+#define ENABLE_SCLK_PERIS_SECURE_CHIPID        0x0A10
+
+/* List of parent clocks for Muxes in CMU_PERIS */
+PNAME(mout_aclk_peris_66_p) = { "fin_pll", "dout_aclk_peris_66" };
+
+static unsigned long peris_clk_regs[] __initdata = {
+       MUX_SEL_PERIS,
+       ENABLE_PCLK_PERIS,
+       ENABLE_PCLK_PERIS_SECURE_CHIPID,
+       ENABLE_SCLK_PERIS,
+       ENABLE_SCLK_PERIS_SECURE_CHIPID,
+};
+
+static struct samsung_mux_clock peris_mux_clks[] __initdata = {
+       MUX(0, "mout_aclk_peris_66_user",
+               mout_aclk_peris_66_p, MUX_SEL_PERIS, 0, 1),
+};
+
+static struct samsung_gate_clock peris_gate_clks[] __initdata = {
+       GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user",
+               ENABLE_PCLK_PERIS, 6, 0, 0),
+       GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user",
+               ENABLE_PCLK_PERIS, 10, 0, 0),
+
+       GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user",
+               ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
+       GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll",
+               ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
+
+       GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0),
+};
+
+static struct samsung_cmu_info peris_cmu_info __initdata = {
+       .mux_clks               = peris_mux_clks,
+       .nr_mux_clks            = ARRAY_SIZE(peris_mux_clks),
+       .gate_clks              = peris_gate_clks,
+       .nr_gate_clks           = ARRAY_SIZE(peris_gate_clks),
+       .nr_clk_ids             = PERIS_NR_CLK,
+       .clk_regs               = peris_clk_regs,
+       .nr_clk_regs            = ARRAY_SIZE(peris_clk_regs),
+};
+
+static void __init exynos7_clk_peris_init(struct device_node *np)
+{
+       samsung_cmu_register_one(np, &peris_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
+       exynos7_clk_peris_init);
+
+/* Register Offset definitions for CMU_FSYS0 (0x10E90000) */
+#define MUX_SEL_FSYS00                 0x0200
+#define MUX_SEL_FSYS01                 0x0204
+#define ENABLE_ACLK_FSYS01             0x0804
+
+/*
+ * List of parent clocks for Muxes in CMU_FSYS0
+ */
+PNAME(mout_aclk_fsys0_200_p)   = { "fin_pll", "dout_aclk_fsys0_200" };
+PNAME(mout_sclk_mmc2_p)                = { "fin_pll", "sclk_mmc2" };
+
+static unsigned long fsys0_clk_regs[] __initdata = {
+       MUX_SEL_FSYS00,
+       MUX_SEL_FSYS01,
+       ENABLE_ACLK_FSYS01,
+};
+
+static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
+       MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_p,
+               MUX_SEL_FSYS00, 24, 1),
+
+       MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1),
+};
+
+static struct samsung_gate_clock fsys0_gate_clks[] __initdata = {
+       GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user",
+               ENABLE_ACLK_FSYS01, 31, 0, 0),
+};
+
+static struct samsung_cmu_info fsys0_cmu_info __initdata = {
+       .mux_clks               = fsys0_mux_clks,
+       .nr_mux_clks            = ARRAY_SIZE(fsys0_mux_clks),
+       .gate_clks              = fsys0_gate_clks,
+       .nr_gate_clks           = ARRAY_SIZE(fsys0_gate_clks),
+       .nr_clk_ids             = TOP1_NR_CLK,
+       .clk_regs               = fsys0_clk_regs,
+       .nr_clk_regs            = ARRAY_SIZE(fsys0_clk_regs),
+};
+
+static void __init exynos7_clk_fsys0_init(struct device_node *np)
+{
+       samsung_cmu_register_one(np, &fsys0_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0",
+       exynos7_clk_fsys0_init);
+
+/* Register Offset definitions for CMU_FSYS1 (0x156E0000) */
+#define MUX_SEL_FSYS10                 0x0200
+#define MUX_SEL_FSYS11                 0x0204
+#define ENABLE_ACLK_FSYS1              0x0800
+
+/*
+ * List of parent clocks for Muxes in CMU_FSYS1
+ */
+PNAME(mout_aclk_fsys1_200_p)   = { "fin_pll",  "dout_aclk_fsys1_200" };
+PNAME(mout_sclk_mmc0_p)                = { "fin_pll", "sclk_mmc0" };
+PNAME(mout_sclk_mmc1_p)                = { "fin_pll", "sclk_mmc1" };
+
+static unsigned long fsys1_clk_regs[] __initdata = {
+       MUX_SEL_FSYS10,
+       MUX_SEL_FSYS11,
+       ENABLE_ACLK_FSYS1,
+};
+
+static struct samsung_mux_clock fsys1_mux_clks[] __initdata = {
+       MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_p,
+               MUX_SEL_FSYS10, 28, 1),
+
+       MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_p, MUX_SEL_FSYS11, 24, 1),
+       MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_p, MUX_SEL_FSYS11, 28, 1),
+};
+
+static struct samsung_gate_clock fsys1_gate_clks[] __initdata = {
+       GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user",
+               ENABLE_ACLK_FSYS1, 29, 0, 0),
+       GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user",
+               ENABLE_ACLK_FSYS1, 30, 0, 0),
+};
+
+static struct samsung_cmu_info fsys1_cmu_info __initdata = {
+       .mux_clks               = fsys1_mux_clks,
+       .nr_mux_clks            = ARRAY_SIZE(fsys1_mux_clks),
+       .gate_clks              = fsys1_gate_clks,
+       .nr_gate_clks           = ARRAY_SIZE(fsys1_gate_clks),
+       .nr_clk_ids             = TOP1_NR_CLK,
+       .clk_regs               = fsys1_clk_regs,
+       .nr_clk_regs            = ARRAY_SIZE(fsys1_clk_regs),
+};
+
+static void __init exynos7_clk_fsys1_init(struct device_node *np)
+{
+       samsung_cmu_register_one(np, &fsys1_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1",
+       exynos7_clk_fsys1_init);
index b07fad2a916703731731f40b5db3aa678e835b17..9d70e5c03804cee247ee54ff4faed549bbf7ea12 100644 (file)
@@ -482,6 +482,8 @@ static const struct clk_ops samsung_pll45xx_clk_min_ops = {
 
 #define PLL46XX_VSEL_MASK      (1)
 #define PLL46XX_MDIV_MASK      (0x1FF)
+#define PLL1460X_MDIV_MASK     (0x3FF)
+
 #define PLL46XX_PDIV_MASK      (0x3F)
 #define PLL46XX_SDIV_MASK      (0x7)
 #define PLL46XX_VSEL_SHIFT     (27)
@@ -511,13 +513,15 @@ static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw,
 
        pll_con0 = __raw_readl(pll->con_reg);
        pll_con1 = __raw_readl(pll->con_reg + 4);
-       mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
+       mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ?
+                               PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK);
        pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
        sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
        kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK :
                                        pll_con1 & PLL46XX_KDIV_MASK;
 
-       shift = pll->type == pll_4600 ? 16 : 10;
+       shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10;
+
        fvco *= (mdiv << shift) + kdiv;
        do_div(fvco, (pdiv << sdiv));
        fvco >>= shift;
@@ -573,14 +577,21 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate,
                lock = 0xffff;
 
        /* Set PLL PMS and VSEL values. */
-       con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
+       if (pll->type == pll_1460x) {
+               con0 &= ~((PLL1460X_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
+                       (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) |
+                       (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT));
+       } else {
+               con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
                        (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) |
                        (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT) |
                        (PLL46XX_VSEL_MASK << PLL46XX_VSEL_SHIFT));
+               con0 |= rate->vsel << PLL46XX_VSEL_SHIFT;
+       }
+
        con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) |
                        (rate->pdiv << PLL46XX_PDIV_SHIFT) |
-                       (rate->sdiv << PLL46XX_SDIV_SHIFT) |
-                       (rate->vsel << PLL46XX_VSEL_SHIFT);
+                       (rate->sdiv << PLL46XX_SDIV_SHIFT);
 
        /* Set PLL K, MFR and MRR values. */
        con1 = __raw_readl(pll->con_reg + 0x4);
@@ -1190,6 +1201,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
        /* clk_ops for 35xx and 2550 are similar */
        case pll_35xx:
        case pll_2550:
+       case pll_1450x:
+       case pll_1451x:
+       case pll_1452x:
                if (!pll->rate_table)
                        init.ops = &samsung_pll35xx_clk_min_ops;
                else
@@ -1223,6 +1237,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
        case pll_4600:
        case pll_4650:
        case pll_4650c:
+       case pll_1460x:
                if (!pll->rate_table)
                        init.ops = &samsung_pll46xx_clk_min_ops;
                else
index c0ed4d41fd90d96adb8f3c465b71e016c7bf787e..213de9af8b4f2ea34e9258ce9df3373f9571f712 100644 (file)
@@ -33,6 +33,10 @@ enum samsung_pll_type {
        pll_s3c2440_mpll,
        pll_2550xx,
        pll_2650xx,
+       pll_1450x,
+       pll_1451x,
+       pll_1452x,
+       pll_1460x,
 };
 
 #define PLL_35XX_RATE(_rate, _m, _p, _s)                       \
index deab84d9f37deec161070fc372f6756a90369a43..4bda54095a16a0f3a1a670d4e949a4267f411041 100644 (file)
  * clock framework for Samsung platforms.
 */
 
+#include <linux/of_address.h>
 #include <linux/syscore_ops.h>
+
 #include "clk.h"
 
+static LIST_HEAD(clock_reg_cache_list);
+
 void samsung_clk_save(void __iomem *base,
                                    struct samsung_clk_reg_dump *rd,
                                    unsigned int num_regs)
@@ -281,7 +285,6 @@ void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
  * obtain the clock speed of all external fixed clock sources from device
  * tree and register it
  */
-#ifdef CONFIG_OF
 void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx,
                        struct samsung_fixed_rate_clock *fixed_rate_clk,
                        unsigned int nr_fixed_rate_clk,
@@ -298,7 +301,6 @@ void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx,
        }
        samsung_clk_register_fixed_rate(ctx, fixed_rate_clk, nr_fixed_rate_clk);
 }
-#endif
 
 /* utility function to get the rate of a specified clock */
 unsigned long _get_rate(const char *clk_name)
@@ -313,3 +315,99 @@ unsigned long _get_rate(const char *clk_name)
 
        return clk_get_rate(clk);
 }
+
+#ifdef CONFIG_PM_SLEEP
+static int samsung_clk_suspend(void)
+{
+       struct samsung_clock_reg_cache *reg_cache;
+
+       list_for_each_entry(reg_cache, &clock_reg_cache_list, node)
+               samsung_clk_save(reg_cache->reg_base, reg_cache->rdump,
+                               reg_cache->rd_num);
+       return 0;
+}
+
+static void samsung_clk_resume(void)
+{
+       struct samsung_clock_reg_cache *reg_cache;
+
+       list_for_each_entry(reg_cache, &clock_reg_cache_list, node)
+               samsung_clk_restore(reg_cache->reg_base, reg_cache->rdump,
+                               reg_cache->rd_num);
+}
+
+static struct syscore_ops samsung_clk_syscore_ops = {
+       .suspend = samsung_clk_suspend,
+       .resume = samsung_clk_resume,
+};
+
+static void samsung_clk_sleep_init(void __iomem *reg_base,
+               const unsigned long *rdump,
+               unsigned long nr_rdump)
+{
+       struct samsung_clock_reg_cache *reg_cache;
+
+       reg_cache = kzalloc(sizeof(struct samsung_clock_reg_cache),
+                       GFP_KERNEL);
+       if (!reg_cache)
+               panic("could not allocate register reg_cache.\n");
+       reg_cache->rdump = samsung_clk_alloc_reg_dump(rdump, nr_rdump);
+
+       if (!reg_cache->rdump)
+               panic("could not allocate register dump storage.\n");
+
+       if (list_empty(&clock_reg_cache_list))
+               register_syscore_ops(&samsung_clk_syscore_ops);
+
+       reg_cache->reg_base = reg_base;
+       reg_cache->rd_num = nr_rdump;
+       list_add_tail(&reg_cache->node, &clock_reg_cache_list);
+}
+
+#else
+static void samsung_clk_sleep_init(void __iomem *reg_base,
+               const unsigned long *rdump,
+               unsigned long nr_rdump) {}
+#endif
+
+/*
+ * Common function which registers plls, muxes, dividers and gates
+ * for each CMU. It also add CMU register list to register cache.
+ */
+void __init samsung_cmu_register_one(struct device_node *np,
+                       struct samsung_cmu_info *cmu)
+{
+       void __iomem *reg_base;
+       struct samsung_clk_provider *ctx;
+
+       reg_base = of_iomap(np, 0);
+       if (!reg_base)
+               panic("%s: failed to map registers\n", __func__);
+
+       ctx = samsung_clk_init(np, reg_base, cmu->nr_clk_ids);
+       if (!ctx)
+               panic("%s: unable to alllocate ctx\n", __func__);
+
+       if (cmu->pll_clks)
+               samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks,
+                       reg_base);
+       if (cmu->mux_clks)
+               samsung_clk_register_mux(ctx, cmu->mux_clks,
+                       cmu->nr_mux_clks);
+       if (cmu->div_clks)
+               samsung_clk_register_div(ctx, cmu->div_clks, cmu->nr_div_clks);
+       if (cmu->gate_clks)
+               samsung_clk_register_gate(ctx, cmu->gate_clks,
+                       cmu->nr_gate_clks);
+       if (cmu->fixed_clks)
+               samsung_clk_register_fixed_rate(ctx, cmu->fixed_clks,
+                       cmu->nr_fixed_clks);
+       if (cmu->fixed_factor_clks)
+               samsung_clk_register_fixed_factor(ctx, cmu->fixed_factor_clks,
+                       cmu->nr_fixed_factor_clks);
+       if (cmu->clk_regs)
+               samsung_clk_sleep_init(reg_base, cmu->clk_regs,
+                       cmu->nr_clk_regs);
+
+       samsung_clk_of_add_provider(np, ctx);
+}
index 66ab36b5cef1018de647434cc0848f549b546ab2..8acabe1f32c4d4f13264eb26088b237778becf6b 100644 (file)
 #ifndef __SAMSUNG_CLK_H
 #define __SAMSUNG_CLK_H
 
-#include <linux/clk.h>
 #include <linux/clkdev.h>
-#include <linux/io.h>
 #include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
 #include "clk-pll.h"
 
 /**
  * struct samsung_clk_provider: information about clock provider
  * @reg_base: virtual address for the register base.
  * @clk_data: holds clock related data like clk* and number of clocks.
- * @lock: maintains exclusion bwtween callbacks for a given clock-provider.
+ * @lock: maintains exclusion between callbacks for a given clock-provider.
  */
 struct samsung_clk_provider {
        void __iomem *reg_base;
@@ -324,6 +320,40 @@ struct samsung_pll_clock {
        __PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE,     \
                _lock, _con, _rtable, _alias)
 
+struct samsung_clock_reg_cache {
+       struct list_head node;
+       void __iomem *reg_base;
+       struct samsung_clk_reg_dump *rdump;
+       unsigned int rd_num;
+};
+
+struct samsung_cmu_info {
+       /* list of pll clocks and respective count */
+       struct samsung_pll_clock *pll_clks;
+       unsigned int nr_pll_clks;
+       /* list of mux clocks and respective count */
+       struct samsung_mux_clock *mux_clks;
+       unsigned int nr_mux_clks;
+       /* list of div clocks and respective count */
+       struct samsung_div_clock *div_clks;
+       unsigned int nr_div_clks;
+       /* list of gate clocks and respective count */
+       struct samsung_gate_clock *gate_clks;
+       unsigned int nr_gate_clks;
+       /* list of fixed clocks and respective count */
+       struct samsung_fixed_rate_clock *fixed_clks;
+       unsigned int nr_fixed_clks;
+       /* list of fixed factor clocks and respective count */
+       struct samsung_fixed_factor_clock *fixed_factor_clks;
+       unsigned int nr_fixed_factor_clks;
+       /* total number of clocks with IDs assigned*/
+       unsigned int nr_clk_ids;
+
+       /* list and number of clocks registers */
+       unsigned long *clk_regs;
+       unsigned int nr_clk_regs;
+};
+
 extern struct samsung_clk_provider *__init samsung_clk_init(
                        struct device_node *np, void __iomem *base,
                        unsigned long nr_clks);
@@ -362,6 +392,9 @@ extern void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
                        struct samsung_pll_clock *pll_list,
                        unsigned int nr_clk, void __iomem *base);
 
+extern void __init samsung_cmu_register_one(struct device_node *,
+                       struct samsung_cmu_info *);
+
 extern unsigned long _get_rate(const char *clk_name);
 
 extern void samsung_clk_save(void __iomem *base,
index f065f694cb65699705def0036c3f47e903e813ae..639241e31e03ec244907761ef430ed95bc53adde 100644 (file)
@@ -32,6 +32,9 @@ struct div6_clock {
        struct clk_hw hw;
        void __iomem *reg;
        unsigned int div;
+       u32 src_shift;
+       u32 src_width;
+       u8 *parents;
 };
 
 #define to_div6_clock(_hw) container_of(_hw, struct div6_clock, hw)
@@ -39,8 +42,11 @@ struct div6_clock {
 static int cpg_div6_clock_enable(struct clk_hw *hw)
 {
        struct div6_clock *clock = to_div6_clock(hw);
+       u32 val;
 
-       clk_writel(CPG_DIV6_DIV(clock->div - 1), clock->reg);
+       val = (clk_readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP))
+           | CPG_DIV6_DIV(clock->div - 1);
+       clk_writel(val, clock->reg);
 
        return 0;
 }
@@ -52,7 +58,7 @@ static void cpg_div6_clock_disable(struct clk_hw *hw)
        /* DIV6 clocks require the divisor field to be non-zero when stopping
         * the clock.
         */
-       clk_writel(CPG_DIV6_CKSTP | CPG_DIV6_DIV(CPG_DIV6_DIV_MASK),
+       clk_writel(clk_readl(clock->reg) | CPG_DIV6_CKSTP | CPG_DIV6_DIV_MASK,
                   clock->reg);
 }
 
@@ -94,12 +100,53 @@ static int cpg_div6_clock_set_rate(struct clk_hw *hw, unsigned long rate,
 {
        struct div6_clock *clock = to_div6_clock(hw);
        unsigned int div = cpg_div6_clock_calc_div(rate, parent_rate);
+       u32 val;
 
        clock->div = div;
 
+       val = clk_readl(clock->reg) & ~CPG_DIV6_DIV_MASK;
        /* Only program the new divisor if the clock isn't stopped. */
-       if (!(clk_readl(clock->reg) & CPG_DIV6_CKSTP))
-               clk_writel(CPG_DIV6_DIV(clock->div - 1), clock->reg);
+       if (!(val & CPG_DIV6_CKSTP))
+               clk_writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg);
+
+       return 0;
+}
+
+static u8 cpg_div6_clock_get_parent(struct clk_hw *hw)
+{
+       struct div6_clock *clock = to_div6_clock(hw);
+       unsigned int i;
+       u8 hw_index;
+
+       if (clock->src_width == 0)
+               return 0;
+
+       hw_index = (clk_readl(clock->reg) >> clock->src_shift) &
+                  (BIT(clock->src_width) - 1);
+       for (i = 0; i < __clk_get_num_parents(hw->clk); i++) {
+               if (clock->parents[i] == hw_index)
+                       return i;
+       }
+
+       pr_err("%s: %s DIV6 clock set to invalid parent %u\n",
+              __func__, __clk_get_name(hw->clk), hw_index);
+       return 0;
+}
+
+static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index)
+{
+       struct div6_clock *clock = to_div6_clock(hw);
+       u8 hw_index;
+       u32 mask;
+
+       if (index >= __clk_get_num_parents(hw->clk))
+               return -EINVAL;
+
+       mask = ~((BIT(clock->src_width) - 1) << clock->src_shift);
+       hw_index = clock->parents[index];
+
+       clk_writel((clk_readl(clock->reg) & mask) |
+               (hw_index << clock->src_shift), clock->reg);
 
        return 0;
 }
@@ -108,6 +155,8 @@ static const struct clk_ops cpg_div6_clock_ops = {
        .enable = cpg_div6_clock_enable,
        .disable = cpg_div6_clock_disable,
        .is_enabled = cpg_div6_clock_is_enabled,
+       .get_parent = cpg_div6_clock_get_parent,
+       .set_parent = cpg_div6_clock_set_parent,
        .recalc_rate = cpg_div6_clock_recalc_rate,
        .round_rate = cpg_div6_clock_round_rate,
        .set_rate = cpg_div6_clock_set_rate,
@@ -115,20 +164,33 @@ static const struct clk_ops cpg_div6_clock_ops = {
 
 static void __init cpg_div6_clock_init(struct device_node *np)
 {
+       unsigned int num_parents, valid_parents;
+       const char **parent_names;
        struct clk_init_data init;
        struct div6_clock *clock;
-       const char *parent_name;
        const char *name;
        struct clk *clk;
+       unsigned int i;
        int ret;
 
        clock = kzalloc(sizeof(*clock), GFP_KERNEL);
-       if (!clock) {
-               pr_err("%s: failed to allocate %s DIV6 clock\n",
+       if (!clock)
+               return;
+
+       num_parents = of_clk_get_parent_count(np);
+       if (num_parents < 1) {
+               pr_err("%s: no parent found for %s DIV6 clock\n",
                       __func__, np->name);
                return;
        }
 
+       clock->parents = kmalloc_array(num_parents, sizeof(*clock->parents),
+               GFP_KERNEL);
+       parent_names = kmalloc_array(num_parents, sizeof(*parent_names),
+                               GFP_KERNEL);
+       if (!parent_names)
+               return;
+
        /* Remap the clock register and read the divisor. Disabling the
         * clock overwrites the divisor, so we need to cache its value for the
         * enable operation.
@@ -150,9 +212,34 @@ static void __init cpg_div6_clock_init(struct device_node *np)
                goto error;
        }
 
-       parent_name = of_clk_get_parent_name(np, 0);
-       if (parent_name == NULL) {
-               pr_err("%s: failed to get %s DIV6 clock parent name\n",
+
+       for (i = 0, valid_parents = 0; i < num_parents; i++) {
+               const char *name = of_clk_get_parent_name(np, i);
+
+               if (name) {
+                       parent_names[valid_parents] = name;
+                       clock->parents[valid_parents] = i;
+                       valid_parents++;
+               }
+       }
+
+       switch (num_parents) {
+       case 1:
+               /* fixed parent clock */
+               clock->src_shift = clock->src_width = 0;
+               break;
+       case 4:
+               /* clock with EXSRC bits 6-7 */
+               clock->src_shift = 6;
+               clock->src_width = 2;
+               break;
+       case 8:
+               /* VCLK with EXSRC bits 12-14 */
+               clock->src_shift = 12;
+               clock->src_width = 3;
+               break;
+       default:
+               pr_err("%s: invalid number of parents for DIV6 clock %s\n",
                       __func__, np->name);
                goto error;
        }
@@ -161,8 +248,8 @@ static void __init cpg_div6_clock_init(struct device_node *np)
        init.name = name;
        init.ops = &cpg_div6_clock_ops;
        init.flags = CLK_IS_BASIC;
-       init.parent_names = &parent_name;
-       init.num_parents = 1;
+       init.parent_names = parent_names;
+       init.num_parents = valid_parents;
 
        clock->hw.init = &init;
 
@@ -175,11 +262,13 @@ static void __init cpg_div6_clock_init(struct device_node *np)
 
        of_clk_add_provider(np, of_clk_src_simple_get, clk);
 
+       kfree(parent_names);
        return;
 
 error:
        if (clock->reg)
                iounmap(clock->reg);
+       kfree(parent_names);
        kfree(clock);
 }
 CLK_OF_DECLARE(cpg_div6_clk, "renesas,cpg-div6-clock", cpg_div6_clock_init);
index 7ddc2b5538466737fbdc0e05ca3c58a153094b26..a66953c0f43094a4b96a816fb0d4ff37bfedf466 100644 (file)
@@ -7,6 +7,7 @@ obj-y += clk-a10-hosc.o
 obj-y += clk-a20-gmac.o
 obj-y += clk-mod0.o
 obj-y += clk-sun8i-mbus.o
+obj-y += clk-sun9i-core.o
 
 obj-$(CONFIG_MFD_SUN6I_PRCM) += \
        clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
index 5296fd6dd7b3f9a9c7103b3fd7ae63b1f0259963..0dcf4f205fb86f1510dfa8b74f20311e301613ce 100644 (file)
@@ -53,6 +53,11 @@ static DEFINE_SPINLOCK(gmac_lock);
 #define SUN7I_A20_GMAC_MASK    0x3
 #define SUN7I_A20_GMAC_PARENTS 2
 
+static u32 sun7i_a20_gmac_mux_table[SUN7I_A20_GMAC_PARENTS] = {
+       0x00, /* Select mii_phy_tx_clk */
+       0x02, /* Select gmac_int_tx_clk */
+};
+
 static void __init sun7i_a20_gmac_clk_setup(struct device_node *node)
 {
        struct clk *clk;
@@ -90,7 +95,7 @@ static void __init sun7i_a20_gmac_clk_setup(struct device_node *node)
        gate->lock = &gmac_lock;
        mux->reg = reg;
        mux->mask = SUN7I_A20_GMAC_MASK;
-       mux->flags = CLK_MUX_INDEX_BIT;
+       mux->table = sun7i_a20_gmac_mux_table;
        mux->lock = &gmac_lock;
 
        clk = clk_register_composite(NULL, clk_name,
index f83ba097126c6e72c22517a66f17034474e8ebf2..62e08fb58554cbe8d4bf8f1c5a08f08bbd58ec68 100644 (file)
@@ -81,7 +81,7 @@ static long clk_factors_round_rate(struct clk_hw *hw, unsigned long rate,
 
 static long clk_factors_determine_rate(struct clk_hw *hw, unsigned long rate,
                                       unsigned long *best_parent_rate,
-                                      struct clk **best_parent_p)
+                                      struct clk_hw **best_parent_p)
 {
        struct clk *clk = hw->clk, *parent, *best_parent = NULL;
        int i, num_parents;
@@ -108,7 +108,7 @@ static long clk_factors_determine_rate(struct clk_hw *hw, unsigned long rate,
        }
 
        if (best_parent)
-               *best_parent_p = best_parent;
+               *best_parent_p = __clk_get_hw(best_parent);
        *best_parent_rate = best;
 
        return best_child_rate;
@@ -224,7 +224,7 @@ struct clk * __init sunxi_factors_register(struct device_node *node,
                /* set up gate properties */
                mux->reg = reg;
                mux->shift = data->mux;
-               mux->mask = SUNXI_FACTORS_MUX_MASK;
+               mux->mask = data->muxmask;
                mux->lock = factors->lock;
                mux_hw = &mux->hw;
        }
index 9913840018d3fdb4f4717a4636b68f8dc6f4a6e6..912238fde1324224863035da8a5836b5c276e8a0 100644 (file)
@@ -7,8 +7,6 @@
 
 #define SUNXI_FACTORS_NOT_APPLICABLE   (0)
 
-#define SUNXI_FACTORS_MUX_MASK 0x3
-
 struct clk_factors_config {
        u8 nshift;
        u8 nwidth;
@@ -24,6 +22,7 @@ struct clk_factors_config {
 struct factors_data {
        int enable;
        int mux;
+       int muxmask;
        struct clk_factors_config *table;
        void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
        const char *name;
index 4a563850ee6ee3a158a286b8a1cfb37ed713569b..da0524eaee9406aff6c2d73f8b56b82c12360a16 100644 (file)
@@ -70,6 +70,7 @@ static struct clk_factors_config sun4i_a10_mod0_config = {
 static const struct factors_data sun4i_a10_mod0_data __initconst = {
        .enable = 31,
        .mux = 24,
+       .muxmask = BIT(1) | BIT(0),
        .table = &sun4i_a10_mod0_config,
        .getter = sun4i_a10_get_mod0_factors,
 };
index acca53290be26c8f5c6aea33ee92b7d7f590703d..3d282fb8f85cc204d84c182aa4b16ae2181ea5e9 100644 (file)
@@ -46,7 +46,7 @@ static unsigned long ar100_recalc_rate(struct clk_hw *hw,
 
 static long ar100_determine_rate(struct clk_hw *hw, unsigned long rate,
                                 unsigned long *best_parent_rate,
-                                struct clk **best_parent_clk)
+                                struct clk_hw **best_parent_clk)
 {
        int nparents = __clk_get_num_parents(hw->clk);
        long best_rate = -EINVAL;
@@ -100,7 +100,7 @@ static long ar100_determine_rate(struct clk_hw *hw, unsigned long rate,
 
                tmp_rate = (parent_rate >> shift) / div;
                if (!*best_parent_clk || tmp_rate > best_rate) {
-                       *best_parent_clk = parent;
+                       *best_parent_clk = __clk_get_hw(parent);
                        *best_parent_rate = parent_rate;
                        best_rate = tmp_rate;
                }
index 8e49b44cee41d9df81ffa666cf812a3fffcdd7af..ef49786eefd3caa5b6f856287635a973213a14b3 100644 (file)
@@ -60,6 +60,7 @@ static struct clk_factors_config sun8i_a23_mbus_config = {
 static const struct factors_data sun8i_a23_mbus_data __initconst = {
        .enable = 31,
        .mux = 24,
+       .muxmask = BIT(1) | BIT(0),
        .table = &sun8i_a23_mbus_config,
        .getter = sun8i_a23_get_mbus_factors,
 };
diff --git a/drivers/clk/sunxi/clk-sun9i-core.c b/drivers/clk/sunxi/clk-sun9i-core.c
new file mode 100644 (file)
index 0000000..3cb9036
--- /dev/null
@@ -0,0 +1,271 @@
+/*
+ * Copyright 2014 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/log2.h>
+
+#include "clk-factors.h"
+
+
+/**
+ * sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL1
+ * PLL4 rate is calculated as follows
+ * rate = (parent_rate * n >> p) / (m + 1);
+ * parent_rate is always 24Mhz
+ *
+ * p and m are named div1 and div2 in Allwinner's SDK
+ */
+
+static void sun9i_a80_get_pll4_factors(u32 *freq, u32 parent_rate,
+                                      u8 *n, u8 *k, u8 *m, u8 *p)
+{
+       int div;
+
+       /* Normalize value to a 6M multiple */
+       div = DIV_ROUND_UP(*freq, 6000000);
+
+       /* divs above 256 cannot be odd */
+       if (div > 256)
+               div = round_up(div, 2);
+
+       /* divs above 512 must be a multiple of 4 */
+       if (div > 512)
+               div = round_up(div, 4);
+
+       *freq = 6000000 * div;
+
+       /* we were called to round the frequency, we can now return */
+       if (n == NULL)
+               return;
+
+       /* p will be 1 for divs under 512 */
+       if (div < 512)
+               *p = 1;
+       else
+               *p = 0;
+
+       /* m will be 1 if div is odd */
+       if (div & 1)
+               *m = 1;
+       else
+               *m = 0;
+
+       /* calculate a suitable n based on m and p */
+       *n = div / (*p + 1) / (*m + 1);
+}
+
+static struct clk_factors_config sun9i_a80_pll4_config = {
+       .mshift = 18,
+       .mwidth = 1,
+       .nshift = 8,
+       .nwidth = 8,
+       .pshift = 16,
+       .pwidth = 1,
+};
+
+static const struct factors_data sun9i_a80_pll4_data __initconst = {
+       .enable = 31,
+       .table = &sun9i_a80_pll4_config,
+       .getter = sun9i_a80_get_pll4_factors,
+};
+
+static DEFINE_SPINLOCK(sun9i_a80_pll4_lock);
+
+static void __init sun9i_a80_pll4_setup(struct device_node *node)
+{
+       sunxi_factors_register(node, &sun9i_a80_pll4_data, &sun9i_a80_pll4_lock);
+}
+CLK_OF_DECLARE(sun9i_a80_pll4, "allwinner,sun9i-a80-pll4-clk", sun9i_a80_pll4_setup);
+
+
+/**
+ * sun9i_a80_get_gt_factors() - calculates m factor for GT
+ * GT rate is calculated as follows
+ * rate = parent_rate / (m + 1);
+ */
+
+static void sun9i_a80_get_gt_factors(u32 *freq, u32 parent_rate,
+                                    u8 *n, u8 *k, u8 *m, u8 *p)
+{
+       u32 div;
+
+       if (parent_rate < *freq)
+               *freq = parent_rate;
+
+       div = DIV_ROUND_UP(parent_rate, *freq);
+
+       /* maximum divider is 4 */
+       if (div > 4)
+               div = 4;
+
+       *freq = parent_rate / div;
+
+       /* we were called to round the frequency, we can now return */
+       if (!m)
+               return;
+
+       *m = div;
+}
+
+static struct clk_factors_config sun9i_a80_gt_config = {
+       .mshift = 0,
+       .mwidth = 2,
+};
+
+static const struct factors_data sun9i_a80_gt_data __initconst = {
+       .mux = 24,
+       .muxmask = BIT(1) | BIT(0),
+       .table = &sun9i_a80_gt_config,
+       .getter = sun9i_a80_get_gt_factors,
+};
+
+static DEFINE_SPINLOCK(sun9i_a80_gt_lock);
+
+static void __init sun9i_a80_gt_setup(struct device_node *node)
+{
+       struct clk *gt = sunxi_factors_register(node, &sun9i_a80_gt_data,
+                                               &sun9i_a80_gt_lock);
+
+       /* The GT bus clock needs to be always enabled */
+       __clk_get(gt);
+       clk_prepare_enable(gt);
+}
+CLK_OF_DECLARE(sun9i_a80_gt, "allwinner,sun9i-a80-gt-clk", sun9i_a80_gt_setup);
+
+
+/**
+ * sun9i_a80_get_ahb_factors() - calculates p factor for AHB0/1/2
+ * AHB rate is calculated as follows
+ * rate = parent_rate >> p;
+ */
+
+static void sun9i_a80_get_ahb_factors(u32 *freq, u32 parent_rate,
+                                     u8 *n, u8 *k, u8 *m, u8 *p)
+{
+       u32 _p;
+
+       if (parent_rate < *freq)
+               *freq = parent_rate;
+
+       _p = order_base_2(DIV_ROUND_UP(parent_rate, *freq));
+
+       /* maximum p is 3 */
+       if (_p > 3)
+               _p = 3;
+
+       *freq = parent_rate >> _p;
+
+       /* we were called to round the frequency, we can now return */
+       if (!p)
+               return;
+
+       *p = _p;
+}
+
+static struct clk_factors_config sun9i_a80_ahb_config = {
+       .pshift = 0,
+       .pwidth = 2,
+};
+
+static const struct factors_data sun9i_a80_ahb_data __initconst = {
+       .mux = 24,
+       .muxmask = BIT(1) | BIT(0),
+       .table = &sun9i_a80_ahb_config,
+       .getter = sun9i_a80_get_ahb_factors,
+};
+
+static DEFINE_SPINLOCK(sun9i_a80_ahb_lock);
+
+static void __init sun9i_a80_ahb_setup(struct device_node *node)
+{
+       sunxi_factors_register(node, &sun9i_a80_ahb_data, &sun9i_a80_ahb_lock);
+}
+CLK_OF_DECLARE(sun9i_a80_ahb, "allwinner,sun9i-a80-ahb-clk", sun9i_a80_ahb_setup);
+
+
+static const struct factors_data sun9i_a80_apb0_data __initconst = {
+       .mux = 24,
+       .muxmask = BIT(0),
+       .table = &sun9i_a80_ahb_config,
+       .getter = sun9i_a80_get_ahb_factors,
+};
+
+static DEFINE_SPINLOCK(sun9i_a80_apb0_lock);
+
+static void __init sun9i_a80_apb0_setup(struct device_node *node)
+{
+       sunxi_factors_register(node, &sun9i_a80_apb0_data, &sun9i_a80_apb0_lock);
+}
+CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-clk", sun9i_a80_apb0_setup);
+
+
+/**
+ * sun9i_a80_get_apb1_factors() - calculates m, p factors for APB1
+ * APB1 rate is calculated as follows
+ * rate = (parent_rate >> p) / (m + 1);
+ */
+
+static void sun9i_a80_get_apb1_factors(u32 *freq, u32 parent_rate,
+                                      u8 *n, u8 *k, u8 *m, u8 *p)
+{
+       u32 div;
+       u8 calcm, calcp;
+
+       if (parent_rate < *freq)
+               *freq = parent_rate;
+
+       div = DIV_ROUND_UP(parent_rate, *freq);
+
+       /* Highest possible divider is 256 (p = 3, m = 31) */
+       if (div > 256)
+               div = 256;
+
+       calcp = order_base_2(div);
+       calcm = (parent_rate >> calcp) - 1;
+       *freq = (parent_rate >> calcp) / (calcm + 1);
+
+       /* we were called to round the frequency, we can now return */
+       if (n == NULL)
+               return;
+
+       *m = calcm;
+       *p = calcp;
+}
+
+static struct clk_factors_config sun9i_a80_apb1_config = {
+       .mshift = 0,
+       .mwidth = 5,
+       .pshift = 16,
+       .pwidth = 2,
+};
+
+static const struct factors_data sun9i_a80_apb1_data __initconst = {
+       .mux = 24,
+       .muxmask = BIT(0),
+       .table = &sun9i_a80_apb1_config,
+       .getter = sun9i_a80_get_apb1_factors,
+};
+
+static DEFINE_SPINLOCK(sun9i_a80_apb1_lock);
+
+static void __init sun9i_a80_apb1_setup(struct device_node *node)
+{
+       sunxi_factors_register(node, &sun9i_a80_apb1_data, &sun9i_a80_apb1_lock);
+}
+CLK_OF_DECLARE(sun9i_a80_apb1, "allwinner,sun9i-a80-apb1-clk", sun9i_a80_apb1_setup);
index d5dc951264cab957bcf2522bc61a9c62395c6432..570202582dcfef88bcd721f99250e6a82bfb3493 100644 (file)
@@ -245,9 +245,9 @@ static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
 }
 
 /**
- * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6
- * PLL6 rate is calculated as follows
- * rate = parent_rate * n * (k + 1) / 2
+ * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6x2
+ * PLL6x2 rate is calculated as follows
+ * rate = parent_rate * (n + 1) * (k + 1)
  * parent_rate is always 24Mhz
  */
 
@@ -256,13 +256,7 @@ static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate,
 {
        u8 div;
 
-       /*
-        * We always have 24MHz / 2, so we can just say that our
-        * parent clock is 12MHz.
-        */
-       parent_rate = parent_rate / 2;
-
-       /* Normalize value to a parent_rate multiple (24M / 2) */
+       /* Normalize value to a parent_rate multiple (24M) */
        div = *freq / parent_rate;
        *freq = parent_rate * div;
 
@@ -274,7 +268,7 @@ static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate,
        if (*k > 3)
                *k = 3;
 
-       *n = DIV_ROUND_UP(div, (*k+1));
+       *n = DIV_ROUND_UP(div, (*k+1)) - 1;
 }
 
 /**
@@ -445,6 +439,7 @@ static struct clk_factors_config sun6i_a31_pll6_config = {
        .nwidth = 5,
        .kshift = 4,
        .kwidth = 2,
+       .n_start = 1,
 };
 
 static struct clk_factors_config sun4i_apb1_config = {
@@ -504,9 +499,12 @@ static const struct factors_data sun6i_a31_pll6_data __initconst = {
        .enable = 31,
        .table = &sun6i_a31_pll6_config,
        .getter = sun6i_a31_get_pll6_factors,
+       .name = "pll6x2",
 };
 
 static const struct factors_data sun4i_apb1_data __initconst = {
+       .mux = 24,
+       .muxmask = BIT(1) | BIT(0),
        .table = &sun4i_apb1_config,
        .getter = sun4i_get_apb1_factors,
 };
@@ -514,6 +512,7 @@ static const struct factors_data sun4i_apb1_data __initconst = {
 static const struct factors_data sun7i_a20_out_data __initconst = {
        .enable = 31,
        .mux = 24,
+       .muxmask = BIT(1) | BIT(0),
        .table = &sun7i_a20_out_config,
        .getter = sun7i_a20_get_out_factors,
 };
@@ -544,10 +543,6 @@ static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
        .shift = 12,
 };
 
-static const struct mux_data sun4i_apb1_mux_data __initconst = {
-       .shift = 24,
-};
-
 static void __init sunxi_mux_clk_setup(struct device_node *node,
                                       struct mux_data *data)
 {
@@ -633,12 +628,6 @@ static const struct div_data sun4i_apb0_data __initconst = {
        .table  = sun4i_apb0_table,
 };
 
-static const struct div_data sun6i_a31_apb2_div_data __initconst = {
-       .shift  = 0,
-       .pow    = 0,
-       .width  = 4,
-};
-
 static void __init sunxi_divider_clk_setup(struct device_node *node,
                                           struct div_data *data)
 {
@@ -757,6 +746,18 @@ static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = {
        .mask = {0x25386742, 0x2505111},
 };
 
+static const struct gates_data sun9i_a80_ahb0_gates_data __initconst = {
+       .mask = {0xF5F12B},
+};
+
+static const struct gates_data sun9i_a80_ahb1_gates_data __initconst = {
+       .mask = {0x1E20003},
+};
+
+static const struct gates_data sun9i_a80_ahb2_gates_data __initconst = {
+       .mask = {0x9B7},
+};
+
 static const struct gates_data sun4i_apb0_gates_data __initconst = {
        .mask = {0x4EF},
 };
@@ -773,6 +774,10 @@ static const struct gates_data sun7i_a20_apb0_gates_data __initconst = {
        .mask = { 0x4ff },
 };
 
+static const struct gates_data sun9i_a80_apb0_gates_data __initconst = {
+       .mask = {0xEB822},
+};
+
 static const struct gates_data sun4i_apb1_gates_data __initconst = {
        .mask = {0xFF00F7},
 };
@@ -801,6 +806,10 @@ static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
        .mask = { 0xff80ff },
 };
 
+static const struct gates_data sun9i_a80_apb1_gates_data __initconst = {
+       .mask = {0x3F001F},
+};
+
 static const struct gates_data sun8i_a23_apb2_gates_data __initconst = {
        .mask = {0x1F0007},
 };
@@ -893,6 +902,7 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
 
 struct divs_data {
        const struct factors_data *factors; /* data for the factor clock */
+       int ndivs; /* number of children */
        struct {
                u8 fixed; /* is it a fixed divisor? if not... */
                struct clk_div_table *table; /* is it a table based divisor? */
@@ -912,6 +922,7 @@ static struct clk_div_table pll6_sata_tbl[] = {
 
 static const struct divs_data pll5_divs_data __initconst = {
        .factors = &sun4i_pll5_data,
+       .ndivs = 2,
        .div = {
                { .shift = 0, .pow = 0, }, /* M, DDR */
                { .shift = 16, .pow = 1, }, /* P, other */
@@ -920,12 +931,21 @@ static const struct divs_data pll5_divs_data __initconst = {
 
 static const struct divs_data pll6_divs_data __initconst = {
        .factors = &sun4i_pll6_data,
+       .ndivs = 2,
        .div = {
                { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
                { .fixed = 2 }, /* P, other */
        }
 };
 
+static const struct divs_data sun6i_a31_pll6_divs_data __initconst = {
+       .factors = &sun6i_a31_pll6_data,
+       .ndivs = 1,
+       .div = {
+               { .fixed = 2 }, /* normal output */
+       }
+};
+
 /**
  * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
  *
@@ -950,7 +970,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
        struct clk_fixed_factor *fix_factor;
        struct clk_divider *divider;
        void __iomem *reg;
-       int i = 0;
+       int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
        int flags, clkflags;
 
        /* Set up factor clock that we will be dividing */
@@ -973,7 +993,11 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
         * our RAM clock! */
        clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
 
-       for (i = 0; i < SUNXI_DIVS_MAX_QTY; i++) {
+       /* if number of children known, use it */
+       if (data->ndivs)
+               ndivs = data->ndivs;
+
+       for (i = 0; i < ndivs; i++) {
                if (of_property_read_string_index(node, "clock-output-names",
                                                  i, &clk_name) != 0)
                        break;
@@ -1062,7 +1086,6 @@ static const struct of_device_id clk_factors_match[] __initconst = {
        {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
        {.compatible = "allwinner,sun8i-a23-pll1-clk", .data = &sun8i_a23_pll1_data,},
        {.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
-       {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,},
        {.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
        {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
        {}
@@ -1074,7 +1097,6 @@ static const struct of_device_id clk_div_match[] __initconst = {
        {.compatible = "allwinner,sun8i-a23-axi-clk", .data = &sun8i_a23_axi_data,},
        {.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,},
        {.compatible = "allwinner,sun4i-a10-apb0-clk", .data = &sun4i_apb0_data,},
-       {.compatible = "allwinner,sun6i-a31-apb2-div-clk", .data = &sun6i_a31_apb2_div_data,},
        {}
 };
 
@@ -1082,13 +1104,13 @@ static const struct of_device_id clk_div_match[] __initconst = {
 static const struct of_device_id clk_divs_match[] __initconst = {
        {.compatible = "allwinner,sun4i-a10-pll5-clk", .data = &pll5_divs_data,},
        {.compatible = "allwinner,sun4i-a10-pll6-clk", .data = &pll6_divs_data,},
+       {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_divs_data,},
        {}
 };
 
 /* Matches for mux clocks */
 static const struct of_device_id clk_mux_match[] __initconst = {
        {.compatible = "allwinner,sun4i-a10-cpu-clk", .data = &sun4i_cpu_mux_data,},
-       {.compatible = "allwinner,sun4i-a10-apb1-mux-clk", .data = &sun4i_apb1_mux_data,},
        {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
        {}
 };
@@ -1102,16 +1124,21 @@ static const struct of_device_id clk_gates_match[] __initconst = {
        {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
        {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
        {.compatible = "allwinner,sun8i-a23-ahb1-gates-clk", .data = &sun8i_a23_ahb1_gates_data,},
+       {.compatible = "allwinner,sun9i-a80-ahb0-gates-clk", .data = &sun9i_a80_ahb0_gates_data,},
+       {.compatible = "allwinner,sun9i-a80-ahb1-gates-clk", .data = &sun9i_a80_ahb1_gates_data,},
+       {.compatible = "allwinner,sun9i-a80-ahb2-gates-clk", .data = &sun9i_a80_ahb2_gates_data,},
        {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
        {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
        {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
        {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
+       {.compatible = "allwinner,sun9i-a80-apb0-gates-clk", .data = &sun9i_a80_apb0_gates_data,},
        {.compatible = "allwinner,sun4i-a10-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
        {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
        {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
        {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
        {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
        {.compatible = "allwinner,sun8i-a23-apb1-gates-clk", .data = &sun8i_a23_apb1_gates_data,},
+       {.compatible = "allwinner,sun9i-a80-apb1-gates-clk", .data = &sun9i_a80_apb1_gates_data,},
        {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
        {.compatible = "allwinner,sun8i-a23-apb2-gates-clk", .data = &sun8i_a23_apb2_gates_data,},
        {.compatible = "allwinner,sun4i-a10-usb-clk", .data = &sun4i_a10_usb_gates_data,},
@@ -1200,3 +1227,9 @@ static void __init sun6i_init_clocks(struct device_node *node)
 }
 CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks);
 CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
+
+static void __init sun9i_init_clocks(struct device_node *node)
+{
+       sunxi_init_clocks(NULL, 0);
+}
+CLK_OF_DECLARE(sun9i_a80_clk_init, "allwinner,sun9i-a80", sun9i_init_clocks);
diff --git a/include/dt-bindings/clock/exynos4415.h b/include/dt-bindings/clock/exynos4415.h
new file mode 100644 (file)
index 0000000..7eed551
--- /dev/null
@@ -0,0 +1,360 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Chanwoo Choi <cw00.choi@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for Samsung Exynos4415 clock controllers.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H
+#define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H
+
+/*
+ * Let each exported clock get a unique index, which is used on DT-enabled
+ * platforms to lookup the clock from a clock specifier. These indices are
+ * therefore considered an ABI and so must not be changed. This implies
+ * that new clocks should be added either in free spaces between clock groups
+ * or at the end.
+ */
+
+/*
+ * Main CMU
+ */
+
+#define CLK_OSCSEL                     1
+#define CLK_FIN_PLL                    2
+#define CLK_FOUT_APLL                  3
+#define CLK_FOUT_MPLL                  4
+#define CLK_FOUT_EPLL                  5
+#define CLK_FOUT_G3D_PLL               6
+#define CLK_FOUT_ISP_PLL               7
+#define CLK_FOUT_DISP_PLL              8
+
+/* Muxes */
+#define CLK_MOUT_MPLL_USER_L           16
+#define CLK_MOUT_GDL                   17
+#define CLK_MOUT_MPLL_USER_R           18
+#define CLK_MOUT_GDR                   19
+#define CLK_MOUT_EBI                   20
+#define CLK_MOUT_ACLK_200              21
+#define CLK_MOUT_ACLK_160              22
+#define CLK_MOUT_ACLK_100              23
+#define CLK_MOUT_ACLK_266              24
+#define CLK_MOUT_G3D_PLL               25
+#define CLK_MOUT_EPLL                  26
+#define CLK_MOUT_EBI_1                 27
+#define CLK_MOUT_ISP_PLL               28
+#define CLK_MOUT_DISP_PLL              29
+#define CLK_MOUT_MPLL_USER_T           30
+#define CLK_MOUT_ACLK_400_MCUISP       31
+#define CLK_MOUT_G3D_PLLSRC            32
+#define CLK_MOUT_CSIS1                 33
+#define CLK_MOUT_CSIS0                 34
+#define CLK_MOUT_CAM1                  35
+#define CLK_MOUT_FIMC3_LCLK            36
+#define CLK_MOUT_FIMC2_LCLK            37
+#define CLK_MOUT_FIMC1_LCLK            38
+#define CLK_MOUT_FIMC0_LCLK            39
+#define CLK_MOUT_MFC                   40
+#define CLK_MOUT_MFC_1                 41
+#define CLK_MOUT_MFC_0                 42
+#define CLK_MOUT_G3D                   43
+#define CLK_MOUT_G3D_1                 44
+#define CLK_MOUT_G3D_0                 45
+#define CLK_MOUT_MIPI0                 46
+#define CLK_MOUT_FIMD0                 47
+#define CLK_MOUT_TSADC_ISP             48
+#define CLK_MOUT_UART_ISP              49
+#define CLK_MOUT_SPI1_ISP              50
+#define CLK_MOUT_SPI0_ISP              51
+#define CLK_MOUT_PWM_ISP               52
+#define CLK_MOUT_AUDIO0                        53
+#define CLK_MOUT_TSADC                 54
+#define CLK_MOUT_MMC2                  55
+#define CLK_MOUT_MMC1                  56
+#define CLK_MOUT_MMC0                  57
+#define CLK_MOUT_UART3                 58
+#define CLK_MOUT_UART2                 59
+#define CLK_MOUT_UART1                 60
+#define CLK_MOUT_UART0                 61
+#define CLK_MOUT_SPI2                  62
+#define CLK_MOUT_SPI1                  63
+#define CLK_MOUT_SPI0                  64
+#define CLK_MOUT_SPDIF                 65
+#define CLK_MOUT_AUDIO2                        66
+#define CLK_MOUT_AUDIO1                        67
+#define CLK_MOUT_MPLL_USER_C           68
+#define CLK_MOUT_HPM                   69
+#define CLK_MOUT_CORE                  70
+#define CLK_MOUT_APLL                  71
+#define CLK_MOUT_PXLASYNC_CSIS1_FIMC   72
+#define CLK_MOUT_PXLASYNC_CSIS0_FIMC   73
+#define CLK_MOUT_JPEG                  74
+#define CLK_MOUT_JPEG1                 75
+#define CLK_MOUT_JPEG0                 76
+#define CLK_MOUT_ACLK_ISP0_300         77
+#define CLK_MOUT_ACLK_ISP0_400         78
+#define CLK_MOUT_ACLK_ISP0_300_USER    79
+#define CLK_MOUT_ACLK_ISP1_300         80
+#define CLK_MOUT_ACLK_ISP1_300_USER    81
+#define CLK_MOUT_HDMI                  82
+
+/* Dividers */
+#define CLK_DIV_GPL                    90
+#define CLK_DIV_GDL                    91
+#define CLK_DIV_GPR                    92
+#define CLK_DIV_GDR                    93
+#define CLK_DIV_ACLK_400_MCUISP                94
+#define CLK_DIV_EBI                    95
+#define CLK_DIV_ACLK_200               96
+#define CLK_DIV_ACLK_160               97
+#define CLK_DIV_ACLK_100               98
+#define CLK_DIV_ACLK_266               99
+#define CLK_DIV_CSIS1                  100
+#define CLK_DIV_CSIS0                  101
+#define CLK_DIV_CAM1                   102
+#define CLK_DIV_FIMC3_LCLK             103
+#define CLK_DIV_FIMC2_LCLK             104
+#define CLK_DIV_FIMC1_LCLK             105
+#define CLK_DIV_FIMC0_LCLK             106
+#define CLK_DIV_TV_BLK                 107
+#define CLK_DIV_MFC                    108
+#define CLK_DIV_G3D                    109
+#define CLK_DIV_MIPI0_PRE              110
+#define CLK_DIV_MIPI0                  111
+#define CLK_DIV_FIMD0                  112
+#define CLK_DIV_UART_ISP               113
+#define CLK_DIV_SPI1_ISP_PRE           114
+#define CLK_DIV_SPI1_ISP               115
+#define CLK_DIV_SPI0_ISP_PRE           116
+#define CLK_DIV_SPI0_ISP               117
+#define CLK_DIV_PWM_ISP                        118
+#define CLK_DIV_PCM0                   119
+#define CLK_DIV_AUDIO0                 120
+#define CLK_DIV_TSADC_PRE              121
+#define CLK_DIV_TSADC                  122
+#define CLK_DIV_MMC1_PRE               123
+#define CLK_DIV_MMC1                   124
+#define CLK_DIV_MMC0_PRE               125
+#define CLK_DIV_MMC0                   126
+#define CLK_DIV_MMC2_PRE               127
+#define CLK_DIV_MMC2                   128
+#define CLK_DIV_UART3                  129
+#define CLK_DIV_UART2                  130
+#define CLK_DIV_UART1                  131
+#define CLK_DIV_UART0                  132
+#define CLK_DIV_SPI1_PRE               133
+#define CLK_DIV_SPI1                   134
+#define CLK_DIV_SPI0_PRE               135
+#define CLK_DIV_SPI0                   136
+#define CLK_DIV_SPI2_PRE               137
+#define CLK_DIV_SPI2                   138
+#define CLK_DIV_PCM2                   139
+#define CLK_DIV_AUDIO2                 140
+#define CLK_DIV_PCM1                   141
+#define CLK_DIV_AUDIO1                 142
+#define CLK_DIV_I2S1                   143
+#define CLK_DIV_PXLASYNC_CSIS1_FIMC    144
+#define CLK_DIV_PXLASYNC_CSIS0_FIMC    145
+#define CLK_DIV_JPEG                   146
+#define CLK_DIV_CORE2                  147
+#define CLK_DIV_APLL                   148
+#define CLK_DIV_PCLK_DBG               149
+#define CLK_DIV_ATB                    150
+#define CLK_DIV_PERIPH                 151
+#define CLK_DIV_COREM1                 152
+#define CLK_DIV_COREM0                 153
+#define CLK_DIV_CORE                   154
+#define CLK_DIV_HPM                    155
+#define CLK_DIV_COPY                   156
+
+/* Gates */
+#define CLK_ASYNC_G3D                  180
+#define CLK_ASYNC_MFCL                 181
+#define CLK_ASYNC_TVX                  182
+#define CLK_PPMULEFT                   183
+#define CLK_GPIO_LEFT                  184
+#define CLK_PPMUIMAGE                  185
+#define CLK_QEMDMA2                    186
+#define CLK_QEROTATOR                  187
+#define CLK_SMMUMDMA2                  188
+#define CLK_SMMUROTATOR                        189
+#define CLK_MDMA2                      190
+#define CLK_ROTATOR                    191
+#define CLK_ASYNC_ISPMX                        192
+#define CLK_ASYNC_MAUDIOX              193
+#define CLK_ASYNC_MFCR                 194
+#define CLK_ASYNC_FSYSD                        195
+#define CLK_ASYNC_LCD0X                        196
+#define CLK_ASYNC_CAMX                 197
+#define CLK_PPMURIGHT                  198
+#define CLK_GPIO_RIGHT                 199
+#define CLK_ANTIRBK_APBIF              200
+#define CLK_EFUSE_WRITER_APBIF         201
+#define CLK_MONOCNT                    202
+#define CLK_TZPC6                      203
+#define CLK_PROVISIONKEY1              204
+#define CLK_PROVISIONKEY0              205
+#define CLK_CMU_ISPPART                        206
+#define CLK_TMU_APBIF                  207
+#define CLK_KEYIF                      208
+#define CLK_RTC                                209
+#define CLK_WDT                                210
+#define CLK_MCT                                211
+#define CLK_SECKEY                     212
+#define CLK_HDMI_CEC                   213
+#define CLK_TZPC5                      214
+#define CLK_TZPC4                      215
+#define CLK_TZPC3                      216
+#define CLK_TZPC2                      217
+#define CLK_TZPC1                      218
+#define CLK_TZPC0                      219
+#define CLK_CMU_COREPART               220
+#define CLK_CMU_TOPPART                        221
+#define CLK_PMU_APBIF                  222
+#define CLK_SYSREG                     223
+#define CLK_CHIP_ID                    224
+#define CLK_SMMUFIMC_LITE2             225
+#define CLK_FIMC_LITE2                 226
+#define CLK_PIXELASYNCM1               227
+#define CLK_PIXELASYNCM0               228
+#define CLK_PPMUCAMIF                  229
+#define CLK_SMMUJPEG                   230
+#define CLK_SMMUFIMC3                  231
+#define CLK_SMMUFIMC2                  232
+#define CLK_SMMUFIMC1                  233
+#define CLK_SMMUFIMC0                  234
+#define CLK_JPEG                       235
+#define CLK_CSIS1                      236
+#define CLK_CSIS0                      237
+#define CLK_FIMC3                      238
+#define CLK_FIMC2                      239
+#define CLK_FIMC1                      240
+#define CLK_FIMC0                      241
+#define CLK_PPMUTV                     242
+#define CLK_SMMUTV                     243
+#define CLK_HDMI                       244
+#define CLK_MIXER                      245
+#define CLK_VP                         246
+#define CLK_PPMUMFC_R                  247
+#define CLK_PPMUMFC_L                  248
+#define CLK_SMMUMFC_R                  249
+#define CLK_SMMUMFC_L                  250
+#define CLK_MFC                                251
+#define CLK_PPMUG3D                    252
+#define CLK_G3D                                253
+#define CLK_PPMULCD0                   254
+#define CLK_SMMUFIMD0                  255
+#define CLK_DSIM0                      256
+#define CLK_SMIES                      257
+#define CLK_MIE0                       258
+#define CLK_FIMD0                      259
+#define CLK_TSADC                      260
+#define CLK_PPMUFILE                   261
+#define CLK_NFCON                      262
+#define CLK_USBDEVICE                  263
+#define CLK_USBHOST                    264
+#define CLK_SROMC                      265
+#define CLK_SDMMC2                     266
+#define CLK_SDMMC1                     267
+#define CLK_SDMMC0                     268
+#define CLK_PDMA1                      269
+#define CLK_PDMA0                      270
+#define CLK_SPDIF                      271
+#define CLK_PWM                                272
+#define CLK_PCM2                       273
+#define CLK_PCM1                       274
+#define CLK_I2S1                       275
+#define CLK_SPI2                       276
+#define CLK_SPI1                       277
+#define CLK_SPI0                       278
+#define CLK_I2CHDMI                    279
+#define CLK_I2C7                       280
+#define CLK_I2C6                       281
+#define CLK_I2C5                       282
+#define CLK_I2C4                       283
+#define CLK_I2C3                       284
+#define CLK_I2C2                       285
+#define CLK_I2C1                       286
+#define CLK_I2C0                       287
+#define CLK_UART3                      288
+#define CLK_UART2                      289
+#define CLK_UART1                      290
+#define CLK_UART0                      291
+
+/* Special clocks */
+#define CLK_SCLK_PXLAYSNC_CSIS1_FIMC   330
+#define CLK_SCLK_PXLAYSNC_CSIS0_FIMC   331
+#define CLK_SCLK_JPEG                  332
+#define CLK_SCLK_CSIS1                 333
+#define CLK_SCLK_CSIS0                 334
+#define CLK_SCLK_CAM1                  335
+#define CLK_SCLK_FIMC3_LCLK            336
+#define CLK_SCLK_FIMC2_LCLK            337
+#define CLK_SCLK_FIMC1_LCLK            338
+#define CLK_SCLK_FIMC0_LCLK            339
+#define CLK_SCLK_PIXEL                 340
+#define CLK_SCLK_HDMI                  341
+#define CLK_SCLK_MIXER                 342
+#define CLK_SCLK_MFC                   343
+#define CLK_SCLK_G3D                   344
+#define CLK_SCLK_MIPIDPHY4L            345
+#define CLK_SCLK_MIPI0                 346
+#define CLK_SCLK_MDNIE0                        347
+#define CLK_SCLK_FIMD0                 348
+#define CLK_SCLK_PCM0                  349
+#define CLK_SCLK_AUDIO0                        350
+#define CLK_SCLK_TSADC                 351
+#define CLK_SCLK_EBI                   352
+#define CLK_SCLK_MMC2                  353
+#define CLK_SCLK_MMC1                  354
+#define CLK_SCLK_MMC0                  355
+#define CLK_SCLK_I2S                   356
+#define CLK_SCLK_PCM2                  357
+#define CLK_SCLK_PCM1                  358
+#define CLK_SCLK_AUDIO2                        359
+#define CLK_SCLK_AUDIO1                        360
+#define CLK_SCLK_SPDIF                 361
+#define CLK_SCLK_SPI2                  362
+#define CLK_SCLK_SPI1                  363
+#define CLK_SCLK_SPI0                  364
+#define CLK_SCLK_UART3                 365
+#define CLK_SCLK_UART2                 366
+#define CLK_SCLK_UART1                 367
+#define CLK_SCLK_UART0                 368
+#define CLK_SCLK_HDMIPHY               369
+
+/*
+ * Total number of clocks of main CMU.
+ * NOTE: Must be equal to last clock ID increased by one.
+ */
+#define CLK_NR_CLKS                    370
+
+/*
+ * CMU DMC
+ */
+#define CLK_DMC_FOUT_MPLL              1
+#define CLK_DMC_FOUT_BPLL              2
+
+#define CLK_DMC_MOUT_MPLL              3
+#define CLK_DMC_MOUT_BPLL              4
+#define CLK_DMC_MOUT_DPHY              5
+#define CLK_DMC_MOUT_DMC_BUS           6
+
+#define CLK_DMC_DIV_DMC                        7
+#define CLK_DMC_DIV_DPHY               8
+#define CLK_DMC_DIV_DMC_PRE            9
+#define CLK_DMC_DIV_DMCP               10
+#define CLK_DMC_DIV_DMCD               11
+#define CLK_DMC_DIV_MPLL_PRE           12
+
+/*
+ * Total number of clocks of CMU_DMC.
+ * NOTE: Must be equal to highest clock ID increased by one.
+ */
+#define NR_CLKS_DMC                    13
+
+#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H */
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
new file mode 100644 (file)
index 0000000..8e4681b
--- /dev/null
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H
+#define _DT_BINDINGS_CLOCK_EXYNOS7_H
+
+/* TOPC */
+#define DOUT_ACLK_PERIS                        1
+#define DOUT_SCLK_BUS0_PLL             2
+#define DOUT_SCLK_BUS1_PLL             3
+#define DOUT_SCLK_CC_PLL               4
+#define DOUT_SCLK_MFC_PLL              5
+#define DOUT_ACLK_CCORE_133            6
+#define TOPC_NR_CLK                    7
+
+/* TOP0 */
+#define DOUT_ACLK_PERIC1               1
+#define DOUT_ACLK_PERIC0               2
+#define CLK_SCLK_UART0                 3
+#define CLK_SCLK_UART1                 4
+#define CLK_SCLK_UART2                 5
+#define CLK_SCLK_UART3                 6
+#define TOP0_NR_CLK                    7
+
+/* TOP1 */
+#define DOUT_ACLK_FSYS1_200            1
+#define DOUT_ACLK_FSYS0_200            2
+#define DOUT_SCLK_MMC2                 3
+#define DOUT_SCLK_MMC1                 4
+#define DOUT_SCLK_MMC0                 5
+#define CLK_SCLK_MMC2                  6
+#define CLK_SCLK_MMC1                  7
+#define CLK_SCLK_MMC0                  8
+#define TOP1_NR_CLK                    9
+
+/* CCORE */
+#define PCLK_RTC                       1
+#define CCORE_NR_CLK                   2
+
+/* PERIC0 */
+#define PCLK_UART0                     1
+#define SCLK_UART0                     2
+#define PCLK_HSI2C0                    3
+#define PCLK_HSI2C1                    4
+#define PCLK_HSI2C4                    5
+#define PCLK_HSI2C5                    6
+#define PCLK_HSI2C9                    7
+#define PCLK_HSI2C10                   8
+#define PCLK_HSI2C11                   9
+#define PCLK_PWM                       10
+#define SCLK_PWM                       11
+#define PCLK_ADCIF                     12
+#define PERIC0_NR_CLK                  13
+
+/* PERIC1 */
+#define PCLK_UART1                     1
+#define PCLK_UART2                     2
+#define PCLK_UART3                     3
+#define SCLK_UART1                     4
+#define SCLK_UART2                     5
+#define SCLK_UART3                     6
+#define PCLK_HSI2C2                    7
+#define PCLK_HSI2C3                    8
+#define PCLK_HSI2C6                    9
+#define PCLK_HSI2C7                    10
+#define PCLK_HSI2C8                    11
+#define PERIC1_NR_CLK                  12
+
+/* PERIS */
+#define PCLK_CHIPID                    1
+#define SCLK_CHIPID                    2
+#define PCLK_WDT                       3
+#define PCLK_TMU                       4
+#define SCLK_TMU                       5
+#define PERIS_NR_CLK                   6
+
+/* FSYS0 */
+#define ACLK_MMC2                      1
+#define FSYS0_NR_CLK                   2
+
+/* FSYS1 */
+#define ACLK_MMC1                      1
+#define ACLK_MMC0                      2
+#define FSYS1_NR_CLK                   3
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
diff --git a/include/dt-bindings/clock/marvell,mmp2.h b/include/dt-bindings/clock/marvell,mmp2.h
new file mode 100644 (file)
index 0000000..591f7fb
--- /dev/null
@@ -0,0 +1,74 @@
+#ifndef __DTS_MARVELL_MMP2_CLOCK_H
+#define __DTS_MARVELL_MMP2_CLOCK_H
+
+/* fixed clocks and plls */
+#define MMP2_CLK_CLK32                 1
+#define MMP2_CLK_VCTCXO                        2
+#define MMP2_CLK_PLL1                  3
+#define MMP2_CLK_PLL1_2                        8
+#define MMP2_CLK_PLL1_4                        9
+#define MMP2_CLK_PLL1_8                        10
+#define MMP2_CLK_PLL1_16               11
+#define MMP2_CLK_PLL1_3                        12
+#define MMP2_CLK_PLL1_6                        13
+#define MMP2_CLK_PLL1_12               14
+#define MMP2_CLK_PLL1_20               15
+#define MMP2_CLK_PLL2                  16
+#define MMP2_CLK_PLL2_2                        17
+#define MMP2_CLK_PLL2_4                        18
+#define MMP2_CLK_PLL2_8                        19
+#define MMP2_CLK_PLL2_16               20
+#define MMP2_CLK_PLL2_3                        21
+#define MMP2_CLK_PLL2_6                        22
+#define MMP2_CLK_PLL2_12               23
+#define MMP2_CLK_VCTCXO_2              24
+#define MMP2_CLK_VCTCXO_4              25
+#define MMP2_CLK_UART_PLL              26
+#define MMP2_CLK_USB_PLL               27
+
+/* apb periphrals */
+#define MMP2_CLK_TWSI0                 60
+#define MMP2_CLK_TWSI1                 61
+#define MMP2_CLK_TWSI2                 62
+#define MMP2_CLK_TWSI3                 63
+#define MMP2_CLK_TWSI4                 64
+#define MMP2_CLK_TWSI5                 65
+#define MMP2_CLK_GPIO                  66
+#define MMP2_CLK_KPC                   67
+#define MMP2_CLK_RTC                   68
+#define MMP2_CLK_PWM0                  69
+#define MMP2_CLK_PWM1                  70
+#define MMP2_CLK_PWM2                  71
+#define MMP2_CLK_PWM3                  72
+#define MMP2_CLK_UART0                 73
+#define MMP2_CLK_UART1                 74
+#define MMP2_CLK_UART2                 75
+#define MMP2_CLK_UART3                 76
+#define MMP2_CLK_SSP0                  77
+#define MMP2_CLK_SSP1                  78
+#define MMP2_CLK_SSP2                  79
+#define MMP2_CLK_SSP3                  80
+
+/* axi periphrals */
+#define MMP2_CLK_SDH0                  101
+#define MMP2_CLK_SDH1                  102
+#define MMP2_CLK_SDH2                  103
+#define MMP2_CLK_SDH3                  104
+#define MMP2_CLK_USB                   105
+#define MMP2_CLK_DISP0                 106
+#define MMP2_CLK_DISP0_MUX             107
+#define MMP2_CLK_DISP0_SPHY            108
+#define MMP2_CLK_DISP1                 109
+#define MMP2_CLK_DISP1_MUX             110
+#define MMP2_CLK_CCIC_ARBITER          111
+#define MMP2_CLK_CCIC0                 112
+#define MMP2_CLK_CCIC0_MIX             113
+#define MMP2_CLK_CCIC0_PHY             114
+#define MMP2_CLK_CCIC0_SPHY            115
+#define MMP2_CLK_CCIC1                 116
+#define MMP2_CLK_CCIC1_MIX             117
+#define MMP2_CLK_CCIC1_PHY             118
+#define MMP2_CLK_CCIC1_SPHY            119
+
+#define MMP2_NR_CLKS                   200
+#endif
diff --git a/include/dt-bindings/clock/marvell,pxa168.h b/include/dt-bindings/clock/marvell,pxa168.h
new file mode 100644 (file)
index 0000000..79630b9
--- /dev/null
@@ -0,0 +1,57 @@
+#ifndef __DTS_MARVELL_PXA168_CLOCK_H
+#define __DTS_MARVELL_PXA168_CLOCK_H
+
+/* fixed clocks and plls */
+#define PXA168_CLK_CLK32               1
+#define PXA168_CLK_VCTCXO              2
+#define PXA168_CLK_PLL1                        3
+#define PXA168_CLK_PLL1_2              8
+#define PXA168_CLK_PLL1_4              9
+#define PXA168_CLK_PLL1_8              10
+#define PXA168_CLK_PLL1_16             11
+#define PXA168_CLK_PLL1_6              12
+#define PXA168_CLK_PLL1_12             13
+#define PXA168_CLK_PLL1_24             14
+#define PXA168_CLK_PLL1_48             15
+#define PXA168_CLK_PLL1_96             16
+#define PXA168_CLK_PLL1_13             17
+#define PXA168_CLK_PLL1_13_1_5         18
+#define PXA168_CLK_PLL1_2_1_5          19
+#define PXA168_CLK_PLL1_3_16           20
+#define PXA168_CLK_UART_PLL            27
+
+/* apb periphrals */
+#define PXA168_CLK_TWSI0               60
+#define PXA168_CLK_TWSI1               61
+#define PXA168_CLK_TWSI2               62
+#define PXA168_CLK_TWSI3               63
+#define PXA168_CLK_GPIO                        64
+#define PXA168_CLK_KPC                 65
+#define PXA168_CLK_RTC                 66
+#define PXA168_CLK_PWM0                        67
+#define PXA168_CLK_PWM1                        68
+#define PXA168_CLK_PWM2                        69
+#define PXA168_CLK_PWM3                        70
+#define PXA168_CLK_UART0               71
+#define PXA168_CLK_UART1               72
+#define PXA168_CLK_UART2               73
+#define PXA168_CLK_SSP0                        74
+#define PXA168_CLK_SSP1                        75
+#define PXA168_CLK_SSP2                        76
+#define PXA168_CLK_SSP3                        77
+#define PXA168_CLK_SSP4                        78
+
+/* axi periphrals */
+#define PXA168_CLK_DFC                 100
+#define PXA168_CLK_SDH0                        101
+#define PXA168_CLK_SDH1                        102
+#define PXA168_CLK_SDH2                        103
+#define PXA168_CLK_USB                 104
+#define PXA168_CLK_SPH                 105
+#define PXA168_CLK_DISP0               106
+#define PXA168_CLK_CCIC0               107
+#define PXA168_CLK_CCIC0_PHY           108
+#define PXA168_CLK_CCIC0_SPHY          109
+
+#define PXA168_NR_CLKS                 200
+#endif
diff --git a/include/dt-bindings/clock/marvell,pxa910.h b/include/dt-bindings/clock/marvell,pxa910.h
new file mode 100644 (file)
index 0000000..719cffb
--- /dev/null
@@ -0,0 +1,54 @@
+#ifndef __DTS_MARVELL_PXA910_CLOCK_H
+#define __DTS_MARVELL_PXA910_CLOCK_H
+
+/* fixed clocks and plls */
+#define PXA910_CLK_CLK32               1
+#define PXA910_CLK_VCTCXO              2
+#define PXA910_CLK_PLL1                        3
+#define PXA910_CLK_PLL1_2              8
+#define PXA910_CLK_PLL1_4              9
+#define PXA910_CLK_PLL1_8              10
+#define PXA910_CLK_PLL1_16             11
+#define PXA910_CLK_PLL1_6              12
+#define PXA910_CLK_PLL1_12             13
+#define PXA910_CLK_PLL1_24             14
+#define PXA910_CLK_PLL1_48             15
+#define PXA910_CLK_PLL1_96             16
+#define PXA910_CLK_PLL1_13             17
+#define PXA910_CLK_PLL1_13_1_5         18
+#define PXA910_CLK_PLL1_2_1_5          19
+#define PXA910_CLK_PLL1_3_16           20
+#define PXA910_CLK_UART_PLL            27
+
+/* apb periphrals */
+#define PXA910_CLK_TWSI0               60
+#define PXA910_CLK_TWSI1               61
+#define PXA910_CLK_TWSI2               62
+#define PXA910_CLK_TWSI3               63
+#define PXA910_CLK_GPIO                        64
+#define PXA910_CLK_KPC                 65
+#define PXA910_CLK_RTC                 66
+#define PXA910_CLK_PWM0                        67
+#define PXA910_CLK_PWM1                        68
+#define PXA910_CLK_PWM2                        69
+#define PXA910_CLK_PWM3                        70
+#define PXA910_CLK_UART0               71
+#define PXA910_CLK_UART1               72
+#define PXA910_CLK_UART2               73
+#define PXA910_CLK_SSP0                        74
+#define PXA910_CLK_SSP1                        75
+
+/* axi periphrals */
+#define PXA910_CLK_DFC                 100
+#define PXA910_CLK_SDH0                        101
+#define PXA910_CLK_SDH1                        102
+#define PXA910_CLK_SDH2                        103
+#define PXA910_CLK_USB                 104
+#define PXA910_CLK_SPH                 105
+#define PXA910_CLK_DISP0               106
+#define PXA910_CLK_CCIC0               107
+#define PXA910_CLK_CCIC0_PHY           108
+#define PXA910_CLK_CCIC0_SPHY          109
+
+#define PXA910_NR_CLKS                 200
+#endif
index 100a08c47692c38c01726482ef26ec10b801278d..f60ce72a2b2c76c23da6fa52c7eb470d39195633 100644 (file)
 #define SCLK_HDMI_CEC          110
 #define SCLK_HEVC_CABAC                111
 #define SCLK_HEVC_CORE         112
+#define SCLK_I2S0_OUT          113
+#define SCLK_SDMMC_DRV         114
+#define SCLK_SDIO0_DRV         115
+#define SCLK_SDIO1_DRV         116
+#define SCLK_EMMC_DRV          117
+#define SCLK_SDMMC_SAMPLE      118
+#define SCLK_SDIO0_SAMPLE      119
+#define SCLK_SDIO1_SAMPLE      120
+#define SCLK_EMMC_SAMPLE       121
 
 #define DCLK_VOP0              190
 #define DCLK_VOP1              191
 #define PCLK_VIO2_H2P          361
 #define PCLK_CPU               362
 #define PCLK_PERI              363
+#define PCLK_DDRUPCTL0         364
+#define PCLK_PUBL0             365
+#define PCLK_DDRUPCTL1         366
+#define PCLK_PUBL1             367
 
 /* hclk gates */
 #define HCLK_GPS               448
index 2839c639f0920942d1e835dd464598432e22e974..d936409520f8db609994f7ddab629a99981883dc 100644 (file)
@@ -176,7 +176,7 @@ struct clk_ops {
                                        unsigned long *parent_rate);
        long            (*determine_rate)(struct clk_hw *hw, unsigned long rate,
                                        unsigned long *best_parent_rate,
-                                       struct clk **best_parent_clk);
+                                       struct clk_hw **best_parent_hw);
        int             (*set_parent)(struct clk_hw *hw, u8 index);
        u8              (*get_parent)(struct clk_hw *hw);
        int             (*set_rate)(struct clk_hw *hw, unsigned long rate,
@@ -544,16 +544,14 @@ u8 __clk_get_num_parents(struct clk *clk);
 struct clk *__clk_get_parent(struct clk *clk);
 struct clk *clk_get_parent_by_index(struct clk *clk, u8 index);
 unsigned int __clk_get_enable_count(struct clk *clk);
-unsigned int __clk_get_prepare_count(struct clk *clk);
 unsigned long __clk_get_rate(struct clk *clk);
-unsigned long __clk_get_accuracy(struct clk *clk);
 unsigned long __clk_get_flags(struct clk *clk);
 bool __clk_is_prepared(struct clk *clk);
 bool __clk_is_enabled(struct clk *clk);
 struct clk *__clk_lookup(const char *name);
 long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
                              unsigned long *best_parent_rate,
-                             struct clk **best_parent_p);
+                             struct clk_hw **best_parent_p);
 
 /*
  * FIXME clock api without lock protection
@@ -652,7 +650,7 @@ static inline void clk_writel(u32 val, u32 __iomem *reg)
 #endif /* platform dependent I/O accessors */
 
 #ifdef CONFIG_DEBUG_FS
-struct dentry *clk_debugfs_add_file(struct clk *clk, char *name, umode_t mode,
+struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode,
                                void *data, const struct file_operations *fops);
 #endif
 
index 74e5341463c91d06c1d5578d93f722358e340929..55ef529a0dbf905995781bd051bf926396b837c5 100644 (file)
@@ -264,7 +264,7 @@ int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
 long omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
                                       unsigned long rate,
                                       unsigned long *best_parent_rate,
-                                      struct clk **best_parent_clk);
+                                      struct clk_hw **best_parent_clk);
 unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
                                         unsigned long parent_rate);
 long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
@@ -273,7 +273,7 @@ long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
 long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
                                        unsigned long rate,
                                        unsigned long *best_parent_rate,
-                                       struct clk **best_parent_clk);
+                                       struct clk_hw **best_parent_clk);
 u8 omap2_init_dpll_parent(struct clk_hw *hw);
 unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
 long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,