drm/amdgpu: use gpu virtual address for interrupt packet write space for vangogh

The interrupts are not stable while uses guest physical address (GPA)
for interrupt packet write space even on direct loading case.

v2: make condition more readable

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index ce4a974ab77716d3bc1a31f8a5ccf0c534bbfbcf..53ea83c08e8e3b3b93a540799c7da028e1baea99 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -661,8 +661,11 @@ static int navi10_ih_sw_init(void *handle)
        /* use gpu virtual address for ih ring
         * until ih_checken is programmed to allow
         * use bus address for ih ring by psp bl */
-       use_bus_addr =
-               (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true;
+       if ((adev->flags & AMD_IS_APU) ||
+           (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
+               use_bus_addr = false;
+       else
+               use_bus_addr = true;
        r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr);
        if (r)
                return r;