};
soc: soc {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0 0xffffffff>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0 0 0 0 0 0xffffffff>;
compatible = "simple-bus";
gcc: clock-controller@100000 {
compatible = "qcom,gcc-sdm845";
- reg = <0x100000 0x1f0000>;
+ reg = <0 0x00100000 0 0x1f0000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
qfprom@784000 {
compatible = "qcom,qfprom";
- reg = <0x784000 0x8ff>;
+ reg = <0 0x00784000 0 0x8ff>;
#address-cells = <1>;
#size-cells = <1>;
rng: rng@793000 {
compatible = "qcom,prng-ee";
- reg = <0x00793000 0x1000>;
+ reg = <0 0x00793000 0 0x1000>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "core";
};
qupv3_id_0: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
- reg = <0x8c0000 0x6000>;
+ reg = <0 0x008c0000 0 0x6000>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
ranges;
status = "disabled";
i2c0: i2c@880000 {
compatible = "qcom,geni-i2c";
- reg = <0x880000 0x4000>;
+ reg = <0 0x00880000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default";
spi0: spi@880000 {
compatible = "qcom,geni-spi";
- reg = <0x880000 0x4000>;
+ reg = <0 0x00880000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default";
uart0: serial@880000 {
compatible = "qcom,geni-uart";
- reg = <0x880000 0x4000>;
+ reg = <0 0x00880000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default";
i2c1: i2c@884000 {
compatible = "qcom,geni-i2c";
- reg = <0x884000 0x4000>;
+ reg = <0 0x00884000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
pinctrl-names = "default";
spi1: spi@884000 {
compatible = "qcom,geni-spi";
- reg = <0x884000 0x4000>;
+ reg = <0 0x00884000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
pinctrl-names = "default";
uart1: serial@884000 {
compatible = "qcom,geni-uart";
- reg = <0x884000 0x4000>;
+ reg = <0 0x00884000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
pinctrl-names = "default";
i2c2: i2c@888000 {
compatible = "qcom,geni-i2c";
- reg = <0x888000 0x4000>;
+ reg = <0 0x00888000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
pinctrl-names = "default";
spi2: spi@888000 {
compatible = "qcom,geni-spi";
- reg = <0x888000 0x4000>;
+ reg = <0 0x00888000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
pinctrl-names = "default";
uart2: serial@888000 {
compatible = "qcom,geni-uart";
- reg = <0x888000 0x4000>;
+ reg = <0 0x00888000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
pinctrl-names = "default";
i2c3: i2c@88c000 {
compatible = "qcom,geni-i2c";
- reg = <0x88c000 0x4000>;
+ reg = <0 0x0088c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
pinctrl-names = "default";
spi3: spi@88c000 {
compatible = "qcom,geni-spi";
- reg = <0x88c000 0x4000>;
+ reg = <0 0x0088c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
pinctrl-names = "default";
uart3: serial@88c000 {
compatible = "qcom,geni-uart";
- reg = <0x88c000 0x4000>;
+ reg = <0 0x0088c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
pinctrl-names = "default";
i2c4: i2c@890000 {
compatible = "qcom,geni-i2c";
- reg = <0x890000 0x4000>;
+ reg = <0 0x00890000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
pinctrl-names = "default";
spi4: spi@890000 {
compatible = "qcom,geni-spi";
- reg = <0x890000 0x4000>;
+ reg = <0 0x00890000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
pinctrl-names = "default";
uart4: serial@890000 {
compatible = "qcom,geni-uart";
- reg = <0x890000 0x4000>;
+ reg = <0 0x00890000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
pinctrl-names = "default";
i2c5: i2c@894000 {
compatible = "qcom,geni-i2c";
- reg = <0x894000 0x4000>;
+ reg = <0 0x00894000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
pinctrl-names = "default";
spi5: spi@894000 {
compatible = "qcom,geni-spi";
- reg = <0x894000 0x4000>;
+ reg = <0 0x00894000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
pinctrl-names = "default";
uart5: serial@894000 {
compatible = "qcom,geni-uart";
- reg = <0x894000 0x4000>;
+ reg = <0 0x00894000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
pinctrl-names = "default";
i2c6: i2c@898000 {
compatible = "qcom,geni-i2c";
- reg = <0x898000 0x4000>;
+ reg = <0 0x00898000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
pinctrl-names = "default";
spi6: spi@898000 {
compatible = "qcom,geni-spi";
- reg = <0x898000 0x4000>;
+ reg = <0 0x00898000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
pinctrl-names = "default";
uart6: serial@898000 {
compatible = "qcom,geni-uart";
- reg = <0x898000 0x4000>;
+ reg = <0 0x00898000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
pinctrl-names = "default";
i2c7: i2c@89c000 {
compatible = "qcom,geni-i2c";
- reg = <0x89c000 0x4000>;
+ reg = <0 0x0089c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
pinctrl-names = "default";
spi7: spi@89c000 {
compatible = "qcom,geni-spi";
- reg = <0x89c000 0x4000>;
+ reg = <0 0x0089c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
pinctrl-names = "default";
uart7: serial@89c000 {
compatible = "qcom,geni-uart";
- reg = <0x89c000 0x4000>;
+ reg = <0 0x0089c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
pinctrl-names = "default";
qupv3_id_1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
- reg = <0xac0000 0x6000>;
+ reg = <0 0x00ac0000 0 0x6000>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
ranges;
status = "disabled";
i2c8: i2c@a80000 {
compatible = "qcom,geni-i2c";
- reg = <0xa80000 0x4000>;
+ reg = <0 0x00a80000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
pinctrl-names = "default";
spi8: spi@a80000 {
compatible = "qcom,geni-spi";
- reg = <0xa80000 0x4000>;
+ reg = <0 0x00a80000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
pinctrl-names = "default";
uart8: serial@a80000 {
compatible = "qcom,geni-uart";
- reg = <0xa80000 0x4000>;
+ reg = <0 0x00a80000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
pinctrl-names = "default";
i2c9: i2c@a84000 {
compatible = "qcom,geni-i2c";
- reg = <0xa84000 0x4000>;
+ reg = <0 0x00a84000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
pinctrl-names = "default";
spi9: spi@a84000 {
compatible = "qcom,geni-spi";
- reg = <0xa84000 0x4000>;
+ reg = <0 0x00a84000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
pinctrl-names = "default";
uart9: serial@a84000 {
compatible = "qcom,geni-debug-uart";
- reg = <0xa84000 0x4000>;
+ reg = <0 0x00a84000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
pinctrl-names = "default";
i2c10: i2c@a88000 {
compatible = "qcom,geni-i2c";
- reg = <0xa88000 0x4000>;
+ reg = <0 0x00a88000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
pinctrl-names = "default";
spi10: spi@a88000 {
compatible = "qcom,geni-spi";
- reg = <0xa88000 0x4000>;
+ reg = <0 0x00a88000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
pinctrl-names = "default";
uart10: serial@a88000 {
compatible = "qcom,geni-uart";
- reg = <0xa88000 0x4000>;
+ reg = <0 0x00a88000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
pinctrl-names = "default";
i2c11: i2c@a8c000 {
compatible = "qcom,geni-i2c";
- reg = <0xa8c000 0x4000>;
+ reg = <0 0x00a8c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
pinctrl-names = "default";
spi11: spi@a8c000 {
compatible = "qcom,geni-spi";
- reg = <0xa8c000 0x4000>;
+ reg = <0 0x00a8c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
pinctrl-names = "default";
uart11: serial@a8c000 {
compatible = "qcom,geni-uart";
- reg = <0xa8c000 0x4000>;
+ reg = <0 0x00a8c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
pinctrl-names = "default";
i2c12: i2c@a90000 {
compatible = "qcom,geni-i2c";
- reg = <0xa90000 0x4000>;
+ reg = <0 0x00a90000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
pinctrl-names = "default";
spi12: spi@a90000 {
compatible = "qcom,geni-spi";
- reg = <0xa90000 0x4000>;
+ reg = <0 0x00a90000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
pinctrl-names = "default";
uart12: serial@a90000 {
compatible = "qcom,geni-uart";
- reg = <0xa90000 0x4000>;
+ reg = <0 0x00a90000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
pinctrl-names = "default";
i2c13: i2c@a94000 {
compatible = "qcom,geni-i2c";
- reg = <0xa94000 0x4000>;
+ reg = <0 0x00a94000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
pinctrl-names = "default";
spi13: spi@a94000 {
compatible = "qcom,geni-spi";
- reg = <0xa94000 0x4000>;
+ reg = <0 0x00a94000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
pinctrl-names = "default";
uart13: serial@a94000 {
compatible = "qcom,geni-uart";
- reg = <0xa94000 0x4000>;
+ reg = <0 0x00a94000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
pinctrl-names = "default";
i2c14: i2c@a98000 {
compatible = "qcom,geni-i2c";
- reg = <0xa98000 0x4000>;
+ reg = <0 0x00a98000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
pinctrl-names = "default";
spi14: spi@a98000 {
compatible = "qcom,geni-spi";
- reg = <0xa98000 0x4000>;
+ reg = <0 0x00a98000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
pinctrl-names = "default";
uart14: serial@a98000 {
compatible = "qcom,geni-uart";
- reg = <0xa98000 0x4000>;
+ reg = <0 0x00a98000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
pinctrl-names = "default";
i2c15: i2c@a9c000 {
compatible = "qcom,geni-i2c";
- reg = <0xa9c000 0x4000>;
+ reg = <0 0x00a9c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
pinctrl-names = "default";
spi15: spi@a9c000 {
compatible = "qcom,geni-spi";
- reg = <0xa9c000 0x4000>;
+ reg = <0 0x00a9c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
pinctrl-names = "default";
uart15: serial@a9c000 {
compatible = "qcom,geni-uart";
- reg = <0xa9c000 0x4000>;
+ reg = <0 0x00a9c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
pinctrl-names = "default";
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
- reg = <0x1d84000 0x2500>;
+ reg = <0 0x01d84000 0 0x2500>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufs_mem_phy_lanes>;
phy-names = "ufsphy";
ufs_mem_phy: phy@1d87000 {
compatible = "qcom,sdm845-qmp-ufs-phy";
- reg = <0x1d87000 0x18c>;
- #address-cells = <1>;
- #size-cells = <1>;
+ reg = <0 0x01d87000 0 0x18c>;
+ #address-cells = <2>;
+ #size-cells = <2>;
ranges;
clock-names = "ref",
"ref_aux";
status = "disabled";
ufs_mem_phy_lanes: lanes@1d87400 {
- reg = <0x1d87400 0x108>,
- <0x1d87600 0x1e0>,
- <0x1d87c00 0x1dc>,
- <0x1d87800 0x108>,
- <0x1d87a00 0x1e0>;
+ reg = <0 0x01d87400 0 0x108>,
+ <0 0x01d87600 0 0x1e0>,
+ <0 0x01d87c00 0 0x1dc>,
+ <0 0x01d87800 0 0x108>,
+ <0 0x01d87a00 0 0x1e0>;
#phy-cells = <0>;
};
};
tcsr_mutex_regs: syscon@1f40000 {
compatible = "syscon";
- reg = <0x1f40000 0x40000>;
+ reg = <0 0x01f40000 0 0x40000>;
};
tlmm: pinctrl@3400000 {
compatible = "qcom,sdm845-pinctrl";
- reg = <0x03400000 0xc00000>;
+ reg = <0 0x03400000 0 0xc00000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpucc: clock-controller@5090000 {
compatible = "qcom,sdm845-gpucc";
- reg = <0x05090000 0x9000>;
+ reg = <0 0x05090000 0 0x9000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
sdhc_2: sdhci@8804000 {
compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
- reg = <0x8804000 0x1000>;
+ reg = <0 0x08804000 0 0x1000>;
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
qspi: spi@88df000 {
compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
- reg = <0x88df000 0x600>;
+ reg = <0 0x088df000 0 0x600>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
usb_1_hsphy: phy@88e2000 {
compatible = "qcom,sdm845-qusb2-phy";
- reg = <0x88e2000 0x400>;
+ reg = <0 0x088e2000 0 0x400>;
status = "disabled";
#phy-cells = <0>;
usb_2_hsphy: phy@88e3000 {
compatible = "qcom,sdm845-qusb2-phy";
- reg = <0x88e3000 0x400>;
+ reg = <0 0x088e3000 0 0x400>;
status = "disabled";
#phy-cells = <0>;
usb_1_qmpphy: phy@88e9000 {
compatible = "qcom,sdm845-qmp-usb3-phy";
- reg = <0x88e9000 0x18c>,
- <0x88e8000 0x10>;
+ reg = <0 0x088e9000 0 0x18c>,
+ <0 0x088e8000 0 0x10>;
reg-names = "reg-base", "dp_com";
status = "disabled";
#clock-cells = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
ranges;
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
reset-names = "phy", "common";
usb_1_ssphy: lanes@88e9200 {
- reg = <0x88e9200 0x128>,
- <0x88e9400 0x200>,
- <0x88e9c00 0x218>,
- <0x88e9600 0x128>,
- <0x88e9800 0x200>,
- <0x88e9a00 0x100>;
+ reg = <0 0x088e9200 0 0x128>,
+ <0 0x088e9400 0 0x200>,
+ <0 0x088e9c00 0 0x218>,
+ <0 0x088e9600 0 0x128>,
+ <0 0x088e9800 0 0x200>,
+ <0 0x088e9a00 0 0x100>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "pipe0";
usb_2_qmpphy: phy@88eb000 {
compatible = "qcom,sdm845-qmp-usb3-uni-phy";
- reg = <0x88eb000 0x18c>;
+ reg = <0 0x088eb000 0 0x18c>;
status = "disabled";
#clock-cells = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
ranges;
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
reset-names = "phy", "common";
usb_2_ssphy: lane@88eb200 {
- reg = <0x88eb200 0x128>,
- <0x88eb400 0x1fc>,
- <0x88eb800 0x218>,
- <0x88eb600 0x70>;
+ reg = <0 0x088eb200 0 0x128>,
+ <0 0x088eb400 0 0x1fc>,
+ <0 0x088eb800 0 0x218>,
+ <0 0x088eb600 0 0x70>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
clock-names = "pipe0";
usb_1: usb@a6f8800 {
compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
- reg = <0xa6f8800 0x400>;
+ reg = <0 0x0a6f8800 0 0x400>;
status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
ranges;
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
usb_1_dwc3: dwc3@a600000 {
compatible = "snps,dwc3";
- reg = <0xa600000 0xcd00>;
+ reg = <0 0x0a600000 0 0xcd00>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
usb_2: usb@a8f8800 {
compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
- reg = <0xa8f8800 0x400>;
+ reg = <0 0x0a8f8800 0 0x400>;
status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
ranges;
clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
usb_2_dwc3: dwc3@a800000 {
compatible = "snps,dwc3";
- reg = <0xa800000 0xcd00>;
+ reg = <0 0x0a800000 0 0xcd00>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
videocc: clock-controller@ab00000 {
compatible = "qcom,sdm845-videocc";
- reg = <0x0ab00000 0x10000>;
+ reg = <0 0x0ab00000 0 0x10000>;
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
mdss: mdss@ae00000 {
compatible = "qcom,sdm845-mdss";
- reg = <0x0ae00000 0x1000>;
+ reg = <0 0x0ae00000 0 0x1000>;
reg-names = "mdss";
power-domains = <&dispcc MDSS_GDSC>;
status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
ranges;
mdss_mdp: mdp@ae01000 {
compatible = "qcom,sdm845-dpu";
- reg = <0x0ae01000 0x8f000>,
- <0x0aeb0000 0x2008>;
+ reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb0000 0 0x2008>;
reg-names = "mdp", "vbif";
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
dsi0: dsi@ae94000 {
compatible = "qcom,mdss-dsi-ctrl";
- reg = <0xae94000 0x400>;
+ reg = <0 0x0ae94000 0 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
dsi0_phy: dsi-phy@ae94400 {
compatible = "qcom,dsi-phy-10nm";
- reg = <0xae94400 0x200>,
- <0xae94600 0x280>,
- <0xae94a00 0x1e0>;
+ reg = <0 0x0ae94400 0 0x200>,
+ <0 0x0ae94600 0 0x280>,
+ <0 0x0ae94a00 0 0x1e0>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
dsi1: dsi@ae96000 {
compatible = "qcom,mdss-dsi-ctrl";
- reg = <0xae96000 0x400>;
+ reg = <0 0x0ae96000 0 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
dsi1_phy: dsi-phy@ae96400 {
compatible = "qcom,dsi-phy-10nm";
- reg = <0xae96400 0x200>,
- <0xae96600 0x280>,
- <0xae96a00 0x10e>;
+ reg = <0 0x0ae96400 0 0x200>,
+ <0 0x0ae96600 0 0x280>,
+ <0 0x0ae96a00 0 0x10e>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
dispcc: clock-controller@af00000 {
compatible = "qcom,sdm845-dispcc";
- reg = <0xaf00000 0x10000>;
+ reg = <0 0x0af00000 0 0x10000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
pdc_reset: reset-controller@b2e0000 {
compatible = "qcom,sdm845-pdc-global";
- reg = <0x0b2e0000 0x20000>;
+ reg = <0 0x0b2e0000 0 0x20000>;
#reset-cells = <1>;
};
tsens0: thermal-sensor@c263000 {
compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
- reg = <0xc263000 0x1ff>, /* TM */
- <0xc222000 0x1ff>; /* SROT */
+ reg = <0 0x0c263000 0 0x1ff>, /* TM */
+ <0 0x0c222000 0 0x1ff>; /* SROT */
#qcom,sensors = <13>;
#thermal-sensor-cells = <1>;
};
tsens1: thermal-sensor@c265000 {
compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
- reg = <0xc265000 0x1ff>, /* TM */
- <0xc223000 0x1ff>; /* SROT */
+ reg = <0 0x0c265000 0 0x1ff>, /* TM */
+ <0 0x0c223000 0 0x1ff>; /* SROT */
#qcom,sensors = <8>;
#thermal-sensor-cells = <1>;
};
aoss_reset: reset-controller@c2a0000 {
compatible = "qcom,sdm845-aoss-cc";
- reg = <0xc2a0000 0x31000>;
+ reg = <0 0x0c2a0000 0 0x31000>;
#reset-cells = <1>;
};
spmi_bus: spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
- reg = <0xc440000 0x1100>,
- <0xc600000 0x2000000>,
- <0xe600000 0x100000>,
- <0xe700000 0xa0000>,
- <0xc40a000 0x26000>;
+ reg = <0 0x0c440000 0 0x1100>,
+ <0 0x0c600000 0 0x2000000>,
+ <0 0x0e600000 0 0x100000>,
+ <0 0x0e700000 0 0xa0000>,
+ <0 0x0c40a000 0 0x26000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
apps_smmu: iommu@15000000 {
compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
- reg = <0x15000000 0x80000>;
+ reg = <0 0x15000000 0 0x80000>;
#iommu-cells = <2>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
apss_shared: mailbox@17990000 {
compatible = "qcom,sdm845-apss-shared";
- reg = <0x17990000 0x1000>;
+ reg = <0 0x17990000 0 0x1000>;
#mbox-cells = <1>;
};
apps_rsc: rsc@179c0000 {
label = "apps_rsc";
compatible = "qcom,rpmh-rsc";
- reg = <0x179c0000 0x10000>,
- <0x179d0000 0x10000>,
- <0x179e0000 0x10000>;
+ reg = <0 0x179c0000 0 0x10000>,
+ <0 0x179d0000 0 0x10000>,
+ <0 0x179e0000 0 0x10000>;
reg-names = "drv-0", "drv-1", "drv-2";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
ranges;
#interrupt-cells = <3>;
interrupt-controller;
- reg = <0x17a00000 0x10000>, /* GICD */
- <0x17a60000 0x100000>; /* GICR * 8 */
+ reg = <0 0x17a00000 0 0x10000>, /* GICD */
+ <0 0x17a60000 0 0x100000>; /* GICR * 8 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
gic-its@17a40000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
- reg = <0x17a40000 0x20000>;
+ reg = <0 0x17a40000 0 0x20000>;
status = "disabled";
};
};
timer@17c90000 {
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
ranges;
compatible = "arm,armv7-timer-mem";
- reg = <0x17c90000 0x1000>;
+ reg = <0 0x17c90000 0 0x1000>;
frame@17ca0000 {
frame-number = <0>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x17ca0000 0x1000>,
- <0x17cb0000 0x1000>;
+ reg = <0 0x17ca0000 0 0x1000>,
+ <0 0x17cb0000 0 0x1000>;
};
frame@17cc0000 {
frame-number = <1>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x17cc0000 0x1000>;
+ reg = <0 0x17cc0000 0 0x1000>;
status = "disabled";
};
frame@17cd0000 {
frame-number = <2>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x17cd0000 0x1000>;
+ reg = <0 0x17cd0000 0 0x1000>;
status = "disabled";
};
frame@17ce0000 {
frame-number = <3>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x17ce0000 0x1000>;
+ reg = <0 0x17ce0000 0 0x1000>;
status = "disabled";
};
frame@17cf0000 {
frame-number = <4>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x17cf0000 0x1000>;
+ reg = <0 0x17cf0000 0 0x1000>;
status = "disabled";
};
frame@17d00000 {
frame-number = <5>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x17d00000 0x1000>;
+ reg = <0 0x17d00000 0 0x1000>;
status = "disabled";
};
frame@17d10000 {
frame-number = <6>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x17d10000 0x1000>;
+ reg = <0 0x17d10000 0 0x1000>;
status = "disabled";
};
};
cpufreq_hw: cpufreq@17d43000 {
compatible = "qcom,cpufreq-hw";
- reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;
+ reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
reg-names = "freq-domain0", "freq-domain1";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
wifi: wifi@18800000 {
compatible = "qcom,wcn3990-wifi";
status = "disabled";
- reg = <0x18800000 0x800000>;
+ reg = <0 0x18800000 0 0x800000>;
reg-names = "membase";
memory-region = <&wlan_msa_mem>;
interrupts =
projects / linux-block.git / commitdiff