Merge branch 'next/topic-cpuid-rev' into next/topic-add-exynos4212

diff --combined arch/arm/mach-exynos4/cpu.c
index 746d6fc6d397dc23dffd93ea3764c80fd0db3bb0,dbc358d75547cc0ba1d2527bd2bf7f81f4c13bf8..0d281bbe345a2bc2b9c44d3fcee91259089d1b76
--- 1/arch/arm/mach-exynos4/cpu.c
--- 2/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@@ -24,13 -24,12 +24,13 @@@
  #include <plat/exynos4.h>
  #include <plat/adc-core.h>
  #include <plat/sdhci.h>
 -#include <plat/devs.h>
  #include <plat/fb-core.h>
  #include <plat/fimc-core.h>
  #include <plat/iic-core.h>
 +#include <plat/reset.h>
  
  #include <mach/regs-irq.h>
 +#include <mach/regs-pmu.h>
  
  extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
                         unsigned int irq_start);
@@@ -43,11 -42,6 +43,6 @@@ static struct map_desc exynos4_iodesc[
                .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
                .length         = SZ_4K,
                .type           = MT_DEVICE,
-       }, {
-               .virtual        = (unsigned long)S5P_VA_SYSRAM,
-               .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM),
-               .length         = SZ_4K,
-               .type           = MT_DEVICE,
        }, {
                .virtual        = (unsigned long)S5P_VA_CMU,
                .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
@@@ -121,6 -115,24 +116,24 @@@
        },
  };
  
+ static struct map_desc exynos4_iodesc0[] __initdata = {
+       {
+               .virtual        = (unsigned long)S5P_VA_SYSRAM,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       },
+ };
+ 
+ static struct map_desc exynos4_iodesc1[] __initdata = {
+       {
+               .virtual        = (unsigned long)S5P_VA_SYSRAM,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       },
+ };
+ 
  static void exynos4_idle(void)
  {
        if (!need_resched())
@@@ -129,11 -141,6 +142,11 @@@
        local_irq_enable();
  }
  
 +static void exynos4_sw_reset(void)
 +{
 +      __raw_writel(0x1, S5P_SWRESET);
 +}
 +
  /*
   * exynos4_map_io
   *
@@@ -143,6 -150,11 +156,11 @@@ void __init exynos4_map_io(void
  {
        iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
  
+       if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
+               iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
+       else
+               iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
+ 
        /* initialize device information early */
        exynos4_default_sdhci0();
        exynos4_default_sdhci1();
@@@ -247,8 -259,5 +265,8 @@@ int __init exynos4_init(void
        /* set idle function */
        pm_idle = exynos4_idle;
  
 +      /* set sw_reset function */
 +      s5p_reset_hook = exynos4_sw_reset;
 +
        return sysdev_register(&exynos4_sysdev);
  }

diff --combined arch/arm/mach-exynos4/platsmp.c
index df6ef1b2f98b8b65ef7f881bc788afba81dfd0fa,96cc6513b128de38a7b7c66e6b0c9036f9ec5993..a3346e36d0aeb84061ff3a41f596e51dfb93bf14
--- 1/arch/arm/mach-exynos4/platsmp.c
--- 2/arch/arm/mach-exynos4/platsmp.c
+++ b/arch/arm/mach-exynos4/platsmp.c
@@@ -30,9 -30,12 +30,12 @@@
  #include <mach/regs-clock.h>
  #include <mach/regs-pmu.h>
  
+ #include <plat/cpu.h>
+ 
  extern void exynos4_secondary_startup(void);
  
- #define CPU1_BOOT_REG S5P_VA_SYSRAM
+ #define CPU1_BOOT_REG         (samsung_rev() == EXYNOS4210_REV_1_1 ? \
+                               S5P_INFORM5 : S5P_VA_SYSRAM)
  
  /*
   * control for which core is the next to come out of the secondary
@@@ -106,8 -109,6 +109,8 @@@ void __cpuinit platform_secondary_init(
         */
        spin_lock(&boot_lock);
        spin_unlock(&boot_lock);
 +
 +      set_cpu_online(cpu, true);
  }
  
  int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
@@@ -218,5 -219,6 +221,6 @@@ void __init platform_smp_prepare_cpus(u
         * until it receives a soft interrupt, and then the
         * secondary CPU branches to this address.
         */
-       __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), S5P_VA_SYSRAM);
+       __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
+                       CPU1_BOOT_REG);
  }

diff --combined arch/arm/mach-s5p64x0/irq-eint.c
index fe7380f5c3cd858613753230a9ef0f0e973e76bf,94104c4995972d9b396f860c566a07fa61a98b11..494e1a8f6f6d68a0613c63a6e5618ad162458d50
--- 1/arch/arm/mach-s5p64x0/irq-eint.c
--- 2/arch/arm/mach-s5p64x0/irq-eint.c
+++ b/arch/arm/mach-s5p64x0/irq-eint.c
@@@ -17,6 -17,7 +17,7 @@@
  #include <linux/irq.h>
  #include <linux/io.h>
  
+ #include <plat/cpu.h>
  #include <plat/regs-irqtype.h>
  #include <plat/gpio-cfg.h>
  
@@@ -67,7 -68,7 +68,7 @@@ static int s5p64x0_irq_eint_set_type(st
        __raw_writel(ctrl, S5P64X0_EINT0CON0);
  
        /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
-       if (0x50000 == (__raw_readl(S5P64X0_SYS_ID) & 0xFF000))
+       if (soc_is_s5p6450())
                s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
        else
                s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
@@@ -129,7 -130,7 +130,7 @@@ static int s5p64x0_alloc_gc(void
        }
  
        ct = gc->chip_types;
 -      ct->chip.irq_ack = irq_gc_ack;
 +      ct->chip.irq_ack = irq_gc_ack_set_bit;
        ct->chip.irq_mask = irq_gc_mask_set_bit;
        ct->chip.irq_unmask = irq_gc_mask_clr_bit;
        ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;