arm64: dts: ti: k3-j7200-evm*: Add bootph-* properties

Adds bootph-* properties to the leaf nodes to enable bootloaders to
utilise them.

Following adds bootph-* to:
- pmic regulator for enabling AVS Support
- main_uart0, mcu_uart0(DM), wkup_uart0(TIFS) for Traces
- mmc0, mmc1, usb0, ospi0, hbmc for enabling various bootmodes.

Reviewed-by: Aniket Limaye <a-limaye@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-12-2af90e3a4fe7@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index 6593c5da82c06463c2d7cbbe01d6fa481be1aa1a..d03690b8d65230d22b3630770a6bc819409837c1 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -129,6 +129,7 @@
                        J721E_WKUP_IOPAD(0x8c, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */
                        J721E_WKUP_IOPAD(0x88, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */
                >;
+               bootph-all;
        };
 
        wkup_uart0_pins_default: wkup-uart0-default-pins {
@@ -136,6 +137,7 @@
                        J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */
                        J721E_WKUP_IOPAD(0x4c, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */
                >;
+               bootph-all;
        };
 
        mcu_cpsw_pins_default: mcu-cpsw-default-pins {
@@ -204,6 +206,7 @@
                        J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */
                        J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */
                >;
+               bootph-all;
        };
 
        main_uart1_pins_default: main-uart1-default-pins {
@@ -238,6 +241,7 @@
                        J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
                        J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
                >;
+               bootph-all;
        };
 
        vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
@@ -259,6 +263,7 @@
                pinctrl-single,pins = <
                        J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
                >;
+               bootph-all;
        };
 };
 
@@ -267,12 +272,14 @@
        status = "reserved";
        pinctrl-names = "default";
        pinctrl-0 = <&wkup_uart0_pins_default>;
+       bootph-all;
 };
 
 &mcu_uart0 {
        status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&mcu_uart0_pins_default>;
+       bootph-all;
 };
 
 &main_uart0 {
@@ -281,6 +288,7 @@
        power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
        pinctrl-names = "default";
        pinctrl-0 = <&main_uart0_pins_default>;
+       bootph-all;
 };
 
 &main_uart1 {
@@ -379,6 +387,7 @@
        /* eMMC */
        status = "okay";
        non-removable;
+       bootph-all;
        ti,driver-strength-ohm = <50>;
        disable-wp;
 };
@@ -390,6 +399,7 @@
        pinctrl-names = "default";
        vmmc-supply = <&vdd_mmc1>;
        vqmmc-supply = <&vdd_sd_dv>;
+       bootph-all;
        ti,driver-strength-ohm = <50>;
        disable-wp;
 };
@@ -401,11 +411,13 @@
 
 &usb_serdes_mux {
        idle-states = <1>; /* USB0 to SERDES lane 3 */
+       bootph-all;
 };
 
 &usbss0 {
        pinctrl-names = "default";
        pinctrl-0 = <&main_usbss0_pins_default>;
+       bootph-all;
        ti,vbus-divider;
        ti,usb2-only;
 };
@@ -413,6 +425,7 @@
 &usb0 {
        dr_mode = "otg";
        maximum-speed = "high-speed";
+       bootph-all;
 };
 
 &tscadc0 {

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
index e78b4622a7d1ff320259b17850e8f1735508f7dd..291ab9bb414d7883f102101035b19fd324767306 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
@@ -121,6 +121,7 @@
                        J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
                        J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
                >;
+               bootph-all;
        };
 
        mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
@@ -137,6 +138,7 @@
                        J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0)  /* MCU_OSPI0_D7 */
                        J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0)  /* MCU_OSPI0_DQS */
                >;
+               bootph-all;
        };
 };
 
@@ -146,6 +148,7 @@
                        J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */
                        J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
                >;
+               bootph-all;
        };
 };
 
@@ -186,6 +189,7 @@
        flash@0,0 {
                compatible = "cypress,hyperflash", "cfi-flash";
                reg = <0x00 0x00 0x4000000>;
+               bootph-all;
 
                partitions {
                        compatible = "fixed-partitions";
@@ -347,6 +351,7 @@
                                regulator-max-microvolt = <1800000>;
                                regulator-boot-on;
                                regulator-always-on;
+                               bootph-all;
                        };
 
                        bucka2: buck2 {
@@ -520,6 +525,7 @@
                        partition@3fc0000 {
                                label = "ospi.phypattern";
                                reg = <0x3fc0000 0x40000>;
+                               bootph-all;
                        };
                };
        };