arm64: dts: ti: k3-j721e: correct cache-sets info

[ Upstream commit 7a0df1f969c14939f60a7f9a6af72adcc314675f ]

A72 Cluster has 48KB Icache, 32KB Dcache and 1MB L2 Cache
 - ICache is 3-way set-associative
 - Dcache is 2-way set-associative
 - Line size are 64bytes

So correct the cache-sets info.

Fixes: 2d87061e70dea ("arm64: dts: ti: Add Support for J721E SoC")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20211112063155.3485777-1-peng.fan@oss.nxp.com
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
index cc483f7344af3132aaa0059eb3e5b6c38ea19a5a..d1ef9fbe4981d125878edfbae5097acdfac38aa7 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
@@ -61,7 +61,7 @@
                        i-cache-sets = <256>;
                        d-cache-size = <0x8000>;
                        d-cache-line-size = <64>;
-                       d-cache-sets = <128>;
+                       d-cache-sets = <256>;
                        next-level-cache = <&L2_0>;
                };
 
@@ -75,7 +75,7 @@
                        i-cache-sets = <256>;
                        d-cache-size = <0x8000>;
                        d-cache-line-size = <64>;
-                       d-cache-sets = <128>;
+                       d-cache-sets = <256>;
                        next-level-cache = <&L2_0>;
                };
        };