ASoC: SOF: ipc4: Add set_core_state pm_ops implementation

IPC4 uses the SET_DX message to enable/disable cores managed by the DSP.
The dx_state.core_mask indicates which core is going to change state,
the dx_state.dx_mask is to power on (1) or off (0) the core.
In the dx_mask only those bits (cores) checked which bit is set in the
core_mask, other bits (cores) ignored.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20220610083549.16773-5-peter.ujfalusi@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/include/sound/sof/ipc4/header.h b/include/sound/sof/ipc4/header.h
index b8b8e5b5e3e1cddef43caf86214706332e9f76ab..a795deacc2eae482280a4210dc1088b770a731db 100644 (file)
--- a/include/sound/sof/ipc4/header.h
+++ b/include/sound/sof/ipc4/header.h
@@ -385,6 +385,14 @@ struct sof_ipc4_fw_version {
        uint16_t build;
 } __packed;
 
+/* Payload data for SOF_IPC4_MOD_SET_DX */
+struct sof_ipc4_dx_state_info {
+       /* core(s) to apply the change */
+       uint32_t core_mask;
+       /* core state: 0: put core_id to D3; 1: put core_id to D0 */
+       uint32_t dx_mask;
+} __packed __aligned(4);
+
 /* Reply messages */
 
 /*

diff --git a/sound/soc/sof/ipc4.c b/sound/soc/sof/ipc4.c
index 658802c86685a5c5c32de45b80ffb093b6b7c550..b2cb92745ec6e44bb81c3fdf3248ab8ae497a746 100644 (file)
--- a/sound/soc/sof/ipc4.c
+++ b/sound/soc/sof/ipc4.c
@@ -597,10 +597,36 @@ static void sof_ipc4_rx_msg(struct snd_sof_dev *sdev)
        }
 }
 
+static int sof_ipc4_set_core_state(struct snd_sof_dev *sdev, int core_idx, bool on)
+{
+       struct sof_ipc4_dx_state_info dx_state;
+       struct sof_ipc4_msg msg;
+
+       dx_state.core_mask = BIT(core_idx);
+       if (on)
+               dx_state.dx_mask = BIT(core_idx);
+       else
+               dx_state.dx_mask = 0;
+
+       msg.primary = SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_MOD_SET_DX);
+       msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
+       msg.primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG);
+       msg.extension = 0;
+       msg.data_ptr = &dx_state;
+       msg.data_size = sizeof(dx_state);
+
+       return sof_ipc4_tx_msg(sdev, &msg, msg.data_size, NULL, 0, false);
+}
+
+static const struct sof_ipc_pm_ops ipc4_pm_ops = {
+       .set_core_state = sof_ipc4_set_core_state,
+};
+
 const struct sof_ipc_ops ipc4_ops = {
        .tx_msg = sof_ipc4_tx_msg,
        .rx_msg = sof_ipc4_rx_msg,
        .set_get_data = sof_ipc4_set_get_data,
        .get_reply = sof_ipc4_get_reply,
+       .pm = &ipc4_pm_ops,
        .fw_loader = &ipc4_loader_ops,
 };