drm/i915/skl: s/SKL/SKYLAKE for platform/subplatform defines

Follow consistent naming convention. Replace SKL with
SKYLAKE and Replace IS_SKL_GRAPHICS_STEP with
IS_SKYLAKE() && IS_GRAPHICS_STEP().

v2:
- Change subject skl instead of SKL(Anusha)

v3:
- Unrolled wrapper IS_SKL_GRAPHICS_STEP.
- Replace with IS_PLATFORM && DISPLAY_STEP(tvrtko/jani)

v4:
- Removed the unused macro.

Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230801135344.3797924-4-dnyaneshwar.bhadane@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 5b2665a9d86dac88e8ea4fbf57e9e421cfc9e5e0..e85eab21b09dc38e3452e779f661cb8b73fa3f56 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1746,9 +1746,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
                encoder->get_buf_trans = kbl_u_get_buf_trans;
        } else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) || IS_KABYLAKE(i915)) {
                encoder->get_buf_trans = kbl_get_buf_trans;
-       } else if (IS_SKL_ULX(i915)) {
+       } else if (IS_SKYLAKE_ULX(i915)) {
                encoder->get_buf_trans = skl_y_get_buf_trans;
-       } else if (IS_SKL_ULT(i915)) {
+       } else if (IS_SKYLAKE_ULT(i915)) {
                encoder->get_buf_trans = skl_u_get_buf_trans;
        } else if (IS_SKYLAKE(i915)) {
                encoder->get_buf_trans = skl_get_buf_trans;

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 9634ab8d738b544532321de16bc6c0a64afaa780..b0b7d448364a07ed1439ce4ae11bf312e35f8b32 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1192,7 +1192,7 @@ skl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
                    GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
 
        /* WaInPlaceDecompressionHang:skl */
-       if (IS_SKL_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0))
+       if (IS_SKYLAKE(gt->i915) && IS_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0))
                wa_write_or(wal,
                            GEN9_GAMT_ECO_REG_RW_IA,
                            GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f3f2ca5c1f922266b93bd0af63dfd4c25f568741..ff853c4b78012a857e2745b58b62b5e1a9734440 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -608,19 +608,19 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 /* ULX machines are also considered ULT. */
 #define IS_HASWELL_ULX(i915) \
        IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
-#define IS_SKL_ULT(i915) \
+#define IS_SKYLAKE_ULT(i915) \
        IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
-#define IS_SKL_ULX(i915) \
+#define IS_SKYLAKE_ULX(i915) \
        IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
 #define IS_KBL_ULT(i915) \
        IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
 #define IS_KBL_ULX(i915) \
        IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
-#define IS_SKL_GT2(i915)       (IS_SKYLAKE(i915) && \
+#define IS_SKYLAKE_GT2(i915)   (IS_SKYLAKE(i915) && \
                                 INTEL_INFO(i915)->gt == 2)
-#define IS_SKL_GT3(i915)       (IS_SKYLAKE(i915) && \
+#define IS_SKYLAKE_GT3(i915)   (IS_SKYLAKE(i915) && \
                                 INTEL_INFO(i915)->gt == 3)
-#define IS_SKL_GT4(i915)       (IS_SKYLAKE(i915) && \
+#define IS_SKYLAKE_GT4(i915)   (IS_SKYLAKE(i915) && \
                                 INTEL_INFO(i915)->gt == 4)
 #define IS_KBL_GT2(i915)       (IS_KABYLAKE(i915) && \
                                 INTEL_INFO(i915)->gt == 2)
@@ -648,7 +648,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_TGL_UY(i915) \
        IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
 
-#define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))
 
 #define IS_KBL_GRAPHICS_STEP(i915, since, until) \
        (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, since, until))
@@ -799,7 +798,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 /* WaRsDisableCoarsePowerGating:skl,cnl */
 #define NEEDS_WaRsDisableCoarsePowerGating(i915)                       \
-       (IS_SKL_GT3(i915) || IS_SKL_GT4(i915))
+       (IS_SKYLAKE_GT3(i915) || IS_SKYLAKE_GT4(i915))
 
 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  * rows, which changed the alignment requirements and fence programming.