net: axienet: reset core on initialization prior to MDIO access

commit 04cc2da39698efd7eb2e30c112538922d26f848e upstream.

In some cases where the Xilinx Ethernet core was used in 1000Base-X or
SGMII modes, which use the internal PCS/PMA PHY, and the MGT
transceiver clock source for the PCS was not running at the time the
FPGA logic was loaded, the core would come up in a state where the
PCS could not be found on the MDIO bus. To fix this, the Ethernet core
(including the PCS) should be reset after enabling the clocks, prior to
attempting to access the PCS using of_mdio_find_device.

Fixes: 1a02556086fc (net: axienet: Properly handle PCS/PMA PHY for 1000BaseX mode)
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
index 811f15eace9f5f2e992ea33b9394862f743bdee3..7b94784a1465ec1b8d0891f7a8f9fa89c1fd3bff 100644 (file)
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
@@ -2024,6 +2024,11 @@ static int axienet_probe(struct platform_device *pdev)
        lp->coalesce_count_rx = XAXIDMA_DFT_RX_THRESHOLD;
        lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
 
+       /* Reset core now that clocks are enabled, prior to accessing MDIO */
+       ret = __axienet_device_reset(lp);
+       if (ret)
+               goto cleanup_clk;
+
        lp->phy_node = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
        if (lp->phy_node) {
                ret = axienet_mdio_setup(lp);