cpufreq: ti: update OPP table for AM62Ax SoCs

As the AM62Ax SoC family matures more speed grades are being defined.
These new grades unfortunately no longer align with the AM62x SoC
family. Define a new table with new OPP speed grade limits for the
AM62Ax

Reviewed-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>

diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c
index 5af85c4cbad0cc151464cbaff98f2f73b917f51c..80f47a33420a65e169f94b610157356f2f079a54 100644 (file)
--- a/drivers/cpufreq/ti-cpufreq.c
+++ b/drivers/cpufreq/ti-cpufreq.c
@@ -47,6 +47,28 @@
 #define AM625_SUPPORT_S_MPU_OPP                        BIT(1)
 #define AM625_SUPPORT_T_MPU_OPP                        BIT(2)
 
+enum {
+       AM62A7_EFUSE_M_MPU_OPP =                13,
+       AM62A7_EFUSE_N_MPU_OPP,
+       AM62A7_EFUSE_O_MPU_OPP,
+       AM62A7_EFUSE_P_MPU_OPP,
+       AM62A7_EFUSE_Q_MPU_OPP,
+       AM62A7_EFUSE_R_MPU_OPP,
+       AM62A7_EFUSE_S_MPU_OPP,
+       /*
+        * The V, U, and T speed grade numbering is out of order
+        * to align with the AM625 more uniformly. I promise I know
+        * my ABCs ;)
+        */
+       AM62A7_EFUSE_V_MPU_OPP,
+       AM62A7_EFUSE_U_MPU_OPP,
+       AM62A7_EFUSE_T_MPU_OPP,
+};
+
+#define AM62A7_SUPPORT_N_MPU_OPP               BIT(0)
+#define AM62A7_SUPPORT_R_MPU_OPP               BIT(1)
+#define AM62A7_SUPPORT_V_MPU_OPP               BIT(2)
+
 #define VERSION_COUNT                          2
 
 struct ti_cpufreq_data;
@@ -112,6 +134,32 @@ static unsigned long omap3_efuse_xlate(struct ti_cpufreq_data *opp_data,
        return BIT(efuse);
 }
 
+static unsigned long am62a7_efuse_xlate(struct ti_cpufreq_data *opp_data,
+                                       unsigned long efuse)
+{
+       unsigned long calculated_efuse = AM62A7_SUPPORT_N_MPU_OPP;
+
+       switch (efuse) {
+       case AM62A7_EFUSE_V_MPU_OPP:
+       case AM62A7_EFUSE_U_MPU_OPP:
+       case AM62A7_EFUSE_T_MPU_OPP:
+       case AM62A7_EFUSE_S_MPU_OPP:
+               calculated_efuse |= AM62A7_SUPPORT_V_MPU_OPP;
+               fallthrough;
+       case AM62A7_EFUSE_R_MPU_OPP:
+       case AM62A7_EFUSE_Q_MPU_OPP:
+       case AM62A7_EFUSE_P_MPU_OPP:
+       case AM62A7_EFUSE_O_MPU_OPP:
+               calculated_efuse |= AM62A7_SUPPORT_R_MPU_OPP;
+               fallthrough;
+       case AM62A7_EFUSE_N_MPU_OPP:
+       case AM62A7_EFUSE_M_MPU_OPP:
+               calculated_efuse |= AM62A7_SUPPORT_N_MPU_OPP;
+       }
+
+       return calculated_efuse;
+}
+
 static unsigned long am625_efuse_xlate(struct ti_cpufreq_data *opp_data,
                                       unsigned long efuse)
 {
@@ -234,6 +282,15 @@ static struct ti_cpufreq_soc_data am625_soc_data = {
        .multi_regulator = false,
 };
 
+static struct ti_cpufreq_soc_data am62a7_soc_data = {
+       .efuse_xlate = am62a7_efuse_xlate,
+       .efuse_offset = 0x0,
+       .efuse_mask = 0x07c0,
+       .efuse_shift = 0x6,
+       .rev_offset = 0x0014,
+       .multi_regulator = false,
+};
+
 /**
  * ti_cpufreq_get_efuse() - Parse and return efuse value present on SoC
  * @opp_data: pointer to ti_cpufreq_data context
@@ -337,7 +394,7 @@ static const struct of_device_id ti_cpufreq_of_match[] = {
        { .compatible = "ti,omap34xx", .data = &omap34xx_soc_data, },
        { .compatible = "ti,omap36xx", .data = &omap36xx_soc_data, },
        { .compatible = "ti,am625", .data = &am625_soc_data, },
-       { .compatible = "ti,am62a7", .data = &am625_soc_data, },
+       { .compatible = "ti,am62a7", .data = &am62a7_soc_data, },
        { .compatible = "ti,am62p5", .data = &am625_soc_data, },
        /* legacy */
        { .compatible = "ti,omap3430", .data = &omap34xx_soc_data, },