drm/i915/dp: move g4x_dp_set_clock() call to g4x_dp_compute_config()
authorJani Nikula <jani.nikula@intel.com>
Wed, 11 Dec 2024 12:54:31 +0000 (14:54 +0200)
committerJani Nikula <jani.nikula@intel.com>
Wed, 11 Dec 2024 17:06:10 +0000 (19:06 +0200)
It does not look like anything in intel_dp_compute_config() after the
g4x_dp_set_clock() call depends on the changes it makes, namely setting
dpll and clock_set in crtc_state. Move the call one level higher to
g4x_dp_compute_config() to reduce the clutter in
intel_dp_compute_config().

Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241211125431.680227-2-jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/display/g4x_dp.c
drivers/gpu/drm/i915/display/g4x_dp.h
drivers/gpu/drm/i915/display/intel_dp.c

index 9ac894a7411f3c01078e0e1fda4f76216efe8a27..e06405a3b82db1f61dceb57f93a33cbb2a8a9746 100644 (file)
@@ -55,8 +55,8 @@ const struct dpll *vlv_get_dpll(struct drm_i915_private *i915)
        return IS_CHERRYVIEW(i915) ? &chv_dpll[0] : &vlv_dpll[0];
 }
 
-void g4x_dp_set_clock(struct intel_encoder *encoder,
-                     struct intel_crtc_state *pipe_config)
+static void g4x_dp_set_clock(struct intel_encoder *encoder,
+                            struct intel_crtc_state *pipe_config)
 {
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
        const struct dpll *divisor = NULL;
@@ -1228,11 +1228,18 @@ static int g4x_dp_compute_config(struct intel_encoder *encoder,
                                 struct drm_connector_state *conn_state)
 {
        struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+       int ret;
 
        if (HAS_PCH_SPLIT(i915) && encoder->port != PORT_A)
                crtc_state->has_pch_encoder = true;
 
-       return intel_dp_compute_config(encoder, crtc_state, conn_state);
+       ret = intel_dp_compute_config(encoder, crtc_state, conn_state);
+       if (ret)
+               return ret;
+
+       g4x_dp_set_clock(encoder, crtc_state);
+
+       return 0;
 }
 
 static void g4x_dp_suspend_complete(struct intel_encoder *encoder)
index c75e64ae79b700be2c6360068238ebb9bb24ed42..839a251dc06951fe679d08117745307a1267feb3 100644 (file)
@@ -19,8 +19,6 @@ struct intel_encoder;
 
 #ifdef I915
 const struct dpll *vlv_get_dpll(struct drm_i915_private *i915);
-void g4x_dp_set_clock(struct intel_encoder *encoder,
-                     struct intel_crtc_state *pipe_config);
 bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv,
                         i915_reg_t dp_reg, enum port port,
                         enum pipe *pipe);
@@ -31,10 +29,6 @@ static inline const struct dpll *vlv_get_dpll(struct drm_i915_private *i915)
 {
        return NULL;
 }
-static inline void g4x_dp_set_clock(struct intel_encoder *encoder,
-                                   struct intel_crtc_state *pipe_config)
-{
-}
 static inline bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv,
                                       i915_reg_t dp_reg, int port,
                                       enum pipe *pipe)
index adc51567ec1730e10be5f067edda315f04723160..f8100c4f4d20378c0ee4b89f39a07824a85b334c 100644 (file)
@@ -3172,9 +3172,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
        if (pipe_config->splitter.enable)
                pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
 
-       if (!HAS_DDI(dev_priv))
-               g4x_dp_set_clock(encoder, pipe_config);
-
        intel_vrr_compute_config(pipe_config, conn_state);
        intel_dp_compute_as_sdp(intel_dp, pipe_config);
        intel_psr_compute_config(intel_dp, pipe_config, conn_state);