drm/amdgpu/dc: Revert commit "treat memory as a single-channel"

This reverts commit "dc: treat memory as a single-channel for
asymmetric memory".

Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Wayne Lin <Wayne.Lin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 49d19fdd750b608b0b143aae0fce2d7086622528..887a54246bde061ab1b0a5156d0945832351af4a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -761,43 +761,6 @@ static struct wm_table ddr4_wm_table_rn = {
        }
 };
 
-static struct wm_table ddr4_1R_wm_table_rn = {
-       .entries = {
-               {
-                       .wm_inst = WM_A,
-                       .wm_type = WM_TYPE_PSTATE_CHG,
-                       .pstate_latency_us = 11.72,
-                       .sr_exit_time_us = 13.90,
-                       .sr_enter_plus_exit_time_us = 14.80,
-                       .valid = true,
-               },
-               {
-                       .wm_inst = WM_B,
-                       .wm_type = WM_TYPE_PSTATE_CHG,
-                       .pstate_latency_us = 11.72,
-                       .sr_exit_time_us = 13.90,
-                       .sr_enter_plus_exit_time_us = 14.80,
-                       .valid = true,
-               },
-               {
-                       .wm_inst = WM_C,
-                       .wm_type = WM_TYPE_PSTATE_CHG,
-                       .pstate_latency_us = 11.72,
-                       .sr_exit_time_us = 13.90,
-                       .sr_enter_plus_exit_time_us = 14.80,
-                       .valid = true,
-               },
-               {
-                       .wm_inst = WM_D,
-                       .wm_type = WM_TYPE_PSTATE_CHG,
-                       .pstate_latency_us = 11.72,
-                       .sr_exit_time_us = 13.90,
-                       .sr_enter_plus_exit_time_us = 14.80,
-                       .valid = true,
-               },
-       }
-};
-
 static struct wm_table lpddr4_wm_table_rn = {
        .entries = {
                {
@@ -982,12 +945,8 @@ void rn_clk_mgr_construct(
                } else {
                        if (is_green_sardine)
                                rn_bw_params.wm_table = ddr4_wm_table_gs;
-                       else {
-                               if (ctx->dc->config.is_single_rank_dimm)
-                                       rn_bw_params.wm_table = ddr4_1R_wm_table_rn;
-                               else
-                                       rn_bw_params.wm_table = ddr4_wm_table_rn;
-                       }
+                       else
+                               rn_bw_params.wm_table = ddr4_wm_table_rn;
                }
                /* Saved clocks configured at boot for debug purposes */
                rn_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);
@@ -1005,9 +964,6 @@ void rn_clk_mgr_construct(
                if (status == PP_SMU_RESULT_OK &&
                    ctx->dc_bios && ctx->dc_bios->integrated_info) {
                        rn_clk_mgr_helper_populate_bw_params (clk_mgr->base.bw_params, &clock_table, ctx->dc_bios->integrated_info);
-                       /* treat memory config as single channel if memory is asymmetrics. */
-                       if (ctx->dc->config.is_asymmetric_memory)
-                               clk_mgr->base.bw_params->num_channels = 1;
                }
        }
 

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 86e6649cb8c51d1ecdf034703509539ce7e9d736..42b9b08324e7f42a29365f3a7d79f93a6d5ea06d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -308,8 +308,6 @@ struct dc_config {
 #endif
        uint64_t vblank_alignment_dto_params;
        uint8_t  vblank_alignment_max_frame_time_diff;
-       bool is_asymmetric_memory;
-       bool is_single_rank_dimm;
 };
 
 enum visual_confirm {