drm/ingenic: Add support for 30-bit modes
authorPaul Cercueil <paul@crapouillou.net>
Sat, 26 Sep 2020 17:05:00 +0000 (19:05 +0200)
committerPaul Cercueil <paul@crapouillou.net>
Sat, 26 Sep 2020 19:55:36 +0000 (21:55 +0200)
Starting from the JZ4760 SoC, the primary and overlay planes support
30-bit pixel modes (10 bits per color component). Add support for these
in the ingenic-drm driver.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20200926170501.1109197-7-paul@crapouillou.net
drivers/gpu/drm/ingenic/ingenic-drm-drv.c
drivers/gpu/drm/ingenic/ingenic-drm.h

index 567facfb7217bc59cd2216b63561866f0aeb8ba1..b5681379ade550390cf5ae0e970410d08fa5dd37 100644 (file)
@@ -458,6 +458,9 @@ void ingenic_drm_plane_config(struct device *dev,
                case DRM_FORMAT_XRGB8888:
                        ctrl |= JZ_LCD_OSDCTRL_BPP_18_24;
                        break;
+               case DRM_FORMAT_XRGB2101010:
+                       ctrl |= JZ_LCD_OSDCTRL_BPP_30;
+                       break;
                }
 
                regmap_update_bits(priv->map, JZ_REG_LCD_OSDCTRL,
@@ -473,6 +476,9 @@ void ingenic_drm_plane_config(struct device *dev,
                case DRM_FORMAT_XRGB8888:
                        ctrl |= JZ_LCD_CTRL_BPP_18_24;
                        break;
+               case DRM_FORMAT_XRGB2101010:
+                       ctrl |= JZ_LCD_CTRL_BPP_30;
+                       break;
                }
 
                regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
@@ -1222,12 +1228,14 @@ static const u32 jz4770_formats_f1[] = {
        DRM_FORMAT_XRGB1555,
        DRM_FORMAT_RGB565,
        DRM_FORMAT_XRGB8888,
+       DRM_FORMAT_XRGB2101010,
 };
 
 static const u32 jz4770_formats_f0[] = {
        DRM_FORMAT_XRGB1555,
        DRM_FORMAT_RGB565,
        DRM_FORMAT_XRGB8888,
+       DRM_FORMAT_XRGB2101010,
 };
 
 static const struct jz_soc_info jz4740_soc_info = {
index df99f0f75d39356f071dac891e4bc07a24cd605f..f05e18e6b6fa4ccebd34380bf4ace56d3354a0f5 100644 (file)
 #define JZ_LCD_CTRL_BPP_8                      0x3
 #define JZ_LCD_CTRL_BPP_15_16                  0x4
 #define JZ_LCD_CTRL_BPP_18_24                  0x5
+#define JZ_LCD_CTRL_BPP_30                     0x7
 #define JZ_LCD_CTRL_BPP_MASK                   (JZ_LCD_CTRL_RGB555 | 0x7)
 
 #define JZ_LCD_CMD_SOF_IRQ                     BIT(31)