dt-bindings: clock: qcom: Document the X1E80100 GPU Clock Controller

Add bindings documentation for the X1E80100 Graphics Clock Controller.

Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-3-7fb08c861c7c@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
index 1a384e8532a59cc99f8e58e3df4b570b16668690..36974309cf6964b821a06d4be73dfb599617c17d 100644 (file)
--- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
@@ -18,6 +18,7 @@ description: |
     include/dt-bindings/clock/qcom,sm8550-gpucc.h
     include/dt-bindings/reset/qcom,sm8450-gpucc.h
     include/dt-bindings/reset/qcom,sm8650-gpucc.h
+    include/dt-bindings/reset/qcom,x1e80100-gpucc.h
 
 properties:
   compatible:
@@ -25,6 +26,7 @@ properties:
       - qcom,sm8450-gpucc
       - qcom,sm8550-gpucc
       - qcom,sm8650-gpucc
+      - qcom,x1e80100-gpucc
 
   clocks:
     items:

diff --git a/include/dt-bindings/clock/qcom,x1e80100-gpucc.h b/include/dt-bindings/clock/qcom,x1e80100-gpucc.h
new file mode 100644 (file)
index 0000000..61a3a8f
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,x1e80100-gpucc.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_GPU_CC_H
+#define _DT_BINDINGS_CLK_QCOM_X1E80100_GPU_CC_H
+
+/* GPU_CC clocks */
+#define GPU_CC_AHB_CLK                                         0
+#define GPU_CC_CB_CLK                                          1
+#define GPU_CC_CRC_AHB_CLK                                     2
+#define GPU_CC_CX_FF_CLK                                       3
+#define GPU_CC_CX_GMU_CLK                                      4
+#define GPU_CC_CXO_AON_CLK                                     5
+#define GPU_CC_CXO_CLK                                         6
+#define GPU_CC_DEMET_CLK                                       7
+#define GPU_CC_DEMET_DIV_CLK_SRC                               8
+#define GPU_CC_FF_CLK_SRC                                      9
+#define GPU_CC_FREQ_MEASURE_CLK                                        10
+#define GPU_CC_GMU_CLK_SRC                                     11
+#define GPU_CC_GX_GMU_CLK                                      12
+#define GPU_CC_GX_VSENSE_CLK                                   13
+#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK                         14
+#define GPU_CC_HUB_AON_CLK                                     15
+#define GPU_CC_HUB_CLK_SRC                                     16
+#define GPU_CC_HUB_CX_INT_CLK                                  17
+#define GPU_CC_MEMNOC_GFX_CLK                                  18
+#define GPU_CC_MND1X_0_GFX3D_CLK                               19
+#define GPU_CC_MND1X_1_GFX3D_CLK                               20
+#define GPU_CC_PLL0                                            21
+#define GPU_CC_PLL1                                            22
+#define GPU_CC_SLEEP_CLK                                       23
+#define GPU_CC_XO_CLK_SRC                                      24
+#define GPU_CC_XO_DIV_CLK_SRC                                  25
+
+/* GDSCs */
+#define GPU_CX_GDSC                                            0
+#define GPU_GX_GDSC                                            1
+
+#endif

diff --git a/include/dt-bindings/reset/qcom,x1e80100-gpucc.h b/include/dt-bindings/reset/qcom,x1e80100-gpucc.h
new file mode 100644 (file)
index 0000000..32b43e7
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,x1e80100-gpucc.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_RESET_QCOM_X1E80100_GPU_CC_H
+#define _DT_BINDINGS_RESET_QCOM_X1E80100_GPU_CC_H
+
+#define GPUCC_GPU_CC_ACD_BCR                                   0
+#define GPUCC_GPU_CC_CB_BCR                                    1
+#define GPUCC_GPU_CC_CX_BCR                                    2
+#define GPUCC_GPU_CC_FAST_HUB_BCR                              3
+#define GPUCC_GPU_CC_FF_BCR                                    4
+#define GPUCC_GPU_CC_GFX3D_AON_BCR                             5
+#define GPUCC_GPU_CC_GMU_BCR                                   6
+#define GPUCC_GPU_CC_GX_BCR                                    7
+#define GPUCC_GPU_CC_XO_BCR                                    8
+
+#endif