drm/amd/display: Add z10 restore checks for DC interfaces

DMCUB has a deferred z10 restore process that needs signalling from
driver to occur. This needs to be done on any interface that programs
the hardware state or sequences where we expect to have the same
hardware state as before.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index f03889b3654bb29e220b07abf194a5b22152e548..7017db8007185f3974c13f348fe9ae9f827c2403 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1482,6 +1482,13 @@ static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context)
        return stream_mask;
 }
 
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+void dc_z10_restore(struct dc *dc)
+{
+       if (dc->hwss.z10_restore)
+               dc->hwss.z10_restore(dc);
+}
+#endif
 /*
  * Applies given context to HW and copy it into current context.
  * It's up to the user to release the src context afterwards.
@@ -1495,6 +1502,9 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
        struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
 
 #if defined(CONFIG_DRM_AMD_DC_DCN)
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+       dc_z10_restore(dc);
+#endif
        dc_allow_idle_optimizations(dc, false);
 #endif
 
@@ -2569,6 +2579,10 @@ static void commit_planes_for_stream(struct dc *dc,
        int i, j;
        struct pipe_ctx *top_pipe_to_program = NULL;
 
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+       dc_z10_restore(dc);
+#endif
+
        if (get_seamless_boot_stream_count(context) > 0 && surface_count > 0) {
                /* Optimize seamless boot flag keeps clocks and watermarks high until
                 * first flip. After first flip, optimization is required to lower
@@ -3024,6 +3038,9 @@ void dc_set_power_state(
        case DC_ACPI_CM_POWER_STATE_D0:
                dc_resource_state_construct(dc, dc->current_state);
 
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+               dc_z10_restore(dc);
+#endif
                if (dc->ctx->dmub_srv)
                        dc_dmub_srv_wait_phy_init(dc->ctx->dmub_srv);
 

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 31ba40746a2f33f0fc822b2e3e3f731ae7c78ed0..6e93e6aed8ff284f6c2903ff2b1c3abd1297e203 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2706,6 +2706,10 @@ bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active,
                return false;
 
        link->psr_settings.psr_allow_active = allow_active;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+       if (!allow_active)
+               dc_z10_restore(dc);
+#endif
 
        if (psr != NULL && link->psr_settings.psr_feature_enabled) {
                if (force_static && psr->funcs->psr_force_static)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 25fa712a7847464b4f4215d631d6ba8a1e8e4919..5420fda47bb79ab3971319466ff0531743e8acde 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -294,6 +294,9 @@ bool dc_stream_set_cursor_attributes(
        stream->cursor_attributes = *attributes;
 
 #if defined(CONFIG_DRM_AMD_DC_DCN)
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+       dc_z10_restore(dc);
+#endif
        /* disable idle optimizations while updating cursor */
        if (dc->idle_optimizations_allowed) {
                dc_allow_idle_optimizations(dc, false);
@@ -355,6 +358,9 @@ bool dc_stream_set_cursor_position(
        dc = stream->ctx->dc;
        res_ctx = &dc->current_state->res_ctx;
 #if defined(CONFIG_DRM_AMD_DC_DCN)
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+       dc_z10_restore(dc);
+#endif
 
        /* disable idle optimizations if enabling cursor */
        if (dc->idle_optimizations_allowed && !stream->cursor_position.enable && position->enable) {

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index ba47979c9cb0887add04afd1afdc48670385ac1b..05aae14198120d63db1e8df60e3710f9289cb2b9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1326,6 +1326,9 @@ void dc_hardware_release(struct dc *dc);
 #endif
 
 bool dc_set_psr_allow_active(struct dc *dc, bool enable);
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+void dc_z10_restore(struct dc *dc);
+#endif
 
 bool dc_enable_dmub_notifications(struct dc *dc);