.num_vco = ARRAY_SIZE(gpu_vco),
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_pll0_pll_out_main",
- .parent_data = &(const struct clk_parent_data){
- .hw = &gpucc_cxo_clk.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &gpucc_cxo_clk.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
.num_vco = ARRAY_SIZE(gpu_vco),
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_pll1_pll_out_main",
- .parent_data = &(const struct clk_parent_data){
- .hw = &gpucc_cxo_clk.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &gpucc_cxo_clk.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpucc_gfx3d_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &gfx3d_clk_src.rcg.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &gfx3d_clk_src.rcg.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,