drm/amd/display: Force max clocks unconditionally when p-state is unsupported

[WHY&HOW]
UCLK and FCLK are updated together, so an FCLK update can also cause UCLK update
to SMU.  When this happens, the UCLK provided should be max if switching is
unsupported.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
index 0975986f59890f13d79ac9dcdfca1cf8c8a1a0c8..0fbe615069f085f7071d5a9b6963a40410c2bd92 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
@@ -791,14 +791,16 @@ static unsigned int dcn401_build_update_bandwidth_clocks_sequence(
                                block_sequence[num_steps].func = CLK_MGR401_UPDATE_FCLK_PSTATE_SUPPORT;
                                num_steps++;
                        }
-               } else {
-                       /* P-State is not supported so force max clocks */
-                       idle_fclk_mhz =
-                                       clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_fclk_levels - 1].fclk_mhz;
-                       active_fclk_mhz = idle_fclk_mhz;
                }
        }
 
+       if (!clk_mgr_base->clks.fclk_p_state_change_support && dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_FCLK)) {
+               /* when P-State switching disabled, set UCLK min = max */
+               idle_fclk_mhz =
+                               clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_fclk_levels - 1].fclk_mhz;
+               active_fclk_mhz = idle_fclk_mhz;
+       }
+
        /* UPDATE DCFCLK */
        if (dc->debug.force_min_dcfclk_mhz > 0)
                new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
@@ -872,19 +874,21 @@ static unsigned int dcn401_build_update_bandwidth_clocks_sequence(
                                block_sequence[num_steps].func = CLK_MGR401_UPDATE_UCLK_PSTATE_SUPPORT;
                                num_steps++;
                        }
+               }
+       }
+
+       if (!clk_mgr_base->clks.p_state_change_support && dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {
+               /* when P-State switching disabled, set UCLK min = max */
+               if (dc->clk_mgr->dc_mode_softmax_enabled) {
+                       /* will never have the functional UCLK min above the softmax
+                       * since we calculate mode support based on softmax being the max UCLK
+                       * frequency.
+                       */
+                       active_uclk_mhz = clk_mgr_base->bw_params->dc_mode_softmax_memclk;
                } else {
-                       /* when disabling P-State switching, set UCLK min = max */
-                       if (dc->clk_mgr->dc_mode_softmax_enabled) {
-                               /* will never have the functional UCLK min above the softmax
-                               * since we calculate mode support based on softmax being the max UCLK
-                               * frequency.
-                               */
-                               active_uclk_mhz = clk_mgr_base->bw_params->dc_mode_softmax_memclk;
-                       } else {
-                               active_uclk_mhz = clk_mgr_base->bw_params->max_memclk_mhz;
-                       }
-                       idle_uclk_mhz = active_uclk_mhz;
+                       active_uclk_mhz = clk_mgr_base->bw_params->max_memclk_mhz;
                }
+               idle_uclk_mhz = active_uclk_mhz;
        }
 
        /* Always update saved value, even if new value not set due to P-State switching unsupported */