clk: meson: g12a-aoclk: migrate to the new parent description method
authorAlexandre Mergnat <amergnat@baylibre.com>
Thu, 25 Jul 2019 16:41:23 +0000 (18:41 +0200)
committerJerome Brunet <jbrunet@baylibre.com>
Mon, 29 Jul 2019 10:42:48 +0000 (12:42 +0200)
This clock controller use the string comparison method to describe parent
relation between the clocks, which is not optimized.

Migrate to the new way by using .parent_hws where possible (when parent
clocks are localy declared in the controller) and use .parent_data
otherwise.

Remove clk input helper and all bypass clocks (declared in probe function)
which are no longer used since we are able to use device-tree clock name
directly.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
drivers/clk/meson/g12a-aoclk.c

index 1994e735396b53aae310390405f8b04a95499101..62499563e4f5a5f2942cbcadaf624376c82ff9e9 100644 (file)
@@ -18,8 +18,6 @@
 #include "clk-regmap.h"
 #include "clk-dualdiv.h"
 
-#define IN_PREFIX "ao-in-"
-
 /*
  * AO Configuration Clock registers offsets
  * Register offsets from the data sheet must be multiplied by 4.
@@ -51,7 +49,9 @@ static struct clk_regmap g12a_aoclk_##_name = {                               \
        .hw.init = &(struct clk_init_data) {                            \
                .name =  "g12a_ao_" #_name,                             \
                .ops = &clk_regmap_gate_ops,                            \
-               .parent_names = (const char *[]){ IN_PREFIX "mpeg-clk" }, \
+               .parent_data = &(const struct clk_parent_data) {        \
+                       .fw_name = "mpeg-clk",                          \
+               },                                                      \
                .num_parents = 1,                                       \
                .flags = CLK_IGNORE_UNUSED,                             \
        },                                                              \
@@ -81,7 +81,9 @@ static struct clk_regmap g12a_aoclk_cts_oscin = {
        .hw.init = &(struct clk_init_data){
                .name = "cts_oscin",
                .ops = &clk_regmap_gate_ro_ops,
-               .parent_names = (const char *[]){ IN_PREFIX "xtal" },
+               .parent_data = &(const struct clk_parent_data) {
+                       .fw_name = "xtal",
+               },
                .num_parents = 1,
        },
 };
@@ -106,7 +108,9 @@ static struct clk_regmap g12a_aoclk_32k_by_oscin_pre = {
        .hw.init = &(struct clk_init_data){
                .name = "g12a_ao_32k_by_oscin_pre",
                .ops = &clk_regmap_gate_ops,
-               .parent_names = (const char *[]){ "cts_oscin" },
+               .parent_hws = (const struct clk_hw *[]) {
+                       &g12a_aoclk_cts_oscin.hw
+               },
                .num_parents = 1,
        },
 };
@@ -143,7 +147,9 @@ static struct clk_regmap g12a_aoclk_32k_by_oscin_div = {
        .hw.init = &(struct clk_init_data){
                .name = "g12a_ao_32k_by_oscin_div",
                .ops = &meson_clk_dualdiv_ops,
-               .parent_names = (const char *[]){ "g12a_ao_32k_by_oscin_pre" },
+               .parent_hws = (const struct clk_hw *[]) {
+                       &g12a_aoclk_32k_by_oscin_pre.hw
+               },
                .num_parents = 1,
        },
 };
@@ -158,8 +164,10 @@ static struct clk_regmap g12a_aoclk_32k_by_oscin_sel = {
        .hw.init = &(struct clk_init_data){
                .name = "g12a_ao_32k_by_oscin_sel",
                .ops = &clk_regmap_mux_ops,
-               .parent_names = (const char *[]){ "g12a_ao_32k_by_oscin_div",
-                                                 "g12a_ao_32k_by_oscin_pre" },
+               .parent_hws = (const struct clk_hw *[]) {
+                       &g12a_aoclk_32k_by_oscin_div.hw,
+                       &g12a_aoclk_32k_by_oscin_pre.hw,
+               },
                .num_parents = 2,
                .flags = CLK_SET_RATE_PARENT,
        },
@@ -173,7 +181,9 @@ static struct clk_regmap g12a_aoclk_32k_by_oscin = {
        .hw.init = &(struct clk_init_data){
                .name = "g12a_ao_32k_by_oscin",
                .ops = &clk_regmap_gate_ops,
-               .parent_names = (const char *[]){ "g12a_ao_32k_by_oscin_sel" },
+               .parent_hws = (const struct clk_hw *[]) {
+                       &g12a_aoclk_32k_by_oscin_sel.hw
+               },
                .num_parents = 1,
                .flags = CLK_SET_RATE_PARENT,
        },
@@ -189,7 +199,9 @@ static struct clk_regmap g12a_aoclk_cec_pre = {
        .hw.init = &(struct clk_init_data){
                .name = "g12a_ao_cec_pre",
                .ops = &clk_regmap_gate_ops,
-               .parent_names = (const char *[]){ "cts_oscin" },
+               .parent_hws = (const struct clk_hw *[]) {
+                       &g12a_aoclk_cts_oscin.hw
+               },
                .num_parents = 1,
        },
 };
@@ -226,7 +238,9 @@ static struct clk_regmap g12a_aoclk_cec_div = {
        .hw.init = &(struct clk_init_data){
                .name = "g12a_ao_cec_div",
                .ops = &meson_clk_dualdiv_ops,
-               .parent_names = (const char *[]){ "g12a_ao_cec_pre" },
+               .parent_hws = (const struct clk_hw *[]) {
+                       &g12a_aoclk_cec_pre.hw
+               },
                .num_parents = 1,
        },
 };
@@ -241,8 +255,10 @@ static struct clk_regmap g12a_aoclk_cec_sel = {
        .hw.init = &(struct clk_init_data){
                .name = "g12a_ao_cec_sel",
                .ops = &clk_regmap_mux_ops,
-               .parent_names = (const char *[]){ "g12a_ao_cec_div",
-                                                 "g12a_ao_cec_pre" },
+               .parent_hws = (const struct clk_hw *[]) {
+                       &g12a_aoclk_cec_div.hw,
+                       &g12a_aoclk_cec_pre.hw,
+               },
                .num_parents = 2,
                .flags = CLK_SET_RATE_PARENT,
        },
@@ -256,7 +272,9 @@ static struct clk_regmap g12a_aoclk_cec = {
        .hw.init = &(struct clk_init_data){
                .name = "g12a_ao_cec",
                .ops = &clk_regmap_gate_ops,
-               .parent_names = (const char *[]){ "g12a_ao_cec_sel" },
+               .parent_hws = (const struct clk_hw *[]) {
+                       &g12a_aoclk_cec_sel.hw
+               },
                .num_parents = 1,
                .flags = CLK_SET_RATE_PARENT,
        },
@@ -272,8 +290,10 @@ static struct clk_regmap g12a_aoclk_cts_rtc_oscin = {
        .hw.init = &(struct clk_init_data){
                .name = "g12a_ao_cts_rtc_oscin",
                .ops = &clk_regmap_mux_ops,
-               .parent_names = (const char *[]){ "g12a_ao_32k_by_oscin",
-                                                 IN_PREFIX "ext_32k-0" },
+               .parent_data = (const struct clk_parent_data []) {
+                       { .hw = &g12a_aoclk_32k_by_oscin.hw },
+                       { .fw_name = "ext-32k-0", },
+               },
                .num_parents = 2,
                .flags = CLK_SET_RATE_PARENT,
        },
@@ -289,8 +309,10 @@ static struct clk_regmap g12a_aoclk_clk81 = {
        .hw.init = &(struct clk_init_data){
                .name = "g12a_ao_clk81",
                .ops = &clk_regmap_mux_ro_ops,
-               .parent_names = (const char *[]){ IN_PREFIX "mpeg-clk",
-                                                 "g12a_ao_cts_rtc_oscin"},
+               .parent_data = (const struct clk_parent_data []) {
+                       { .fw_name = "mpeg-clk", },
+                       { .hw = &g12a_aoclk_cts_rtc_oscin.hw },
+               },
                .num_parents = 2,
                .flags = CLK_SET_RATE_PARENT,
        },
@@ -305,8 +327,10 @@ static struct clk_regmap g12a_aoclk_saradc_mux = {
        .hw.init = &(struct clk_init_data){
                .name = "g12a_ao_saradc_mux",
                .ops = &clk_regmap_mux_ops,
-               .parent_names = (const char *[]){ IN_PREFIX "xtal",
-                                                 "g12a_ao_clk81" },
+               .parent_data = (const struct clk_parent_data []) {
+                       { .fw_name = "xtal", },
+                       { .hw = &g12a_aoclk_clk81.hw },
+               },
                .num_parents = 2,
        },
 };
@@ -320,7 +344,9 @@ static struct clk_regmap g12a_aoclk_saradc_div = {
        .hw.init = &(struct clk_init_data){
                .name = "g12a_ao_saradc_div",
                .ops = &clk_regmap_divider_ops,
-               .parent_names = (const char *[]){ "g12a_ao_saradc_mux" },
+               .parent_hws = (const struct clk_hw *[]) {
+                       &g12a_aoclk_saradc_mux.hw
+               },
                .num_parents = 1,
                .flags = CLK_SET_RATE_PARENT,
        },
@@ -334,7 +360,9 @@ static struct clk_regmap g12a_aoclk_saradc_gate = {
        .hw.init = &(struct clk_init_data){
                .name = "g12a_ao_saradc_gate",
                .ops = &clk_regmap_gate_ops,
-               .parent_names = (const char *[]){ "g12a_ao_saradc_div" },
+               .parent_hws = (const struct clk_hw *[]) {
+                       &g12a_aoclk_saradc_div.hw
+               },
                .num_parents = 1,
                .flags = CLK_SET_RATE_PARENT,
        },
@@ -417,12 +445,6 @@ static const struct clk_hw_onecell_data g12a_aoclk_onecell_data = {
        .num = NR_CLKS,
 };
 
-static const struct meson_aoclk_input g12a_aoclk_inputs[] = {
-       { .name = "xtal",       .required = true  },
-       { .name = "mpeg-clk",   .required = true  },
-       { .name = "ext-32k-0",  .required = false },
-};
-
 static const struct meson_aoclk_data g12a_aoclkc_data = {
        .reset_reg      = AO_RTI_GEN_CNTL_REG0,
        .num_reset      = ARRAY_SIZE(g12a_aoclk_reset),
@@ -430,9 +452,6 @@ static const struct meson_aoclk_data g12a_aoclkc_data = {
        .num_clks       = ARRAY_SIZE(g12a_aoclk_regmap),
        .clks           = g12a_aoclk_regmap,
        .hw_data        = &g12a_aoclk_onecell_data,
-       .inputs         = g12a_aoclk_inputs,
-       .num_inputs     = ARRAY_SIZE(g12a_aoclk_inputs),
-       .input_prefix   = IN_PREFIX,
 };
 
 static const struct of_device_id g12a_aoclkc_match_table[] = {