ARM: dts: enable ahci sata and sata phy for exynos5250
authorYuvaraj Kumar C D <yuvaraj.cd@samsung.com>
Mon, 17 Mar 2014 22:49:14 +0000 (07:49 +0900)
committerKukjin Kim <kgene.kim@samsung.com>
Mon, 17 Mar 2014 22:49:14 +0000 (07:49 +0900)
This patch adds dt entry for ahci sata controller and its
corresponding phy controller.phy node has been added w.r.t
new generic phy framework.

Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Documentation/devicetree/bindings/ata/exynos-sata-phy.txt [deleted file]
Documentation/devicetree/bindings/ata/exynos-sata.txt
Documentation/devicetree/bindings/phy/samsung-phy.txt
arch/arm/boot/dts/exynos5250-arndale.dts
arch/arm/boot/dts/exynos5250-smdk5250.dts
arch/arm/boot/dts/exynos5250.dtsi

diff --git a/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt b/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
deleted file mode 100644 (file)
index 37824fa..0000000
+++ /dev/null
@@ -1,14 +0,0 @@
-* Samsung SATA PHY Controller
-
-SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
-Each SATA PHY controller should have its own node.
-
-Required properties:
-- compatible        : compatible list, contains "samsung,exynos5-sata-phy"
-- reg               : <registers mapping>
-
-Example:
-        sata@ffe07000 {
-                compatible = "samsung,exynos5-sata-phy";
-                reg = <0xffe07000 0x1000>;
-        };
index 0849f1025e3468b0aa6cf945beaa3547d141c15c..b2adb1f3090ebe385e0cb6dbce93c3a249a75297 100644 (file)
@@ -4,14 +4,21 @@ SATA nodes are defined to describe on-chip Serial ATA controllers.
 Each SATA controller should have its own node.
 
 Required properties:
-- compatible        : compatible list, contains "samsung,exynos5-sata"
-- interrupts        : <interrupt mapping for SATA IRQ>
-- reg               : <registers mapping>
-- samsung,sata-freq : <frequency in MHz>
+- compatible           : compatible list, contains "samsung,exynos5-sata"
+- interrupts           : <interrupt mapping for SATA IRQ>
+- reg                  : <registers mapping>
+- samsung,sata-freq    : <frequency in MHz>
+- phys                 : as mentioned in phy-bindings.txt
+- phy-names            : as mentioned in phy-bindings.txt
 
 Example:
-        sata@ffe08000 {
-                compatible = "samsung,exynos5-sata";
-                reg = <0xffe08000 0x1000>;
-                interrupts = <115>;
-        };
+       sata@122f0000 {
+               compatible = "snps,dwc-ahci";
+               samsung,sata-freq = <66>;
+               reg = <0x122f0000 0x1ff>;
+               interrupts = <0 115 0>;
+               clocks = <&clock 277>, <&clock 143>;
+               clock-names = "sata", "sclk_sata";
+               phys = <&sata_phy>;
+               phy-names = "sata-phy";
+       };
index c0fccaa1671ec8da7e403d0a8478860da3e586ba..a937f75d062c9fd05ca086b4a01221dacf492195 100644 (file)
@@ -20,3 +20,39 @@ Required properties:
 - compatible : should be "samsung,exynos5250-dp-video-phy";
 - reg : offset and length of the Display Port PHY register set;
 - #phy-cells : from the generic PHY bindings, must be 0;
+
+Samsung SATA PHY Controller
+---------------------------
+
+SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
+Each SATA PHY controller should have its own node.
+
+Required properties:
+- compatible        : compatible list, contains "samsung,exynos5250-sata-phy"
+- reg : offset and length of the SATA PHY register set;
+- #phy-cells : from the generic phy bindings;
+
+Example:
+       sata_phy: sata-phy@12170000 {
+               compatible = "samsung,exynos5250-sata-phy";
+               reg = <0x12170000 0x1ff>;
+               clocks = <&clock 287>;
+               clock-names = "sata_phyctrl";
+               #phy-cells = <0>;
+               samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
+               samsung,syscon-phandle = <&pmu_syscon>;
+       };
+
+Device-Tree bindings for sataphy i2c client driver
+--------------------------------------------------
+
+Required properties:
+compatible: Should be "samsung,exynos-sataphy-i2c"
+- reg: I2C address of the sataphy i2c device.
+
+Example:
+
+       sata_phy_i2c:sata-phy@38 {
+               compatible = "samsung,exynos-sataphy-i2c";
+               reg = <0x38>;
+       };
index 56c40783c3ebe66faba677db81ccc154ba98defc..9a78d96f8477497aecee6477881a3c5cc2a7d900 100644 (file)
                };
        };
 
+       i2c@121D0000 {
+               status = "okay";
+               samsung,i2c-sda-delay = <100>;
+               samsung,i2c-max-bus-freq = <40000>;
+               samsung,i2c-slave-addr = <0x38>;
+
+               sata_phy_i2c:sata-phy@38 {
+                       compatible = "samsung,exynos-sataphy-i2c";
+                       reg = <0x38>;
+               };
+       };
+
+       sata@122F0000 {
+               status = "okay";
+       };
+
+       sata-phy@12170000 {
+               status = "okay";
+               samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
+       };
+
        mmc_0: mmc@12200000 {
                status = "okay";
                num-slots = <1>;
index 736eb3441bc3ef2a6108a8c8463c54f89cfa39fa..140de8563e94d53eaa914782bb383977d6a04d03 100644 (file)
                samsung,i2c-slave-addr = <0x38>;
                status = "okay";
 
-               sata-phy {
-                       compatible = "samsung,sata-phy";
+               sata_phy_i2c:sata-phy@38 {
+                       compatible = "samsung,exynos-sataphy-i2c";
                        reg = <0x38>;
                };
        };
 
-       sata@122F0000 {
-               samsung,sata-freq = <66>;
-       };
-
        i2c@12C80000 {
                samsung,i2c-sda-delay = <100>;
                samsung,i2c-max-bus-freq = <66000>;
                };
        };
 
+       sata@122F0000 {
+               status = "okay";
+       };
+
+       sata-phy@12170000 {
+               status = "okay";
+               samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
+       };
+
        mmc@12200000 {
                status = "okay";
                num-slots = <1>;
index 9ecffcb1fe912192a194d88d7b605fc00f15926f..fdeed7c29ac9f854c8c7587a8e25fe5897feee33 100644 (file)
@@ -47,6 +47,7 @@
                i2c6 = &i2c_6;
                i2c7 = &i2c_7;
                i2c8 = &i2c_8;
+               i2c9 = &i2c_9;
                pinctrl0 = &pinctrl_0;
                pinctrl1 = &pinctrl_1;
                pinctrl2 = &pinctrl_2;
        };
 
        sata@122F0000 {
-               compatible = "samsung,exynos5-sata-ahci";
+               compatible = "snps,dwc-ahci";
+               samsung,sata-freq = <66>;
                reg = <0x122F0000 0x1ff>;
                interrupts = <0 115 0>;
                clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
                clock-names = "sata", "sclk_sata";
+               phys = <&sata_phy>;
+               phy-names = "sata-phy";
+               status = "disabled";
        };
 
-       sata-phy@12170000 {
-               compatible = "samsung,exynos5-sata-phy";
+       sata_phy: sata-phy@12170000 {
+               compatible = "samsung,exynos5250-sata-phy";
                reg = <0x12170000 0x1ff>;
+               clocks = <&clock 287>;
+               clock-names = "sata_phyctrl";
+               #phy-cells = <0>;
+               samsung,syscon-phandle = <&pmu_system_controller>;
+               status = "disabled";
        };
 
        i2c_0: i2c@12C60000 {
                status = "disabled";
        };
 
-       i2c@121D0000 {
+       i2c_9: i2c@121D0000 {
                 compatible = "samsung,exynos5-sata-phy-i2c";
                 reg = <0x121D0000 0x100>;
                 #address-cells = <1>;