drm/i915/dpio: s/ddi/dpio/ for bxt/glk PHY stuff

Since all of this lives in intel_dpio_phy.c let's rename the
bxt/glk functions to have bxt_dpio_phy_ namespace.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240412175818.29217-7-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index ef2cd34c8e4f7843376ab61b00597c51ea84b8bb..3c3fc53376ce37b628947a176fa8b5d84331994b 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3522,8 +3522,8 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
                 */
                intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
        else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
-               bxt_ddi_phy_set_lane_optim_mask(encoder,
-                                               crtc_state->lane_lat_optim_mask);
+               bxt_dpio_phy_set_lane_optim_mask(encoder,
+                                                crtc_state->lane_lat_optim_mask);
 }
 
 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder)
@@ -3955,7 +3955,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
 
        if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
                pipe_config->lane_lat_optim_mask =
-                       bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
+                       bxt_dpio_phy_get_lane_lat_optim_mask(encoder);
 
        intel_ddi_compute_min_voltage_level(pipe_config);
 
@@ -4232,7 +4232,7 @@ static int intel_ddi_compute_config(struct intel_encoder *encoder,
 
        if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
                pipe_config->lane_lat_optim_mask =
-                       bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
+                       bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
 
        intel_ddi_compute_min_voltage_level(pipe_config);
 
@@ -5084,7 +5084,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
                else
                        encoder->set_signal_levels = icl_mg_phy_set_signal_levels;
        } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
-               encoder->set_signal_levels = bxt_ddi_phy_set_signal_levels;
+               encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels;
        } else {
                encoder->set_signal_levels = hsw_set_signal_levels;
        }

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index a28e61130b8178d676a779b2728d055170b6ce36..e8a6e53fd551106e490a847c66b7750b3ae7ad80 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -905,39 +905,39 @@ static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
                                           struct i915_power_well *power_well)
 {
-       bxt_ddi_phy_init(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
+       bxt_dpio_phy_init(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
 }
 
 static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
                                            struct i915_power_well *power_well)
 {
-       bxt_ddi_phy_uninit(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
+       bxt_dpio_phy_uninit(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
 }
 
 static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv,
                                            struct i915_power_well *power_well)
 {
-       return bxt_ddi_phy_is_enabled(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
+       return bxt_dpio_phy_is_enabled(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
 }
 
-static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
+static void bxt_verify_dpio_phy_power_wells(struct drm_i915_private *dev_priv)
 {
        struct i915_power_well *power_well;
 
        power_well = lookup_power_well(dev_priv, BXT_DISP_PW_DPIO_CMN_A);
        if (intel_power_well_refcount(power_well) > 0)
-               bxt_ddi_phy_verify_state(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
+               bxt_dpio_phy_verify_state(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
 
        power_well = lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
        if (intel_power_well_refcount(power_well) > 0)
-               bxt_ddi_phy_verify_state(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
+               bxt_dpio_phy_verify_state(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
 
        if (IS_GEMINILAKE(dev_priv)) {
                power_well = lookup_power_well(dev_priv,
                                               GLK_DISP_PW_DPIO_CMN_C);
                if (intel_power_well_refcount(power_well) > 0)
-                       bxt_ddi_phy_verify_state(dev_priv,
-                                                i915_power_well_instance(power_well)->bxt.phy);
+                       bxt_dpio_phy_verify_state(dev_priv,
+                                                 i915_power_well_instance(power_well)->bxt.phy);
        }
 }
 
@@ -986,7 +986,7 @@ void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
        gen9_assert_dbuf_enabled(dev_priv);
 
        if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
-               bxt_verify_ddi_phy_power_wells(dev_priv);
+               bxt_verify_dpio_phy_power_wells(dev_priv);
 
        if (DISPLAY_VER(dev_priv) >= 11)
                /*

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 37ff5457d5d15cca4a8f9907df95aa252715483b..c772ba19c5477aaab6ce7858d523d162c9d18b32 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -645,7 +645,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
 
        if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
                pipe_config->lane_lat_optim_mask =
-                       bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
+                       bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
 
        intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
 

diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 377963c0ed5faea750243a0b8c8170d7aeb944d7..77597edb391c21bd4b3cba8c07ff014508ba4618 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -124,9 +124,9 @@
  */
 
 /**
- * struct bxt_ddi_phy_info - Hold info for a broxton DDI phy
+ * struct bxt_dpio_phy_info - Hold info for a broxton DDI phy
  */
-struct bxt_ddi_phy_info {
+struct bxt_dpio_phy_info {
        /**
         * @dual_channel: true if this phy has a second channel.
         */
@@ -162,7 +162,7 @@ struct bxt_ddi_phy_info {
        } channel[2];
 };
 
-static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
+static const struct bxt_dpio_phy_info bxt_dpio_phy_info[] = {
        [DPIO_PHY0] = {
                .dual_channel = true,
                .rcomp_phy = DPIO_PHY1,
@@ -184,7 +184,7 @@ static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
        },
 };
 
-static const struct bxt_ddi_phy_info glk_ddi_phy_info[] = {
+static const struct bxt_dpio_phy_info glk_dpio_phy_info[] = {
        [DPIO_PHY0] = {
                .dual_channel = false,
                .rcomp_phy = DPIO_PHY1,
@@ -217,23 +217,23 @@ static const struct bxt_ddi_phy_info glk_ddi_phy_info[] = {
        },
 };
 
-static const struct bxt_ddi_phy_info *
+static const struct bxt_dpio_phy_info *
 bxt_get_phy_list(struct drm_i915_private *dev_priv, int *count)
 {
        if (IS_GEMINILAKE(dev_priv)) {
-               *count =  ARRAY_SIZE(glk_ddi_phy_info);
-               return glk_ddi_phy_info;
+               *count =  ARRAY_SIZE(glk_dpio_phy_info);
+               return glk_dpio_phy_info;
        } else {
-               *count =  ARRAY_SIZE(bxt_ddi_phy_info);
-               return bxt_ddi_phy_info;
+               *count =  ARRAY_SIZE(bxt_dpio_phy_info);
+               return bxt_dpio_phy_info;
        }
 }
 
-static const struct bxt_ddi_phy_info *
+static const struct bxt_dpio_phy_info *
 bxt_get_phy_info(struct drm_i915_private *dev_priv, enum dpio_phy phy)
 {
        int count;
-       const struct bxt_ddi_phy_info *phy_list =
+       const struct bxt_dpio_phy_info *phy_list =
                bxt_get_phy_list(dev_priv, &count);
 
        return &phy_list[phy];
@@ -242,7 +242,7 @@ bxt_get_phy_info(struct drm_i915_private *dev_priv, enum dpio_phy phy)
 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
                             enum dpio_phy *phy, enum dpio_channel *ch)
 {
-       const struct bxt_ddi_phy_info *phy_info, *phys;
+       const struct bxt_dpio_phy_info *phy_info, *phys;
        int i, count;
 
        phys = bxt_get_phy_list(dev_priv, &count);
@@ -274,10 +274,10 @@ void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
  * Like intel_de_rmw() but reads from a single per-lane register and
  * writes to the group register to write the same value to all the lanes.
  */
-static u32 bxt_ddi_phy_rmw_grp(struct drm_i915_private *i915,
-                              i915_reg_t reg_single,
-                              i915_reg_t reg_group,
-                              u32 clear, u32 set)
+static u32 bxt_dpio_phy_rmw_grp(struct drm_i915_private *i915,
+                               i915_reg_t reg_single,
+                               i915_reg_t reg_group,
+                               u32 clear, u32 set)
 {
        u32 old, val;
 
@@ -288,8 +288,8 @@ static u32 bxt_ddi_phy_rmw_grp(struct drm_i915_private *i915,
        return old;
 }
 
-void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder,
-                                  const struct intel_crtc_state *crtc_state)
+void bxt_dpio_phy_set_signal_levels(struct intel_encoder *encoder,
+                                   const struct intel_crtc_state *crtc_state)
 {
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
        int level = intel_ddi_level(encoder, crtc_state, 0);
@@ -309,40 +309,40 @@ void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder,
         * While we write to the group register to program all lanes at once we
         * can read only lane registers and we pick lanes 0/1 for that.
         */
-       bxt_ddi_phy_rmw_grp(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch),
-                           BXT_PORT_PCS_DW10_GRP(phy, ch),
-                           TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT, 0);
-
-       bxt_ddi_phy_rmw_grp(dev_priv, BXT_PORT_TX_DW2_LN(phy, ch, 0),
-                           BXT_PORT_TX_DW2_GRP(phy, ch),
-                           MARGIN_000_MASK | UNIQ_TRANS_SCALE_MASK,
-                           MARGIN_000(trans->entries[level].bxt.margin) |
-                           UNIQ_TRANS_SCALE(trans->entries[level].bxt.scale));
-
-       bxt_ddi_phy_rmw_grp(dev_priv, BXT_PORT_TX_DW3_LN(phy, ch, 0),
-                           BXT_PORT_TX_DW3_GRP(phy, ch),
-                           SCALE_DCOMP_METHOD,
-                           trans->entries[level].bxt.enable ?
-                           SCALE_DCOMP_METHOD : 0);
+       bxt_dpio_phy_rmw_grp(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch),
+                            BXT_PORT_PCS_DW10_GRP(phy, ch),
+                            TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT, 0);
+
+       bxt_dpio_phy_rmw_grp(dev_priv, BXT_PORT_TX_DW2_LN(phy, ch, 0),
+                            BXT_PORT_TX_DW2_GRP(phy, ch),
+                            MARGIN_000_MASK | UNIQ_TRANS_SCALE_MASK,
+                            MARGIN_000(trans->entries[level].bxt.margin) |
+                            UNIQ_TRANS_SCALE(trans->entries[level].bxt.scale));
+
+       bxt_dpio_phy_rmw_grp(dev_priv, BXT_PORT_TX_DW3_LN(phy, ch, 0),
+                            BXT_PORT_TX_DW3_GRP(phy, ch),
+                            SCALE_DCOMP_METHOD,
+                            trans->entries[level].bxt.enable ?
+                            SCALE_DCOMP_METHOD : 0);
 
        val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN(phy, ch, 0));
        if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
                drm_err(&dev_priv->drm,
                        "Disabled scaling while ouniqetrangenmethod was set");
 
-       bxt_ddi_phy_rmw_grp(dev_priv, BXT_PORT_TX_DW4_LN(phy, ch, 0),
-                           BXT_PORT_TX_DW4_GRP(phy, ch), DE_EMPHASIS_MASK,
-                           DE_EMPHASIS(trans->entries[level].bxt.deemphasis));
+       bxt_dpio_phy_rmw_grp(dev_priv, BXT_PORT_TX_DW4_LN(phy, ch, 0),
+                            BXT_PORT_TX_DW4_GRP(phy, ch), DE_EMPHASIS_MASK,
+                            DE_EMPHASIS(trans->entries[level].bxt.deemphasis));
 
-       bxt_ddi_phy_rmw_grp(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch),
-                           BXT_PORT_PCS_DW10_GRP(phy, ch),
-                           0, TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
+       bxt_dpio_phy_rmw_grp(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch),
+                            BXT_PORT_PCS_DW10_GRP(phy, ch),
+                            0, TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
 }
 
-bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
-                           enum dpio_phy phy)
+bool bxt_dpio_phy_is_enabled(struct drm_i915_private *dev_priv,
+                            enum dpio_phy phy)
 {
-       const struct bxt_ddi_phy_info *phy_info;
+       const struct bxt_dpio_phy_info *phy_info;
 
        phy_info = bxt_get_phy_info(dev_priv, phy);
 
@@ -383,20 +383,20 @@ static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
                        phy);
 }
 
-static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
-                             enum dpio_phy phy)
+static void _bxt_dpio_phy_init(struct drm_i915_private *dev_priv,
+                              enum dpio_phy phy)
 {
-       const struct bxt_ddi_phy_info *phy_info;
+       const struct bxt_dpio_phy_info *phy_info;
        u32 val;
 
        phy_info = bxt_get_phy_info(dev_priv, phy);
 
-       if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
+       if (bxt_dpio_phy_is_enabled(dev_priv, phy)) {
                /* Still read out the GRC value for state verification */
                if (phy_info->rcomp_phy != -1)
                        dev_priv->display.state.bxt_phy_grc = bxt_get_grc(dev_priv, phy);
 
-               if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
+               if (bxt_dpio_phy_verify_state(dev_priv, phy)) {
                        drm_dbg(&dev_priv->drm, "DDI PHY %d already enabled, "
                                "won't reprogram it\n", phy);
                        return;
@@ -464,9 +464,9 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
        intel_de_rmw(dev_priv, BXT_PHY_CTL_FAMILY(phy), 0, COMMON_RESET_DIS);
 }
 
-void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
+void bxt_dpio_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
 {
-       const struct bxt_ddi_phy_info *phy_info;
+       const struct bxt_dpio_phy_info *phy_info;
 
        phy_info = bxt_get_phy_info(dev_priv, phy);
 
@@ -475,9 +475,9 @@ void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
        intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, phy_info->pwron_mask, 0);
 }
 
-void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
+void bxt_dpio_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
 {
-       const struct bxt_ddi_phy_info *phy_info =
+       const struct bxt_dpio_phy_info *phy_info =
                bxt_get_phy_info(dev_priv, phy);
        enum dpio_phy rcomp_phy = phy_info->rcomp_phy;
        bool was_enabled;
@@ -486,19 +486,19 @@ void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
 
        was_enabled = true;
        if (rcomp_phy != -1)
-               was_enabled = bxt_ddi_phy_is_enabled(dev_priv, rcomp_phy);
+               was_enabled = bxt_dpio_phy_is_enabled(dev_priv, rcomp_phy);
 
        /*
         * We need to copy the GRC calibration value from rcomp_phy,
         * so make sure it's powered up.
         */
        if (!was_enabled)
-               _bxt_ddi_phy_init(dev_priv, rcomp_phy);
+               _bxt_dpio_phy_init(dev_priv, rcomp_phy);
 
-       _bxt_ddi_phy_init(dev_priv, phy);
+       _bxt_dpio_phy_init(dev_priv, phy);
 
        if (!was_enabled)
-               bxt_ddi_phy_uninit(dev_priv, rcomp_phy);
+               bxt_dpio_phy_uninit(dev_priv, rcomp_phy);
 }
 
 static bool __printf(6, 7)
@@ -528,10 +528,10 @@ __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
        return false;
 }
 
-bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
-                             enum dpio_phy phy)
+bool bxt_dpio_phy_verify_state(struct drm_i915_private *dev_priv,
+                              enum dpio_phy phy)
 {
-       const struct bxt_ddi_phy_info *phy_info;
+       const struct bxt_dpio_phy_info *phy_info;
        u32 mask;
        bool ok;
 
@@ -541,7 +541,7 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
        __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt,      \
                               ## __VA_ARGS__)
 
-       if (!bxt_ddi_phy_is_enabled(dev_priv, phy))
+       if (!bxt_dpio_phy_is_enabled(dev_priv, phy))
                return false;
 
        ok = true;
@@ -585,7 +585,7 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
 }
 
 u8
-bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count)
+bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count)
 {
        switch (lane_count) {
        case 1:
@@ -601,8 +601,8 @@ bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count)
        }
 }
 
-void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
-                                    u8 lane_lat_optim_mask)
+void bxt_dpio_phy_set_lane_optim_mask(struct intel_encoder *encoder,
+                                     u8 lane_lat_optim_mask)
 {
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
        enum port port = encoder->port;
@@ -624,7 +624,7 @@ void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
 }
 
 u8
-bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
+bxt_dpio_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
 {
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
        enum port port = encoder->port;

diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.h b/drivers/gpu/drm/i915/display/intel_dpio_phy.h
index 9adc4e8c1738160ebc55500f3f3e05272d0050af..226994dcb89b003fca36062c90ca157f4a2d308e 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.h
@@ -29,18 +29,18 @@ enum dpio_phy {
 #ifdef I915
 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
                             enum dpio_phy *phy, enum dpio_channel *ch);
-void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder,
-                                  const struct intel_crtc_state *crtc_state);
-void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
-void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
-bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
-                           enum dpio_phy phy);
-bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
-                             enum dpio_phy phy);
-u8 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count);
-void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
-                                    u8 lane_lat_optim_mask);
-u8 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
+void bxt_dpio_phy_set_signal_levels(struct intel_encoder *encoder,
+                                   const struct intel_crtc_state *crtc_state);
+void bxt_dpio_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
+void bxt_dpio_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
+bool bxt_dpio_phy_is_enabled(struct drm_i915_private *dev_priv,
+                            enum dpio_phy phy);
+bool bxt_dpio_phy_verify_state(struct drm_i915_private *dev_priv,
+                              enum dpio_phy phy);
+u8 bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count);
+void bxt_dpio_phy_set_lane_optim_mask(struct intel_encoder *encoder,
+                                     u8 lane_lat_optim_mask);
+u8 bxt_dpio_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
 
 enum dpio_channel vlv_dig_port_to_channel(struct intel_digital_port *dig_port);
 enum dpio_phy vlv_dig_port_to_phy(struct intel_digital_port *dig_port);
@@ -77,35 +77,35 @@ static inline void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, en
                                           enum dpio_phy *phy, enum dpio_channel *ch)
 {
 }
-static inline void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder,
-                                                const struct intel_crtc_state *crtc_state)
+static inline void bxt_dpio_phy_set_signal_levels(struct intel_encoder *encoder,
+                                                 const struct intel_crtc_state *crtc_state)
 {
 }
-static inline void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
+static inline void bxt_dpio_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
 {
 }
-static inline void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
+static inline void bxt_dpio_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
 {
 }
-static inline bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
-                                         enum dpio_phy phy)
+static inline bool bxt_dpio_phy_is_enabled(struct drm_i915_private *dev_priv,
+                                          enum dpio_phy phy)
 {
        return false;
 }
-static inline bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
-                                           enum dpio_phy phy)
+static inline bool bxt_dpio_phy_verify_state(struct drm_i915_private *dev_priv,
+                                            enum dpio_phy phy)
 {
        return true;
 }
-static inline u8 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count)
+static inline u8 bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count)
 {
        return 0;
 }
-static inline void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
-                                                  u8 lane_lat_optim_mask)
+static inline void bxt_dpio_phy_set_lane_optim_mask(struct intel_encoder *encoder,
+                                                   u8 lane_lat_optim_mask)
 {
 }
-static inline u8 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
+static inline u8 bxt_dpio_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
 {
        return 0;
 }