drm/amd/display: Exclude clkoffset and ips setting for dcn351 specific

Exclude clock offset and IPS setting for dcn351 specific only.

Reviewed-by: Syed Hassan <syed.hassan@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
index 1648226586e22cdc7e35b39f5df21d135a8841ee..56800c573a711e49ab54f6b4515fc1b709704eee 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
@@ -1249,7 +1249,7 @@ void dcn35_clk_mgr_construct(
        clk_mgr->base.dprefclk_ss_divider = 1000;
        clk_mgr->base.ss_on_dprefclk = false;
        clk_mgr->base.dfs_ref_freq_khz = 48000;
-       if (ctx->dce_version == DCN_VERSION_3_5) {
+       if (ctx->dce_version != DCN_VERSION_3_51) {
                clk_mgr->base.regs = &clk_mgr_regs_dcn35;
                clk_mgr->base.clk_mgr_shift = &clk_mgr_shift_dcn35;
                clk_mgr->base.clk_mgr_mask = &clk_mgr_mask_dcn35;
@@ -1401,7 +1401,7 @@ void dcn35_clk_mgr_construct(
 
                        /* Disable dynamic IPS2 in older PMFW (93.12) for Z8 interop. */
                        if (ctx->dc->config.disable_ips == DMUB_IPS_ENABLE &&
-                           ctx->dce_version == DCN_VERSION_3_5 &&
+                           ctx->dce_version != DCN_VERSION_3_51 &&
                            ((clk_mgr->base.smu_ver & 0x00FFFFFF) <= 0x005d0c00))
                                ctx->dc->config.disable_ips = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
                } else {