dt-bindings: clock: exynos7885: Add indices for USB clocks

Exynos7885 SoC has a DWC3 USB Controller with Exynos USB PHY which in
theory supports USB3 SuperSpeed, but is only used as USB2 in all known
devices.

These, of course, need some clocks.
Add indices for these clocks.

Signed-off-by: David Virag <virag.david003@gmail.com>
Link: https://lore.kernel.org/r/20240806121157.479212-4-virag.david003@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/include/dt-bindings/clock/exynos7885.h b/include/dt-bindings/clock/exynos7885.h
index 4ce86810b10d328fc8350eb19af53966d559dd81..cfede84b46b9100112196cfd01e0f90e1f7d3df8 100644 (file)
--- a/include/dt-bindings/clock/exynos7885.h
+++ b/include/dt-bindings/clock/exynos7885.h
@@ -134,16 +134,24 @@
 #define CLK_GOUT_WDT1_PCLK             43
 
 /* CMU_FSYS */
-#define CLK_MOUT_FSYS_BUS_USER         1
-#define CLK_MOUT_FSYS_MMC_CARD_USER    2
-#define CLK_MOUT_FSYS_MMC_EMBD_USER    3
-#define CLK_MOUT_FSYS_MMC_SDIO_USER    4
-#define CLK_GOUT_MMC_CARD_ACLK         5
-#define CLK_GOUT_MMC_CARD_SDCLKIN      6
-#define CLK_GOUT_MMC_EMBD_ACLK         7
-#define CLK_GOUT_MMC_EMBD_SDCLKIN      8
-#define CLK_GOUT_MMC_SDIO_ACLK         9
-#define CLK_GOUT_MMC_SDIO_SDCLKIN      10
-#define CLK_MOUT_FSYS_USB30DRD_USER    11
+#define CLK_MOUT_FSYS_BUS_USER                 1
+#define CLK_MOUT_FSYS_MMC_CARD_USER            2
+#define CLK_MOUT_FSYS_MMC_EMBD_USER            3
+#define CLK_MOUT_FSYS_MMC_SDIO_USER            4
+#define CLK_GOUT_MMC_CARD_ACLK                 5
+#define CLK_GOUT_MMC_CARD_SDCLKIN              6
+#define CLK_GOUT_MMC_EMBD_ACLK                 7
+#define CLK_GOUT_MMC_EMBD_SDCLKIN              8
+#define CLK_GOUT_MMC_SDIO_ACLK                 9
+#define CLK_GOUT_MMC_SDIO_SDCLKIN              10
+#define CLK_MOUT_FSYS_USB30DRD_USER            11
+#define CLK_MOUT_USB_PLL                       12
+#define CLK_FOUT_USB_PLL                       13
+#define CLK_FSYS_USB20PHY_CLKCORE              14
+#define CLK_FSYS_USB30DRD_ACLK_20PHYCTRL       15
+#define CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_0     16
+#define CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_1     17
+#define CLK_FSYS_USB30DRD_BUS_CLK_EARLY                18
+#define CLK_FSYS_USB30DRD_REF_CLK              19
 
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */