riscv: csr: Add CSR encodings for CSR_VXRM/CSR_VXSAT

The VXRM vector csr for xtheadvector has an encoding of 0xa and VXSAT
has an encoding of 0x9.

Co-developed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Tested-by: Yangyu Chen <cyy@cyyself.name>
Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-7-236c22791ef9@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index db1d26dfaef909a70a4b609768fa7827aa1b512e..2155f5afffd630edba5d14edd232c0b55d7007b2 100644 (file)
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -314,9 +314,14 @@
 #define CSR_STIMECMP           0x14D
 #define CSR_STIMECMPH          0x15D
 
-#define VCSR_VXRM_MASK                 3
-#define VCSR_VXRM_SHIFT                        1
-#define VCSR_VXSAT_MASK                        1
+/* xtheadvector symbolic CSR names */
+#define CSR_VXSAT              0x9
+#define CSR_VXRM               0xa
+
+/* xtheadvector CSR masks */
+#define CSR_VXRM_MASK          3
+#define CSR_VXRM_SHIFT         1
+#define CSR_VXSAT_MASK         1
 
 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
 #define CSR_SISELECT           0x150