clk: meson: axg-aoclk: migrate to the new parent description method
authorAlexandre Mergnat <amergnat@baylibre.com>
Thu, 25 Jul 2019 16:41:25 +0000 (18:41 +0200)
committerJerome Brunet <jbrunet@baylibre.com>
Mon, 29 Jul 2019 10:42:48 +0000 (12:42 +0200)
This clock controller use the string comparison method to describe parent
relation between the clocks, which is not optimized.

Migrate to the new way by using .parent_hws where possible (when parent
clocks are localy declared in the controller) and use .parent_data
otherwise.

Remove clk input helper and all bypass clocks (declared in probe function)
which are no longer used since we are able to use device-tree clock name
directly.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
drivers/clk/meson/axg-aoclk.c

index 0086f31288eb8621bc38a0c4a104cd2c664079ed..b488b40c9d0e3f56bd94d0a7145abd475a263d3d 100644 (file)
@@ -18,8 +18,6 @@
 #include "clk-regmap.h"
 #include "clk-dualdiv.h"
 
-#define IN_PREFIX "ao-in-"
-
 /*
  * AO Configuration Clock registers offsets
  * Register offsets from the data sheet must be multiplied by 4.
@@ -42,7 +40,9 @@ static struct clk_regmap axg_aoclk_##_name = {                                \
        .hw.init = &(struct clk_init_data) {                            \
                .name =  "axg_ao_" #_name,                              \
                .ops = &clk_regmap_gate_ops,                            \
-               .parent_names = (const char *[]){ IN_PREFIX "mpeg-clk" }, \
+               .parent_data = &(const struct clk_parent_data) {        \
+                       .fw_name = "mpeg-clk",                          \
+               },                                                      \
                .num_parents = 1,                                       \
                .flags = CLK_IGNORE_UNUSED,                             \
        },                                                              \
@@ -64,7 +64,9 @@ static struct clk_regmap axg_aoclk_cts_oscin = {
        .hw.init = &(struct clk_init_data){
                .name = "cts_oscin",
                .ops = &clk_regmap_gate_ro_ops,
-               .parent_names = (const char *[]){ IN_PREFIX "xtal" },
+               .parent_data = &(const struct clk_parent_data) {
+                       .fw_name = "xtal",
+               },
                .num_parents = 1,
        },
 };
@@ -77,7 +79,9 @@ static struct clk_regmap axg_aoclk_32k_pre = {
        .hw.init = &(struct clk_init_data){
                .name = "axg_ao_32k_pre",
                .ops = &clk_regmap_gate_ops,
-               .parent_names = (const char *[]){ "cts_oscin" },
+               .parent_hws = (const struct clk_hw *[]) {
+                       &axg_aoclk_cts_oscin.hw
+               },
                .num_parents = 1,
        },
 };
@@ -124,7 +128,9 @@ static struct clk_regmap axg_aoclk_32k_div = {
        .hw.init = &(struct clk_init_data){
                .name = "axg_ao_32k_div",
                .ops = &meson_clk_dualdiv_ops,
-               .parent_names = (const char *[]){ "axg_ao_32k_pre" },
+               .parent_hws = (const struct clk_hw *[]) {
+                       &axg_aoclk_32k_pre.hw
+               },
                .num_parents = 1,
        },
 };
@@ -139,8 +145,10 @@ static struct clk_regmap axg_aoclk_32k_sel = {
        .hw.init = &(struct clk_init_data){
                .name = "axg_ao_32k_sel",
                .ops = &clk_regmap_mux_ops,
-               .parent_names = (const char *[]){ "axg_ao_32k_div",
-                                                 "axg_ao_32k_pre" },
+               .parent_hws = (const struct clk_hw *[]) {
+                       &axg_aoclk_32k_div.hw,
+                       &axg_aoclk_32k_pre.hw,
+               },
                .num_parents = 2,
                .flags = CLK_SET_RATE_PARENT,
        },
@@ -154,7 +162,9 @@ static struct clk_regmap axg_aoclk_32k = {
        .hw.init = &(struct clk_init_data){
                .name = "axg_ao_32k",
                .ops = &clk_regmap_gate_ops,
-               .parent_names = (const char *[]){ "axg_ao_32k_sel" },
+               .parent_hws = (const struct clk_hw *[]) {
+                       &axg_aoclk_32k_sel.hw
+               },
                .num_parents = 1,
                .flags = CLK_SET_RATE_PARENT,
        },
@@ -170,8 +180,10 @@ static struct clk_regmap axg_aoclk_cts_rtc_oscin = {
        .hw.init = &(struct clk_init_data){
                .name = "axg_ao_cts_rtc_oscin",
                .ops = &clk_regmap_mux_ops,
-               .parent_names = (const char *[]){ "axg_ao_32k",
-                                                 IN_PREFIX "ext_32k-0" },
+               .parent_data = (const struct clk_parent_data []) {
+                       { .hw = &axg_aoclk_32k.hw },
+                       { .fw_name = "ext_32k-0", },
+               },
                .num_parents = 2,
                .flags = CLK_SET_RATE_PARENT,
        },
@@ -187,8 +199,10 @@ static struct clk_regmap axg_aoclk_clk81 = {
        .hw.init = &(struct clk_init_data){
                .name = "axg_ao_clk81",
                .ops = &clk_regmap_mux_ro_ops,
-               .parent_names = (const char *[]){ IN_PREFIX "mpeg-clk",
-                                                 "axg_ao_cts_rtc_oscin"},
+               .parent_data = (const struct clk_parent_data []) {
+                       { .fw_name = "mpeg-clk", },
+                       { .hw = &axg_aoclk_cts_rtc_oscin.hw },
+               },
                .num_parents = 2,
                .flags = CLK_SET_RATE_PARENT,
        },
@@ -203,8 +217,10 @@ static struct clk_regmap axg_aoclk_saradc_mux = {
        .hw.init = &(struct clk_init_data){
                .name = "axg_ao_saradc_mux",
                .ops = &clk_regmap_mux_ops,
-               .parent_names = (const char *[]){ IN_PREFIX "xtal",
-                                                 "axg_ao_clk81" },
+               .parent_data = (const struct clk_parent_data []) {
+                       { .fw_name = "xtal", },
+                       { .hw = &axg_aoclk_clk81.hw },
+               },
                .num_parents = 2,
        },
 };
@@ -218,7 +234,9 @@ static struct clk_regmap axg_aoclk_saradc_div = {
        .hw.init = &(struct clk_init_data){
                .name = "axg_ao_saradc_div",
                .ops = &clk_regmap_divider_ops,
-               .parent_names = (const char *[]){ "axg_ao_saradc_mux" },
+               .parent_hws = (const struct clk_hw *[]) {
+                       &axg_aoclk_saradc_mux.hw
+               },
                .num_parents = 1,
                .flags = CLK_SET_RATE_PARENT,
        },
@@ -232,7 +250,9 @@ static struct clk_regmap axg_aoclk_saradc_gate = {
        .hw.init = &(struct clk_init_data){
                .name = "axg_ao_saradc_gate",
                .ops = &clk_regmap_gate_ops,
-               .parent_names = (const char *[]){ "axg_ao_saradc_div" },
+               .parent_hws = (const struct clk_hw *[]) {
+                       &axg_aoclk_saradc_div.hw
+               },
                .num_parents = 1,
                .flags = CLK_SET_RATE_PARENT,
        },
@@ -290,12 +310,6 @@ static const struct clk_hw_onecell_data axg_aoclk_onecell_data = {
        .num = NR_CLKS,
 };
 
-static const struct meson_aoclk_input axg_aoclk_inputs[] = {
-       { .name = "xtal",       .required = true  },
-       { .name = "mpeg-clk",   .required = true  },
-       { .name = "ext-32k-0",  .required = false },
-};
-
 static const struct meson_aoclk_data axg_aoclkc_data = {
        .reset_reg      = AO_RTI_GEN_CNTL_REG0,
        .num_reset      = ARRAY_SIZE(axg_aoclk_reset),
@@ -303,9 +317,6 @@ static const struct meson_aoclk_data axg_aoclkc_data = {
        .num_clks       = ARRAY_SIZE(axg_aoclk_regmap),
        .clks           = axg_aoclk_regmap,
        .hw_data        = &axg_aoclk_onecell_data,
-       .inputs         = axg_aoclk_inputs,
-       .num_inputs     = ARRAY_SIZE(axg_aoclk_inputs),
-       .input_prefix   = IN_PREFIX,
 };
 
 static const struct of_device_id axg_aoclkc_match_table[] = {