drm/amd/display: Force enable 3DLUT DMA check for dcn401 in DML

[WHY]
Currently TR0 (trip 0) is not properly budgeting for urgent latency in
DML2.1. This results in overly aggressive prefetch schedules that are
vulnerable to request return jitter, resulting in severe underflow at
the start of the frame.

[HOW]
Forcing 3DLUT DMA check to enable causes urgent latency to be budgeted
properly into the prefetch schedule, avoiding the vulnerability.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
index b0de8920f7e7c5805a46ed5c0e366a853851effb..006667aa961bb28fbd916f636bd2323aaf5ff1ce 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
@@ -816,6 +816,7 @@ static void populate_dml21_plane_config_from_plane_state(struct dml2_context *dm
 
        if (plane_state->mcm_luts.lut3d_data.lut3d_src == DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM) {
                plane->tdlut.setup_for_tdlut = true;
+
                switch (plane_state->mcm_luts.lut3d_data.gpu_mem_params.layout) {
                case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_RGB:
                case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_BGR:
@@ -825,6 +826,7 @@ static void populate_dml21_plane_config_from_plane_state(struct dml2_context *dm
                        plane->tdlut.tdlut_addressing_mode = dml2_tdlut_simple_linear;
                        break;
                }
+
                switch (plane_state->mcm_luts.lut3d_data.gpu_mem_params.size) {
                case DC_CM2_GPU_MEM_SIZE_171717:
                        plane->tdlut.tdlut_width_mode = dml2_tdlut_width_17_cube;
@@ -833,8 +835,8 @@ static void populate_dml21_plane_config_from_plane_state(struct dml2_context *dm
                        //plane->tdlut.tdlut_width_mode = dml2_tdlut_width_flatten; // dml2_tdlut_width_flatten undefined
                        break;
                }
-       } else
-               plane->tdlut.setup_for_tdlut = false;
+       }
+       plane->tdlut.setup_for_tdlut |= dml_ctx->config.force_tdlut_enable;
 
        plane->dynamic_meta_data.enable = false;
        plane->dynamic_meta_data.lines_before_active_required = 0;

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h
index 023325e8f6e22f735ddf0daca0e42921cc750fe9..0f944fcfd5a5bba0a010df53634fae350378bc17 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h
@@ -236,6 +236,7 @@ struct dml2_configuration_options {
 
        bool use_clock_dc_limits;
        bool gpuvm_enable;
+       bool force_tdlut_enable;
        struct dml2_soc_bb *bb_from_dmub;
 };
 

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
index 3e76732ac0dcae650593d21e257ae7e9e3b7eb50..ec676d269d33f59a7dcfe31691ecc7e89c0bf2ab 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
@@ -2099,6 +2099,7 @@ static bool dcn401_resource_construct(
        dc->dml2_options.use_native_soc_bb_construction = true;
        dc->dml2_options.minimize_dispclk_using_odm = true;
        dc->dml2_options.map_dc_pipes_with_callbacks = true;
+       dc->dml2_options.force_tdlut_enable = true;
 
        resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
        dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;