drm/amd/display: add plane CTM driver-specific property
authorMelissa Wen <mwen@igalia.com>
Thu, 16 Nov 2023 19:58:10 +0000 (18:58 -0100)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 14 Dec 2023 20:26:15 +0000 (15:26 -0500)
Plane CTM for pre-blending color space conversion. Only enable
driver-specific plane CTM property on drivers that support both pre- and
post-blending gamut remap matrix, i.e., DCN3+ family. Otherwise it
conflits with DRM CRTC CTM property.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

index 790c08b8262d613eae6151da4478c213f46941f3..2e4911050cc5ec8e34213553c42681f5f87ac2d1 100644 (file)
@@ -364,6 +364,8 @@ struct amdgpu_mode_info {
         * @plane_hdr_mult_property:
         */
        struct drm_property *plane_hdr_mult_property;
+
+       struct drm_property *plane_ctm_property;
        /**
         * @shaper_lut_property: Plane property to set pre-blending shaper LUT
         * that converts color content before 3D LUT. If
index 7706d412d206fa13dd73c05fed7bbf3e90d4d4e9..2d5af83d40b53bd128a85235a44126e8b3f95734 100644 (file)
@@ -784,6 +784,13 @@ struct dm_plane_state {
         * TF is needed for any subsequent linear-to-non-linear transforms.
         */
        __u64 hdr_mult;
+       /**
+        * @ctm:
+        *
+        * Color transformation matrix. The blob (if not NULL) is a &struct
+        * drm_color_ctm_3x4.
+        */
+       struct drm_property_blob *ctm;
        /**
         * @shaper_lut: shaper lookup table blob. The blob (if not NULL) is an
         * array of &struct drm_color_lut.
index 3a1ca13eaee4d849a206822200b8187be08053c3..3eed47736b26b2d4ed9c82783a5c61111f126377 100644 (file)
@@ -240,6 +240,13 @@ amdgpu_dm_create_color_properties(struct amdgpu_device *adev)
                return -ENOMEM;
        adev->mode_info.plane_hdr_mult_property = prop;
 
+       prop = drm_property_create(adev_to_drm(adev),
+                                  DRM_MODE_PROP_BLOB,
+                                  "AMD_PLANE_CTM", 0);
+       if (!prop)
+               return -ENOMEM;
+       adev->mode_info.plane_ctm_property = prop;
+
        prop = drm_property_create(adev_to_drm(adev),
                                   DRM_MODE_PROP_BLOB,
                                   "AMD_PLANE_SHAPER_LUT", 0);
index 35a4732483ba74015a3e7d4fdafc6043263d7757..f10c5154d06ad4943e3ec617bd7a9e863d8e64ac 100644 (file)
@@ -1366,6 +1366,9 @@ static struct drm_plane_state *amdgpu_dm_plane_drm_plane_duplicate_state(struct
        if (old_dm_plane_state->degamma_lut)
                dm_plane_state->degamma_lut =
                        drm_property_blob_get(old_dm_plane_state->degamma_lut);
+       if (old_dm_plane_state->ctm)
+               dm_plane_state->ctm =
+                       drm_property_blob_get(old_dm_plane_state->ctm);
        if (old_dm_plane_state->shaper_lut)
                dm_plane_state->shaper_lut =
                        drm_property_blob_get(old_dm_plane_state->shaper_lut);
@@ -1450,6 +1453,8 @@ static void amdgpu_dm_plane_drm_plane_destroy_state(struct drm_plane *plane,
 
        if (dm_plane_state->degamma_lut)
                drm_property_blob_put(dm_plane_state->degamma_lut);
+       if (dm_plane_state->ctm)
+               drm_property_blob_put(dm_plane_state->ctm);
        if (dm_plane_state->lut3d)
                drm_property_blob_put(dm_plane_state->lut3d);
        if (dm_plane_state->shaper_lut)
@@ -1490,6 +1495,11 @@ dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm,
                                   dm->adev->mode_info.plane_hdr_mult_property,
                                   AMDGPU_HDR_MULT_DEFAULT);
 
+       /* Only enable plane CTM if both DPP and MPC gamut remap is available. */
+       if (dm->dc->caps.color.mpc.gamut_remap)
+               drm_object_attach_property(&plane->base,
+                                          dm->adev->mode_info.plane_ctm_property, 0);
+
        if (dpp_color_caps.hw_3d_lut) {
                drm_object_attach_property(&plane->base,
                                           mode_info.plane_shaper_lut_property, 0);
@@ -1547,6 +1557,14 @@ dm_atomic_plane_set_property(struct drm_plane *plane,
                        dm_plane_state->hdr_mult = val;
                        dm_plane_state->base.color_mgmt_changed = 1;
                }
+       } else if (property == adev->mode_info.plane_ctm_property) {
+               ret = drm_property_replace_blob_from_id(plane->dev,
+                                                       &dm_plane_state->ctm,
+                                                       val,
+                                                       sizeof(struct drm_color_ctm), -1,
+                                                       &replaced);
+               dm_plane_state->base.color_mgmt_changed |= replaced;
+               return ret;
        } else if (property == adev->mode_info.plane_shaper_lut_property) {
                ret = drm_property_replace_blob_from_id(plane->dev,
                                                        &dm_plane_state->shaper_lut,
@@ -1608,6 +1626,9 @@ dm_atomic_plane_get_property(struct drm_plane *plane,
                *val = dm_plane_state->degamma_tf;
        } else if (property == adev->mode_info.plane_hdr_mult_property) {
                *val = dm_plane_state->hdr_mult;
+       } else if (property == adev->mode_info.plane_ctm_property) {
+               *val = (dm_plane_state->ctm) ?
+                       dm_plane_state->ctm->base.id : 0;
        } else  if (property == adev->mode_info.plane_shaper_lut_property) {
                *val = (dm_plane_state->shaper_lut) ?
                        dm_plane_state->shaper_lut->base.id : 0;