drm/amdgpu/vcn: using separate VCN1_AON_SOC offset

VCN1_AON_SOC_ADDRESS_3_0 offset varies on different
VCN generations, the issue in vcn4.0.5 is caused by
a different VCN1_AON_SOC_ADDRESS_3_0 offset.

This patch does the following:

    1. use the same offset for other VCN generations.
    2. use the vcn4.0.5 special offset
    3. update vcn_4_0 and vcn_5_0

Acked-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 5c89ceda9984498b28716944633a9a01cbb2c90d)
Cc: stable@vger.kernel.org

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index cdcdae7f71ce979e90dfe1a421bce3acb04b29ab..83adf81defc7114ce3301ab9e695862c6c4c5d16 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -66,7 +66,6 @@
 #define VCN_ENC_CMD_REG_WAIT           0x0000000c
 
 #define VCN_AON_SOC_ADDRESS_2_0        0x1f800
-#define VCN1_AON_SOC_ADDRESS_3_0       0x48000
 #define VCN_VID_IP_ADDRESS_2_0         0x0
 #define VCN_AON_IP_ADDRESS_2_0         0x30000
 

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 8e7a36f26e9cb3f74be3efd7b593741f85eddf65..b8d835c9e17eda68df9cefd3831ae196d82c19f7 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -39,6 +39,7 @@
 
 #define VCN_VID_SOC_ADDRESS_2_0                                        0x1fa00
 #define VCN1_VID_SOC_ADDRESS_3_0                               0x48200
+#define VCN1_AON_SOC_ADDRESS_3_0                               0x48000
 
 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET                       0x1fd
 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET                   0x503

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index d716510b8dd686c5930dd3d2e704d7f363f6626f..3eec1b8feaeea4d358f63435b5676079417a1a34 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -39,6 +39,7 @@
 
 #define VCN_VID_SOC_ADDRESS_2_0                                        0x1fa00
 #define VCN1_VID_SOC_ADDRESS_3_0                               0x48200
+#define VCN1_AON_SOC_ADDRESS_3_0                               0x48000
 
 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET                       0x27
 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET                   0x0f

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 22ae1939476f0a33948be59d3f5214d6baceca96..0b19f0ab4480da979c3c0eaffe2797397d95f900 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -40,6 +40,7 @@
 
 #define VCN_VID_SOC_ADDRESS_2_0                                        0x1fa00
 #define VCN1_VID_SOC_ADDRESS_3_0                               0x48200
+#define VCN1_AON_SOC_ADDRESS_3_0                               0x48000
 
 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET                       0x27
 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET                   0x0f

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index c6f6392c1c20b60c6aa1160a60d1567d36149ef1..1f777c125b00de713fd18fa6c60822506b5f018e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -46,6 +46,7 @@
 
 #define VCN_VID_SOC_ADDRESS_2_0                                                        0x1fb00
 #define VCN1_VID_SOC_ADDRESS_3_0                                               0x48300
+#define VCN1_AON_SOC_ADDRESS_3_0                                               0x48000
 
 #define VCN_HARVEST_MMSCH                                                              0
 
@@ -614,7 +615,8 @@ static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst,
 
        /* VCN global tiling registers */
        WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
-               VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
+                       VCN, inst_idx, regUVD_GFX10_ADDR_CONFIG),
+                       adev->gfx.config.gb_addr_config, 0, indirect);
 }
 
 /**

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index 3e176b4b7c69dd31b7d047aab43d5c4fb020fdb0..012f6ea928ec66aa02cc948dfdfa729b7f33aa2e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -45,6 +45,7 @@
 
 #define VCN_VID_SOC_ADDRESS_2_0                0x1fb00
 #define VCN1_VID_SOC_ADDRESS_3_0       0x48300
+#define VCN1_AON_SOC_ADDRESS_3_0       0x48000
 
 static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = {
        SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index ba603b2246e2ee12c3e0d27300588066139f36c3..a1171e6152ed2da64eb240a7650a1b8e97e97c65 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -46,6 +46,7 @@
 
 #define VCN_VID_SOC_ADDRESS_2_0                                                0x1fb00
 #define VCN1_VID_SOC_ADDRESS_3_0                                       (0x48300 + 0x38000)
+#define VCN1_AON_SOC_ADDRESS_3_0                                       (0x48000 + 0x38000)
 
 #define VCN_HARVEST_MMSCH                                                      0
 

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index d99d05f42f1d93a6923f021729929642b70eb0fa..b90da3d3e1406bf4e049e2c56a89347a9ed1aac1 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -533,7 +533,8 @@ static void vcn_v5_0_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst,
 
        /* VCN global tiling registers */
        WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(
-               VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
+               VCN, inst_idx, regUVD_GFX10_ADDR_CONFIG),
+               adev->gfx.config.gb_addr_config, 0, indirect);
 
        return;
 }