drm/amdgpu: add support for GC IP version 11.5.3
authorTim Huang <tim.huang@amd.com>
Thu, 5 Dec 2024 08:24:44 +0000 (16:24 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 13 Feb 2025 02:02:55 +0000 (21:02 -0500)
This initializes GC IP version 11.5.3.

Signed-off-by: Tim Huang <tim.huang@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
drivers/gpu/drm/amd/amdgpu/soc21.c
drivers/gpu/drm/amd/amdkfd/kfd_crat.c
drivers/gpu/drm/amd/amdkfd/kfd_device.c

index 949d74eff29465b12df862d8c1e00c09a9990d96..ea31418a479b5cf45f7d133d261d675bdbe0682a 100644 (file)
@@ -1864,6 +1864,7 @@ static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)
        case IP_VERSION(11, 5, 0):
        case IP_VERSION(11, 5, 1):
        case IP_VERSION(11, 5, 2):
+       case IP_VERSION(11, 5, 3):
                amdgpu_device_ip_block_add(adev, &soc21_common_ip_block);
                break;
        case IP_VERSION(12, 0, 0):
@@ -1919,6 +1920,7 @@ static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev)
        case IP_VERSION(11, 5, 0):
        case IP_VERSION(11, 5, 1):
        case IP_VERSION(11, 5, 2):
+       case IP_VERSION(11, 5, 3):
                amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block);
                break;
        case IP_VERSION(12, 0, 0):
@@ -2215,6 +2217,7 @@ static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)
        case IP_VERSION(11, 5, 0):
        case IP_VERSION(11, 5, 1):
        case IP_VERSION(11, 5, 2):
+       case IP_VERSION(11, 5, 3):
                amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block);
                break;
        case IP_VERSION(12, 0, 0):
@@ -2393,6 +2396,7 @@ static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
        case IP_VERSION(11, 5, 0):
        case IP_VERSION(11, 5, 1):
        case IP_VERSION(11, 5, 2):
+       case IP_VERSION(11, 5, 3):
                amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block);
                adev->enable_mes = true;
                adev->enable_mes_kiq = true;
@@ -2708,6 +2712,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
        case IP_VERSION(11, 5, 0):
        case IP_VERSION(11, 5, 1):
        case IP_VERSION(11, 5, 2):
+       case IP_VERSION(11, 5, 3):
                adev->family = AMDGPU_FAMILY_GC_11_5_0;
                break;
        case IP_VERSION(12, 0, 0):
@@ -2733,6 +2738,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
        case IP_VERSION(11, 5, 0):
        case IP_VERSION(11, 5, 1):
        case IP_VERSION(11, 5, 2):
+       case IP_VERSION(11, 5, 3):
                adev->flags |= AMD_IS_APU;
                break;
        default:
index 1c19a65e655337d4cf9de5e78797aaab614587f8..2667a183e9c5f806fd4e0a0367c50876923cff65 100644 (file)
@@ -851,6 +851,7 @@ void amdgpu_gmc_tmz_set(struct amdgpu_device *adev)
        case IP_VERSION(11, 5, 0):
        case IP_VERSION(11, 5, 1):
        case IP_VERSION(11, 5, 2):
+       case IP_VERSION(11, 5, 3):
                /* Don't enable it by default yet.
                 */
                if (amdgpu_tmz < 1) {
index 56c06b72a70ac56b249ae15c77e9d2b5f302aa0e..87ed78aa3703dbe52e2f3f29ea092e291b3ade7a 100644 (file)
@@ -98,6 +98,10 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_2_pfp.bin");
 MODULE_FIRMWARE("amdgpu/gc_11_5_2_me.bin");
 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mec.bin");
 MODULE_FIRMWARE("amdgpu/gc_11_5_2_rlc.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_5_3_pfp.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_5_3_me.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_5_3_mec.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_5_3_rlc.bin");
 
 static const struct amdgpu_hwip_reg_entry gc_reg_list_11_0[] = {
        SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),
@@ -1087,6 +1091,7 @@ static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev)
        case IP_VERSION(11, 5, 0):
        case IP_VERSION(11, 5, 1):
        case IP_VERSION(11, 5, 2):
+       case IP_VERSION(11, 5, 3):
                adev->gfx.config.max_hw_contexts = 8;
                adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
                adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
@@ -1568,6 +1573,7 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
        case IP_VERSION(11, 5, 0):
        case IP_VERSION(11, 5, 1):
        case IP_VERSION(11, 5, 2):
+       case IP_VERSION(11, 5, 3):
                adev->gfx.me.num_me = 1;
                adev->gfx.me.num_pipe_per_me = 1;
                adev->gfx.me.num_queue_per_pipe = 1;
@@ -2926,7 +2932,8 @@ static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
                            IP_VERSION(11, 0, 4) ||
                    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 0) ||
                    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 1) ||
-                   amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 2))
+                   amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 2) ||
+                   amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 3))
                        bootload_status = RREG32_SOC15(GC, 0,
                                        regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1);
                else
@@ -5448,6 +5455,7 @@ static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable)
                case IP_VERSION(11, 5, 0):
                case IP_VERSION(11, 5, 1):
                case IP_VERSION(11, 5, 2):
+               case IP_VERSION(11, 5, 3):
                        WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1);
                        break;
                default:
@@ -5485,6 +5493,7 @@ static int gfx_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
        case IP_VERSION(11, 5, 0):
        case IP_VERSION(11, 5, 1):
        case IP_VERSION(11, 5, 2):
+       case IP_VERSION(11, 5, 3):
                if (!enable)
                        amdgpu_gfx_off_ctrl(adev, false);
 
@@ -5518,6 +5527,7 @@ static int gfx_v11_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
        case IP_VERSION(11, 5, 0):
        case IP_VERSION(11, 5, 1):
        case IP_VERSION(11, 5, 2):
+       case IP_VERSION(11, 5, 3):
                gfx_v11_0_update_gfx_clock_gating(adev,
                                state ==  AMD_CG_STATE_GATE);
                break;
index 72751ab4c766ec2e1f8de0d2d98d5c1e6ba62b51..5047b80ab60c2faffa72d312869a9678f9b55ddb 100644 (file)
@@ -596,6 +596,7 @@ static void gmc_v11_0_set_gfxhub_funcs(struct amdgpu_device *adev)
        case IP_VERSION(11, 5, 0):
        case IP_VERSION(11, 5, 1):
        case IP_VERSION(11, 5, 2):
+       case IP_VERSION(11, 5, 3):
                adev->gfxhub.funcs = &gfxhub_v11_5_0_funcs;
                break;
        default:
@@ -759,6 +760,7 @@ static int gmc_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
        case IP_VERSION(11, 5, 0):
        case IP_VERSION(11, 5, 1):
        case IP_VERSION(11, 5, 2):
+       case IP_VERSION(11, 5, 3):
                set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
                set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);
                /*
index aeca5c08ea2f2bd820149391df37bffccdfb4829..cfa91d709d49963dffc4684ac3ce3dcbf5e60596 100644 (file)
@@ -39,6 +39,7 @@ MODULE_FIRMWARE("amdgpu/gc_11_0_4_imu.bin");
 MODULE_FIRMWARE("amdgpu/gc_11_5_0_imu.bin");
 MODULE_FIRMWARE("amdgpu/gc_11_5_1_imu.bin");
 MODULE_FIRMWARE("amdgpu/gc_11_5_2_imu.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_5_3_imu.bin");
 
 static int imu_v11_0_init_microcode(struct amdgpu_device *adev)
 {
index 65f389eb65e5fa4e2d2319f312ab1ee4e83a6d66..5c4aee86cf76d99456a9d4792d36eb13ca5c8324 100644 (file)
@@ -54,6 +54,8 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes_2.bin");
 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes1.bin");
 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes_2.bin");
 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes1.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes_2.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes1.bin");
 
 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block);
 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block);
index 62ad67d0b598f576ff5af435675622745eb36af9..ba889a85cdc5160cc66cc0f65cde504e1d16e7eb 100644 (file)
@@ -781,6 +781,28 @@ static int soc21_common_early_init(struct amdgpu_ip_block *ip_block)
                        AMD_PG_SUPPORT_GFX_PG;
                adev->external_rev_id = adev->rev_id + 0x40;
                break;
+       case IP_VERSION(11, 5, 3):
+               adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG |
+                       AMD_CG_SUPPORT_GFX_CGLS |
+                       AMD_CG_SUPPORT_GFX_MGCG |
+                       AMD_CG_SUPPORT_GFX_FGCG |
+                       AMD_CG_SUPPORT_REPEATER_FGCG |
+                       AMD_CG_SUPPORT_GFX_PERF_CLK |
+                       AMD_CG_SUPPORT_GFX_3D_CGCG |
+                       AMD_CG_SUPPORT_GFX_3D_CGLS |
+                       AMD_CG_SUPPORT_MC_MGCG |
+                       AMD_CG_SUPPORT_MC_LS |
+                       AMD_CG_SUPPORT_HDP_LS |
+                       AMD_CG_SUPPORT_HDP_DS |
+                       AMD_CG_SUPPORT_HDP_SD |
+                       AMD_CG_SUPPORT_ATHUB_MGCG |
+                       AMD_CG_SUPPORT_ATHUB_LS |
+                       AMD_CG_SUPPORT_IH_CG |
+                       AMD_CG_SUPPORT_BIF_MGCG |
+                       AMD_CG_SUPPORT_BIF_LS;
+               adev->pg_flags = AMD_PG_SUPPORT_GFX_PG;
+               adev->external_rev_id = adev->rev_id + 0x50;
+               break;
        default:
                /* FIXME: not supported yet */
                return -EINVAL;
index 693469c18c609b196034a82d324b510c54da9e14..70b3ae0b74febac359878578c10a9a44b8a03d6b 100644 (file)
@@ -1704,6 +1704,7 @@ int kfd_get_gpu_cache_info(struct kfd_node *kdev, struct kfd_gpu_cache_info **pc
                case IP_VERSION(11, 5, 0):
                case IP_VERSION(11, 5, 1):
                case IP_VERSION(11, 5, 2):
+               case IP_VERSION(11, 5, 3):
                        /* Cacheline size not available in IP discovery for gc11.
                         * kfd_fill_gpu_cache_info_from_gfx_config to hard code it
                         */
index a29374c8640565a3549cc9dc4b130b9ede5d893b..b5d70d8032898f0b66901ade5e72bf391e013c87 100644 (file)
@@ -180,6 +180,7 @@ static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd)
        case IP_VERSION(11, 5, 0):
        case IP_VERSION(11, 5, 1):
        case IP_VERSION(11, 5, 2):
+       case IP_VERSION(11, 5, 3):
                kfd->device_info.event_interrupt_class = &event_interrupt_class_v11;
                break;
        case IP_VERSION(12, 0, 0):
@@ -454,6 +455,10 @@ struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)
                        gfx_target_version = 110502;
                        f2g = &gfx_v11_kfd2kgd;
                        break;
+               case IP_VERSION(11, 5, 3):
+                       gfx_target_version = 110503;
+                       f2g = &gfx_v11_kfd2kgd;
+                       break;
                case IP_VERSION(12, 0, 0):
                        gfx_target_version = 120000;
                        f2g = &gfx_v12_kfd2kgd;