drm/xe/pf: Add runtime registers for graphics gen >= 30

Add missing runtime registers for graphics versions of 3000 or higher.
This is required for Xe3 where additionally we have
MIRROR_L3BANK_ENABLE register.

Signed-off-by: Jakub Kolakowski <jakub1.kolakowski@intel.com>
Suggested-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
Cc: Adam Miszczak <adam.miszczak@linux.intel.com>
Cc: Jakub Kolakowski <jakub1.kolakowski@intel.com>
Cc: Lukasz Laguna <lukasz.laguna@intel.com>
Cc: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Piotr Piorkowski <piotr.piorkowski@intel.com>
Cc: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
Reviewed-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
Tested-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250128110300.2840596-2-jakub1.kolakowski@intel.com

diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c b/drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c
index 924e75b94aec0862c2ab1dd98806f225c3753d1e..6b5f849a072231b98b42a888d96be1dff0bbb933 100644 (file)
--- a/drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c
+++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c
@@ -176,11 +176,32 @@ static const struct xe_reg ver_2000_runtime_regs[] = {
        TIMESTAMP_OVERRIDE,             /* _MMIO(0x44074) */
 };
 
+static const struct xe_reg ver_3000_runtime_regs[] = {
+       RPM_CONFIG0,                    /* _MMIO(0x0d00) */
+       XEHP_FUSE4,                     /* _MMIO(0x9114) */
+       MIRROR_FUSE3,                   /* _MMIO(0x9118) */
+       MIRROR_FUSE1,                   /* _MMIO(0x911c) */
+       MIRROR_L3BANK_ENABLE,           /* _MMIO(0x9130) */
+       XELP_EU_ENABLE,                 /* _MMIO(0x9134) */
+       XELP_GT_GEOMETRY_DSS_ENABLE,    /* _MMIO(0x913c) */
+       GT_VEBOX_VDBOX_DISABLE,         /* _MMIO(0x9140) */
+       XEHP_GT_COMPUTE_DSS_ENABLE,     /* _MMIO(0x9144) */
+       XEHPC_GT_COMPUTE_DSS_ENABLE_EXT,/* _MMIO(0x9148) */
+       XE2_GT_COMPUTE_DSS_2,           /* _MMIO(0x914c) */
+       XE2_GT_GEOMETRY_DSS_1,          /* _MMIO(0x9150) */
+       XE2_GT_GEOMETRY_DSS_2,          /* _MMIO(0x9154) */
+       CTC_MODE,                       /* _MMIO(0xa26c) */
+       HUC_KERNEL_LOAD_INFO,           /* _MMIO(0xc1dc) */
+};
+
 static const struct xe_reg *pick_runtime_regs(struct xe_device *xe, unsigned int *count)
 {
        const struct xe_reg *regs;
 
-       if (GRAPHICS_VERx100(xe) >= 2000) {
+       if (GRAPHICS_VERx100(xe) >= 3000) {
+               *count = ARRAY_SIZE(ver_3000_runtime_regs);
+               regs = ver_3000_runtime_regs;
+       } else if (GRAPHICS_VERx100(xe) >= 2000) {
                *count = ARRAY_SIZE(ver_2000_runtime_regs);
                regs = ver_2000_runtime_regs;
        } else if (GRAPHICS_VERx100(xe) >= 1270) {