drm/amdgpu: Move memory partition query to gmc
authorLijo Lazar <lijo.lazar@amd.com>
Tue, 31 Jan 2023 07:09:49 +0000 (12:39 +0530)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 9 Jun 2023 13:56:50 +0000 (09:56 -0400)
GMC block handles memory related information, it makes more sense to
keep memory partition functions in gmc block.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

index 1487ecac27054dcb8a39b8cdbbd02a7092152242..2f7a101593e78a3c8a4ba1edbaf9902c07d3dffe 100644 (file)
@@ -1204,24 +1204,6 @@ static ssize_t amdgpu_gfx_get_current_compute_partition(struct device *dev,
        return sysfs_emit(buf, "%s\n", partition_mode);
 }
 
-static ssize_t amdgpu_gfx_get_current_memory_partition(struct device *dev,
-                                               struct device_attribute *addr,
-                                               char *buf)
-{
-       struct drm_device *ddev = dev_get_drvdata(dev);
-       struct amdgpu_device *adev = drm_to_adev(ddev);
-       enum amdgpu_memory_partition mode;
-       static const char *partition_modes[] = {
-               "UNKNOWN", "NPS1", "NPS2", "NPS4", "NPS8"
-       };
-       BUILD_BUG_ON(ARRAY_SIZE(partition_modes) <= AMDGPU_NPS8_PARTITION_MODE);
-
-       mode = min((int)adev->gfx.funcs->query_mem_partition_mode(adev),
-               AMDGPU_NPS8_PARTITION_MODE);
-
-       return sysfs_emit(buf, "%s\n", partition_modes[mode]);
-}
-
 static ssize_t amdgpu_gfx_set_compute_partition(struct device *dev,
                                                struct device_attribute *addr,
                                                const char *buf, size_t count)
@@ -1305,9 +1287,6 @@ static DEVICE_ATTR(current_compute_partition, S_IRUGO | S_IWUSR,
 static DEVICE_ATTR(available_compute_partition, S_IRUGO,
                   amdgpu_gfx_get_available_compute_partition, NULL);
 
-static DEVICE_ATTR(current_memory_partition, S_IRUGO,
-                  amdgpu_gfx_get_current_memory_partition, NULL);
-
 int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev)
 {
        int r;
@@ -1317,19 +1296,12 @@ int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev)
                return r;
 
        r = device_create_file(adev->dev, &dev_attr_available_compute_partition);
-       if (r)
-               return r;
 
-       r = device_create_file(adev->dev, &dev_attr_current_memory_partition);
-       if (r)
-               return r;
-
-       return 0;
+       return r;
 }
 
 void amdgpu_gfx_sysfs_fini(struct amdgpu_device *adev)
 {
        device_remove_file(adev->dev, &dev_attr_current_compute_partition);
        device_remove_file(adev->dev, &dev_attr_available_compute_partition);
-       device_remove_file(adev->dev, &dev_attr_current_memory_partition);
 }
index 81b4c7e684af2962e6085df0befa59eb7f468067..728977f8afe7a8fb529ea9130521929376f4cdc3 100644 (file)
@@ -71,14 +71,6 @@ enum amdgpu_pkg_type {
        AMDGPU_PKG_TYPE_UNKNOWN,
 };
 
-enum amdgpu_memory_partition {
-       UNKNOWN_MEMORY_PARTITION_MODE = 0,
-       AMDGPU_NPS1_PARTITION_MODE = 1,
-       AMDGPU_NPS2_PARTITION_MODE = 2,
-       AMDGPU_NPS4_PARTITION_MODE = 3,
-       AMDGPU_NPS8_PARTITION_MODE = 4,
-};
-
 struct amdgpu_mec {
        struct amdgpu_bo        *hpd_eop_obj;
        u64                     hpd_eop_gpu_addr;
@@ -276,8 +268,6 @@ struct amdgpu_gfx_funcs {
                                   struct amdgpu_gfx_shadow_info *shadow_info);
        enum amdgpu_gfx_partition
                        (*query_partition_mode)(struct amdgpu_device *adev);
-       enum amdgpu_memory_partition
-                       (*query_mem_partition_mode)(struct amdgpu_device *adev);
        int (*switch_partition_mode)(struct amdgpu_device *adev,
                                     int num_xccs_per_xcp);
        int (*ih_node_to_logical_xcc)(struct amdgpu_device *adev, int ih_node);
@@ -414,7 +404,6 @@ struct amdgpu_gfx {
        bool                            cp_gfx_shadow; /* for gfx11 */
 
        uint16_t                        xcc_mask;
-       enum amdgpu_memory_partition    mem_partition_mode;
        uint32_t                        num_xcc_per_xcp;
        struct mutex                    partition_mutex;
 };
index b8825a0670a4165596e645df1800ee00c1509f7a..d12625f1de5ab9a6bddbc8e0176e22cbfcd06fe7 100644 (file)
@@ -891,3 +891,47 @@ int amdgpu_gmc_vram_checking(struct amdgpu_device *adev)
 
        return 0;
 }
+
+static ssize_t current_memory_partition_show(
+       struct device *dev, struct device_attribute *addr, char *buf)
+{
+       struct drm_device *ddev = dev_get_drvdata(dev);
+       struct amdgpu_device *adev = drm_to_adev(ddev);
+       enum amdgpu_memory_partition mode;
+
+       mode = adev->gmc.gmc_funcs->query_mem_partition_mode(adev);
+       switch (mode) {
+       case AMDGPU_NPS1_PARTITION_MODE:
+               return sysfs_emit(buf, "NPS1\n");
+       case AMDGPU_NPS2_PARTITION_MODE:
+               return sysfs_emit(buf, "NPS2\n");
+       case AMDGPU_NPS3_PARTITION_MODE:
+               return sysfs_emit(buf, "NPS3\n");
+       case AMDGPU_NPS4_PARTITION_MODE:
+               return sysfs_emit(buf, "NPS4\n");
+       case AMDGPU_NPS6_PARTITION_MODE:
+               return sysfs_emit(buf, "NPS6\n");
+       case AMDGPU_NPS8_PARTITION_MODE:
+               return sysfs_emit(buf, "NPS8\n");
+       default:
+               return sysfs_emit(buf, "UNKNOWN\n");
+       }
+
+       return sysfs_emit(buf, "UNKNOWN\n");
+}
+
+static DEVICE_ATTR_RO(current_memory_partition);
+
+int amdgpu_gmc_sysfs_init(struct amdgpu_device *adev)
+{
+       if (!adev->gmc.gmc_funcs->query_mem_partition_mode)
+               return 0;
+
+       return device_create_file(adev->dev,
+                                 &dev_attr_current_memory_partition);
+}
+
+void amdgpu_gmc_sysfs_fini(struct amdgpu_device *adev)
+{
+       device_remove_file(adev->dev, &dev_attr_current_memory_partition);
+}
index e408abfc2daf3d8029bb82663d97bebe0830ca53..2bd3b9665ebfdddad1dbfc86c42e475802ff6760 100644 (file)
 
 struct firmware;
 
+enum amdgpu_memory_partition {
+       UNKNOWN_MEMORY_PARTITION_MODE = 0,
+       AMDGPU_NPS1_PARTITION_MODE = 1,
+       AMDGPU_NPS2_PARTITION_MODE = 2,
+       AMDGPU_NPS3_PARTITION_MODE = 3,
+       AMDGPU_NPS4_PARTITION_MODE = 4,
+       AMDGPU_NPS6_PARTITION_MODE = 6,
+       AMDGPU_NPS8_PARTITION_MODE = 8,
+};
+
 /*
  * GMC page fault information
  */
@@ -140,6 +150,9 @@ struct amdgpu_gmc_funcs {
                           uint64_t *flags);
        /* get the amount of memory used by the vbios for pre-OS console */
        unsigned int (*get_vbios_fb_size)(struct amdgpu_device *adev);
+
+       enum amdgpu_memory_partition (*query_mem_partition_mode)(
+               struct amdgpu_device *adev);
 };
 
 struct amdgpu_xgmi_ras {
@@ -375,4 +388,7 @@ uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr);
 uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo);
 uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo);
 int amdgpu_gmc_vram_checking(struct amdgpu_device *adev);
+int amdgpu_gmc_sysfs_init(struct amdgpu_device *adev);
+void amdgpu_gmc_sysfs_fini(struct amdgpu_device *adev);
+
 #endif
index 69867294117ead00d157c8dc71037f1961c404df..81ab3cd2f229661e94702bec8c643050cd37a2ef 100644 (file)
@@ -607,16 +607,7 @@ static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev,
 {
        soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id));
 }
-static enum amdgpu_memory_partition
-gfx_v9_4_3_query_memory_partition(struct amdgpu_device *adev)
-{
-       enum amdgpu_memory_partition mode = UNKNOWN_MEMORY_PARTITION_MODE;
-
-       if (adev->nbio.funcs->get_memory_partition_mode)
-               mode = adev->nbio.funcs->get_memory_partition_mode(adev);
 
-       return mode;
-}
 
 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev,
                                                int num_xccs_per_xcp)
@@ -660,7 +651,6 @@ static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = {
        .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs,
        .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q,
        .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition,
-       .query_mem_partition_mode = &gfx_v9_4_3_query_memory_partition,
        .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst,
 };
 
index 245de27c7540296a15bab3455d942e7e6597049e..db157a31a780e39de1d35c0f39ba779071bcdfd3 100644 (file)
@@ -1330,6 +1330,17 @@ static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
        return size;
 }
 
+static enum amdgpu_memory_partition
+gmc_v9_0_query_memory_partition(struct amdgpu_device *adev)
+{
+       enum amdgpu_memory_partition mode = UNKNOWN_MEMORY_PARTITION_MODE;
+
+       if (adev->nbio.funcs->get_memory_partition_mode)
+               mode = adev->nbio.funcs->get_memory_partition_mode(adev);
+
+       return mode;
+}
+
 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
        .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
        .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid,
@@ -1339,6 +1350,7 @@ static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
        .get_vm_pde = gmc_v9_0_get_vm_pde,
        .get_vm_pte = gmc_v9_0_get_vm_pte,
        .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size,
+       .query_mem_partition_mode = &gmc_v9_0_query_memory_partition,
 };
 
 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
@@ -1901,6 +1913,9 @@ static int gmc_v9_0_sw_init(void *handle)
        if (r)
                return r;
 
+       if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3))
+               amdgpu_gmc_sysfs_init(adev);
+
        return 0;
 }
 
@@ -1908,6 +1923,9 @@ static int gmc_v9_0_sw_fini(void *handle)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+       if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3))
+               amdgpu_gmc_sysfs_fini(adev);
+
        amdgpu_gmc_ras_fini(adev);
        amdgpu_gem_force_release(adev);
        amdgpu_vm_manager_fini(adev);