clk: renesas: r9a09g057: Add clock and reset entries for GE3D

Add PLLGPU along with the necessary clock and reset entries for GE3D.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250309211402.80886-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
index 031f332893a1974d75a9d518f84d3665644c407e..da20dbaead1f6e7b0d95aeb06bd948dc2e9836cf 100644 (file)
--- a/drivers/clk/renesas/r9a09g057-cpg.c
+++ b/drivers/clk/renesas/r9a09g057-cpg.c
@@ -29,6 +29,7 @@ enum clk_ids {
        CLK_PLLDTY,
        CLK_PLLCA55,
        CLK_PLLVDO,
+       CLK_PLLGPU,
 
        /* Internal Core Clocks */
        CLK_PLLCM33_DIV4,
@@ -47,6 +48,7 @@ enum clk_ids {
        CLK_PLLVDO_CRU1,
        CLK_PLLVDO_CRU2,
        CLK_PLLVDO_CRU3,
+       CLK_PLLGPU_GEAR,
 
        /* Module Clocks */
        MOD_CLK_BASE,
@@ -87,6 +89,7 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
        DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
        DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
        DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
+       DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU),
 
        /* Internal Core Clocks */
        DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4),
@@ -110,6 +113,8 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
        DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4),
        DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4),
 
+       DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64),
+
        /* Core Clocks */
        DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
        DEF_DDIV("ca55_0_coreclk0", R9A09G057_CA55_0_CORE_CLK0, CLK_PLLCA55,
@@ -238,6 +243,12 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
                                                BUS_MSTOP(9, BIT(7))),
        DEF_MOD("cru_3_pclk",                   CLK_PLLDTY_DIV16, 13, 13, 6, 29,
                                                BUS_MSTOP(9, BIT(7))),
+       DEF_MOD("gpu_0_clk",                    CLK_PLLGPU_GEAR, 15, 0, 7, 16,
+                                               BUS_MSTOP(3, BIT(4))),
+       DEF_MOD("gpu_0_axi_clk",                CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
+                                               BUS_MSTOP(3, BIT(4))),
+       DEF_MOD("gpu_0_ace_clk",                CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,
+                                               BUS_MSTOP(3, BIT(4))),
 };
 
 static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
@@ -287,6 +298,9 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
        DEF_RST(12, 14, 5, 31),         /* CRU_3_PRESETN */
        DEF_RST(12, 15, 6, 0),          /* CRU_3_ARESETN */
        DEF_RST(13, 0, 6, 1),           /* CRU_3_S_RESETN */
+       DEF_RST(13, 13, 6, 14),         /* GPU_0_RESETN */
+       DEF_RST(13, 14, 6, 15),         /* GPU_0_AXI_RESETN */
+       DEF_RST(13, 15, 6, 16),         /* GPU_0_ACE_RESETN */
 };
 
 const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = {

diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index d52f5416e371f7f83606b431790438b0d923f804..59f72fbed1337f84ec1c58049a2e6337929cd8be 100644 (file)
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -28,6 +28,7 @@ struct pll {
        })
 
 #define PLLCA55                PLL_PACK(0x60, 1)
+#define PLLGPU         PLL_PACK(0x120, 1)
 
 /**
  * struct ddiv - Structure for dynamic switching divider
@@ -63,6 +64,7 @@ struct ddiv {
 #define CDDIV1_DIVCTL1 DDIV_PACK(CPG_CDDIV1, 4, 2, 5)
 #define CDDIV1_DIVCTL2 DDIV_PACK(CPG_CDDIV1, 8, 2, 6)
 #define CDDIV1_DIVCTL3 DDIV_PACK(CPG_CDDIV1, 12, 2, 7)
+#define CDDIV3_DIVCTL1 DDIV_PACK(CPG_CDDIV3, 4, 3, 13)
 #define CDDIV3_DIVCTL2 DDIV_PACK(CPG_CDDIV3, 8, 3, 14)
 #define CDDIV3_DIVCTL3 DDIV_PACK(CPG_CDDIV3, 12, 1, 15)
 #define CDDIV4_DIVCTL0 DDIV_PACK(CPG_CDDIV4, 0, 1, 16)