drm/amdgpu: fix the nullptr issue as for PWR IP not existing in discovery table

Fixes: c1cf79ca5ced46 ("drm/amdgpu: use IP discovery table for renoir")

This nullptr issue should be specific on the Renoir series during try access the PWR_MISC_CNTL_STATUS
when PWR IP not been detected by discovery table. Moreover the PWR IP not existing in Renoir series is
expected therefore just avoid access PWR register in Renoir series.

Signed-off-by: Prike.Liang <Prike.Liang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 22943773ae31c2ece6740e0525c99acef74c3b38..6b94587df407b63bd76e2683592bebee14b5aa15 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2856,8 +2856,8 @@ static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
                /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
                data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
                WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
-
-               pwr_10_0_gfxip_control_over_cgpg(adev, true);
+               if (adev->asic_type != CHIP_RENOIR)
+                       pwr_10_0_gfxip_control_over_cgpg(adev, true);
        }
 }