drm/amdgpu/display: Remove t_srx_delay_us.
authorBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Sun, 23 Jan 2022 02:38:28 +0000 (03:38 +0100)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 27 Jan 2022 20:47:34 +0000 (15:47 -0500)
Unused. Convert the divisions into asserts on the divisor, to
debug why it is zero. The divide by zero is suspected of causing
kernel panics.

While I have no idea where the zero is coming from I think this
patch is a positive either way.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c
drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

index ec19678a070213d85322cfdff065c4e0eb7f665a..e447c74be713826183e4619093fc791a84436f22 100644 (file)
@@ -503,7 +503,6 @@ static void dcn_bw_calc_rq_dlg_ttu(
        //input[in_idx].dout.output_standard;
 
        /*todo: soc->sr_enter_plus_exit_time??*/
-       dlg_sys_param->t_srx_delay_us = dc->dcn_ip->dcfclk_cstate_latency / v->dcf_clk_deep_sleep;
 
        dml1_rq_dlg_get_rq_params(dml, rq_param, &input->pipe.src);
        dml1_extract_rq_regs(dml, rq_regs, rq_param);
index 246071c72f6bf5ce2ceb1f29a5c2f6d075b26556..548cdef8a8ade2236445894e8743018acb893365 100644 (file)
@@ -1576,8 +1576,6 @@ void dml20_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
        dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib,
                        e2e_pipe_param,
                        num_pipes);
-       dlg_sys_param.t_srx_delay_us = mode_lib->ip.dcfclk_cstate_latency
-                       / dlg_sys_param.deepsleep_dcfclk_mhz; // TODO: Deprecated
 
        print__dlg_sys_params_st(mode_lib, &dlg_sys_param);
 
index 015e7f2c0b1602a7184f04c2ae670f6013f766ec..0fc9f3e3ffaefd2c3d56abec6734e701fab997c6 100644 (file)
@@ -1577,8 +1577,6 @@ void dml20v2_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
        dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib,
                        e2e_pipe_param,
                        num_pipes);
-       dlg_sys_param.t_srx_delay_us = mode_lib->ip.dcfclk_cstate_latency
-                       / dlg_sys_param.deepsleep_dcfclk_mhz; // TODO: Deprecated
 
        print__dlg_sys_params_st(mode_lib, &dlg_sys_param);
 
index 8bc27de4c104162cd8fa342ba7153785110e7692..618f4b682ab1b1c090a36867b4aabf764af518c0 100644 (file)
@@ -1688,8 +1688,6 @@ void dml21_rq_dlg_get_dlg_reg(
                        mode_lib,
                        e2e_pipe_param,
                        num_pipes);
-       dlg_sys_param.t_srx_delay_us = mode_lib->ip.dcfclk_cstate_latency
-                       / dlg_sys_param.deepsleep_dcfclk_mhz; // TODO: Deprecated
 
        print__dlg_sys_params_st(mode_lib, &dlg_sys_param);
 
index aef8542700544ddefa91dacb1d89b8d2337c91fa..747167083dea6cc0f4bf424df30e5cac3a2ca743 100644 (file)
@@ -1858,8 +1858,6 @@ void dml30_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
        dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib,
                e2e_pipe_param,
                num_pipes);
-       dlg_sys_param.t_srx_delay_us = mode_lib->ip.dcfclk_cstate_latency
-               / dlg_sys_param.deepsleep_dcfclk_mhz; // TODO: Deprecated
 
        print__dlg_sys_params_st(mode_lib, &dlg_sys_param);
 
index d46a2733024ce5aeb78a606ee16bb4cea277f1f7..8f9f1d607f7cb9aa43a57ae9660f257cba05ff7c 100644 (file)
@@ -546,7 +546,6 @@ struct _vcs_dpi_display_dlg_sys_params_st {
        double t_sr_wm_us;
        double t_extra_us;
        double mem_trip_us;
-       double t_srx_delay_us;
        double deepsleep_dcfclk_mhz;
        double total_flip_bw;
        unsigned int total_flip_bytes;
index 71ea503cb32fff48d0bb53a7f771ccf4335528b7..412e75eb47041abaef36ffcfb4d6c061ac46d15c 100644 (file)
@@ -141,9 +141,6 @@ void print__dlg_sys_params_st(struct display_mode_lib *mode_lib, const struct _v
        dml_print("DML_RQ_DLG_CALC:    t_urg_wm_us          = %3.2f\n", dlg_sys_param->t_urg_wm_us);
        dml_print("DML_RQ_DLG_CALC:    t_sr_wm_us           = %3.2f\n", dlg_sys_param->t_sr_wm_us);
        dml_print("DML_RQ_DLG_CALC:    t_extra_us           = %3.2f\n", dlg_sys_param->t_extra_us);
-       dml_print(
-                       "DML_RQ_DLG_CALC:    t_srx_delay_us       = %3.2f\n",
-                       dlg_sys_param->t_srx_delay_us);
        dml_print(
                        "DML_RQ_DLG_CALC:    deepsleep_dcfclk_mhz = %3.2f\n",
                        dlg_sys_param->deepsleep_dcfclk_mhz);
index 59dc2c5b58dd71da980c391bacf0897146de3185..3df559c591f890c1be146b5a0379f8ff4272b193 100644 (file)
@@ -1331,10 +1331,6 @@ void dml1_rq_dlg_get_dlg_params(
        if (dual_plane)
                DTRACE("DLG: %s: swath_height_c     = %d", __func__, swath_height_c);
 
-       DTRACE(
-                       "DLG: %s: t_srx_delay_us     = %3.2f",
-                       __func__,
-                       (double) dlg_sys_param->t_srx_delay_us);
        DTRACE("DLG: %s: line_time_in_us    = %3.2f", __func__, (double) line_time_in_us);
        DTRACE("DLG: %s: vupdate_offset     = %d", __func__, vupdate_offset);
        DTRACE("DLG: %s: vupdate_width      = %d", __func__, vupdate_width);